drivers/video/via/hw.c

   1 /*
   2  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
   3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
   4
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public
   7  * License as published by the Free Software Foundation;
   8  * either version 2, or (at your option) any later version.
   9
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
  12  * the implied warranty of MERCHANTABILITY or FITNESS FOR
  13  * A PARTICULAR PURPOSE.See the GNU General Public License
  14  * for more details.
  15
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc.,
  19  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20  */
  21 #include "via-core.h"
  22 #include "global.h"
  23
  24 static struct pll_map pll_value[] = {
  25         {CLK_25_175M, CLE266_PLL_25_175M, K800_PLL_25_175M,
  26          CX700_25_175M, VX855_25_175M},
  27         {CLK_29_581M, CLE266_PLL_29_581M, K800_PLL_29_581M,
  28          CX700_29_581M, VX855_29_581M},
  29         {CLK_26_880M, CLE266_PLL_26_880M, K800_PLL_26_880M,
  30          CX700_26_880M, VX855_26_880M},
  31         {CLK_31_490M, CLE266_PLL_31_490M, K800_PLL_31_490M,
  32          CX700_31_490M, VX855_31_490M},
  33         {CLK_31_500M, CLE266_PLL_31_500M, K800_PLL_31_500M,
  34          CX700_31_500M, VX855_31_500M},
  35         {CLK_31_728M, CLE266_PLL_31_728M, K800_PLL_31_728M,
  36          CX700_31_728M, VX855_31_728M},
  37         {CLK_32_668M, CLE266_PLL_32_668M, K800_PLL_32_668M,
  38          CX700_32_668M, VX855_32_668M},
  39         {CLK_36_000M, CLE266_PLL_36_000M, K800_PLL_36_000M,
  40          CX700_36_000M, VX855_36_000M},
  41         {CLK_40_000M, CLE266_PLL_40_000M, K800_PLL_40_000M,
  42          CX700_40_000M, VX855_40_000M},
  43         {CLK_41_291M, CLE266_PLL_41_291M, K800_PLL_41_291M,
  44          CX700_41_291M, VX855_41_291M},
  45         {CLK_43_163M, CLE266_PLL_43_163M, K800_PLL_43_163M,
  46          CX700_43_163M, VX855_43_163M},
  47         {CLK_45_250M, CLE266_PLL_45_250M, K800_PLL_45_250M,
  48          CX700_45_250M, VX855_45_250M},
  49         {CLK_46_000M, CLE266_PLL_46_000M, K800_PLL_46_000M,
  50          CX700_46_000M, VX855_46_000M},
  51         {CLK_46_996M, CLE266_PLL_46_996M, K800_PLL_46_996M,
  52          CX700_46_996M, VX855_46_996M},
  53         {CLK_48_000M, CLE266_PLL_48_000M, K800_PLL_48_000M,
  54          CX700_48_000M, VX855_48_000M},
  55         {CLK_48_875M, CLE266_PLL_48_875M, K800_PLL_48_875M,
  56          CX700_48_875M, VX855_48_875M},
  57         {CLK_49_500M, CLE266_PLL_49_500M, K800_PLL_49_500M,
  58          CX700_49_500M, VX855_49_500M},
  59         {CLK_52_406M, CLE266_PLL_52_406M, K800_PLL_52_406M,
  60          CX700_52_406M, VX855_52_406M},
  61         {CLK_52_977M, CLE266_PLL_52_977M, K800_PLL_52_977M,
  62          CX700_52_977M, VX855_52_977M},
  63         {CLK_56_250M, CLE266_PLL_56_250M, K800_PLL_56_250M,
  64          CX700_56_250M, VX855_56_250M},
  65         {CLK_57_275M, 0, 0, 0, VX855_57_275M},
  66         {CLK_60_466M, CLE266_PLL_60_466M, K800_PLL_60_466M,
  67          CX700_60_466M, VX855_60_466M},
  68         {CLK_61_500M, CLE266_PLL_61_500M, K800_PLL_61_500M,
  69          CX700_61_500M, VX855_61_500M},
  70         {CLK_65_000M, CLE266_PLL_65_000M, K800_PLL_65_000M,
  71          CX700_65_000M, VX855_65_000M},
  72         {CLK_65_178M, CLE266_PLL_65_178M, K800_PLL_65_178M,
  73          CX700_65_178M, VX855_65_178M},
  74         {CLK_66_750M, CLE266_PLL_66_750M, K800_PLL_66_750M,
  75          CX700_66_750M, VX855_66_750M},
  76         {CLK_68_179M, CLE266_PLL_68_179M, K800_PLL_68_179M,
  77          CX700_68_179M, VX855_68_179M},
  78         {CLK_69_924M, CLE266_PLL_69_924M, K800_PLL_69_924M,
  79          CX700_69_924M, VX855_69_924M},
  80         {CLK_70_159M, CLE266_PLL_70_159M, K800_PLL_70_159M,
  81          CX700_70_159M, VX855_70_159M},
  82         {CLK_72_000M, CLE266_PLL_72_000M, K800_PLL_72_000M,
  83          CX700_72_000M, VX855_72_000M},
  84         {CLK_78_750M, CLE266_PLL_78_750M, K800_PLL_78_750M,
  85          CX700_78_750M, VX855_78_750M},
  86         {CLK_80_136M, CLE266_PLL_80_136M, K800_PLL_80_136M,
  87          CX700_80_136M, VX855_80_136M},
  88         {CLK_83_375M, CLE266_PLL_83_375M, K800_PLL_83_375M,
  89          CX700_83_375M, VX855_83_375M},
  90         {CLK_83_950M, CLE266_PLL_83_950M, K800_PLL_83_950M,
  91          CX700_83_950M, VX855_83_950M},
  92         {CLK_84_750M, CLE266_PLL_84_750M, K800_PLL_84_750M,
  93          CX700_84_750M, VX855_84_750M},
  94         {CLK_85_860M, CLE266_PLL_85_860M, K800_PLL_85_860M,
  95          CX700_85_860M, VX855_85_860M},
  96         {CLK_88_750M, CLE266_PLL_88_750M, K800_PLL_88_750M,
  97          CX700_88_750M, VX855_88_750M},
  98         {CLK_94_500M, CLE266_PLL_94_500M, K800_PLL_94_500M,
  99          CX700_94_500M, VX855_94_500M},
 100         {CLK_97_750M, CLE266_PLL_97_750M, K800_PLL_97_750M,
 101          CX700_97_750M, VX855_97_750M},
 102         {CLK_101_000M, CLE266_PLL_101_000M, K800_PLL_101_000M,
 103          CX700_101_000M, VX855_101_000M},
 104         {CLK_106_500M, CLE266_PLL_106_500M, K800_PLL_106_500M,
 105          CX700_106_500M, VX855_106_500M},
 106         {CLK_108_000M, CLE266_PLL_108_000M, K800_PLL_108_000M,
 107          CX700_108_000M, VX855_108_000M},
 108         {CLK_113_309M, CLE266_PLL_113_309M, K800_PLL_113_309M,
 109          CX700_113_309M, VX855_113_309M},
 110         {CLK_118_840M, CLE266_PLL_118_840M, K800_PLL_118_840M,
 111          CX700_118_840M, VX855_118_840M},
 112         {CLK_119_000M, CLE266_PLL_119_000M, K800_PLL_119_000M,
 113          CX700_119_000M, VX855_119_000M},
 114         {CLK_121_750M, CLE266_PLL_121_750M, K800_PLL_121_750M,
 115          CX700_121_750M, 0},
 116         {CLK_125_104M, CLE266_PLL_125_104M, K800_PLL_125_104M,
 117          CX700_125_104M, 0},
 118         {CLK_133_308M, CLE266_PLL_133_308M, K800_PLL_133_308M,
 119          CX700_133_308M, 0},
 120         {CLK_135_000M, CLE266_PLL_135_000M, K800_PLL_135_000M,
 121          CX700_135_000M, VX855_135_000M},
 122         {CLK_136_700M, CLE266_PLL_136_700M, K800_PLL_136_700M,
 123          CX700_136_700M, VX855_136_700M},
 124         {CLK_138_400M, CLE266_PLL_138_400M, K800_PLL_138_400M,
 125          CX700_138_400M, VX855_138_400M},
 126         {CLK_146_760M, CLE266_PLL_146_760M, K800_PLL_146_760M,
 127          CX700_146_760M, VX855_146_760M},
 128         {CLK_153_920M, CLE266_PLL_153_920M, K800_PLL_153_920M,
 129          CX700_153_920M, VX855_153_920M},
 130         {CLK_156_000M, CLE266_PLL_156_000M, K800_PLL_156_000M,
 131          CX700_156_000M, VX855_156_000M},
 132         {CLK_157_500M, CLE266_PLL_157_500M, K800_PLL_157_500M,
 133          CX700_157_500M, VX855_157_500M},
 134         {CLK_162_000M, CLE266_PLL_162_000M, K800_PLL_162_000M,
 135          CX700_162_000M, VX855_162_000M},
 136         {CLK_187_000M, CLE266_PLL_187_000M, K800_PLL_187_000M,
 137          CX700_187_000M, VX855_187_000M},
 138         {CLK_193_295M, CLE266_PLL_193_295M, K800_PLL_193_295M,
 139          CX700_193_295M, VX855_193_295M},
 140         {CLK_202_500M, CLE266_PLL_202_500M, K800_PLL_202_500M,
 141          CX700_202_500M, VX855_202_500M},
 142         {CLK_204_000M, CLE266_PLL_204_000M, K800_PLL_204_000M,
 143          CX700_204_000M, VX855_204_000M},
 144         {CLK_218_500M, CLE266_PLL_218_500M, K800_PLL_218_500M,
 145          CX700_218_500M, VX855_218_500M},
 146         {CLK_234_000M, CLE266_PLL_234_000M, K800_PLL_234_000M,
 147          CX700_234_000M, VX855_234_000M},
 148         {CLK_267_250M, CLE266_PLL_267_250M, K800_PLL_267_250M,
 149          CX700_267_250M, VX855_267_250M},
 150         {CLK_297_500M, CLE266_PLL_297_500M, K800_PLL_297_500M,
 151          CX700_297_500M, VX855_297_500M},
 152         {CLK_74_481M, CLE266_PLL_74_481M, K800_PLL_74_481M,
 153          CX700_74_481M, VX855_74_481M},
 154         {CLK_172_798M, CLE266_PLL_172_798M, K800_PLL_172_798M,
 155          CX700_172_798M, VX855_172_798M},
 156         {CLK_122_614M, CLE266_PLL_122_614M, K800_PLL_122_614M,
 157          CX700_122_614M, VX855_122_614M},
 158         {CLK_74_270M, CLE266_PLL_74_270M, K800_PLL_74_270M,
 159          CX700_74_270M, 0},
 160         {CLK_148_500M, CLE266_PLL_148_500M, K800_PLL_148_500M,
 161          CX700_148_500M, VX855_148_500M}
 162 };
 163
 164 static struct fifo_depth_select display_fifo_depth_reg = {
 165         /* IGA1 FIFO Depth_Select */
 166         {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } },
 167         /* IGA2 FIFO Depth_Select */
 168         {IGA2_FIFO_DEPTH_SELECT_REG_NUM,
 169          {{CR68, 4, 7}, {CR94, 7, 7}, {CR95, 7, 7} } }
 170 };
 171
 172 static struct fifo_threshold_select fifo_threshold_select_reg = {
 173         /* IGA1 FIFO Threshold Select */
 174         {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } },
 175         /* IGA2 FIFO Threshold Select */
 176         {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68, 0, 3}, {CR95, 4, 6} } }
 177 };
 178
 179 static struct fifo_high_threshold_select fifo_high_threshold_select_reg = {
 180         /* IGA1 FIFO High Threshold Select */
 181         {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18, 0, 5}, {SR18, 7, 7} } },
 182         /* IGA2 FIFO High Threshold Select */
 183         {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92, 0, 3}, {CR95, 0, 2} } }
 184 };
 185
 186 static struct display_queue_expire_num display_queue_expire_num_reg = {
 187         /* IGA1 Display Queue Expire Num */
 188         {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22, 0, 4} } },
 189         /* IGA2 Display Queue Expire Num */
 190         {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94, 0, 6} } }
 191 };
 192
 193 /* Definition Fetch Count Registers*/
 194 static struct fetch_count fetch_count_reg = {
 195         /* IGA1 Fetch Count Register */
 196         {IGA1_FETCH_COUNT_REG_NUM, {{SR1C, 0, 7}, {SR1D, 0, 1} } },
 197         /* IGA2 Fetch Count Register */
 198         {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } }
 199 };
 200
 201 static struct iga1_crtc_timing iga1_crtc_reg = {
 202         /* IGA1 Horizontal Total */
 203         {IGA1_HOR_TOTAL_REG_NUM, {{CR00, 0, 7}, {CR36, 3, 3} } },
 204         /* IGA1 Horizontal Addressable Video */
 205         {IGA1_HOR_ADDR_REG_NUM, {{CR01, 0, 7} } },
 206         /* IGA1 Horizontal Blank Start */
 207         {IGA1_HOR_BLANK_START_REG_NUM, {{CR02, 0, 7} } },
 208         /* IGA1 Horizontal Blank End */
 209         {IGA1_HOR_BLANK_END_REG_NUM,
 210          {{CR03, 0, 4}, {CR05, 7, 7}, {CR33, 5, 5} } },
 211         /* IGA1 Horizontal Sync Start */
 212         {IGA1_HOR_SYNC_START_REG_NUM, {{CR04, 0, 7}, {CR33, 4, 4} } },
 213         /* IGA1 Horizontal Sync End */
 214         {IGA1_HOR_SYNC_END_REG_NUM, {{CR05, 0, 4} } },
 215         /* IGA1 Vertical Total */
 216         {IGA1_VER_TOTAL_REG_NUM,
 217          {{CR06, 0, 7}, {CR07, 0, 0}, {CR07, 5, 5}, {CR35, 0, 0} } },
 218         /* IGA1 Vertical Addressable Video */
 219         {IGA1_VER_ADDR_REG_NUM,
 220          {{CR12, 0, 7}, {CR07, 1, 1}, {CR07, 6, 6}, {CR35, 2, 2} } },
 221         /* IGA1 Vertical Blank Start */
 222         {IGA1_VER_BLANK_START_REG_NUM,
 223          {{CR15, 0, 7}, {CR07, 3, 3}, {CR09, 5, 5}, {CR35, 3, 3} } },
 224         /* IGA1 Vertical Blank End */
 225         {IGA1_VER_BLANK_END_REG_NUM, {{CR16, 0, 7} } },
 226         /* IGA1 Vertical Sync Start */
 227         {IGA1_VER_SYNC_START_REG_NUM,
 228          {{CR10, 0, 7}, {CR07, 2, 2}, {CR07, 7, 7}, {CR35, 1, 1} } },
 229         /* IGA1 Vertical Sync End */
 230         {IGA1_VER_SYNC_END_REG_NUM, {{CR11, 0, 3} } }
 231 };
 232
 233 static struct iga2_crtc_timing iga2_crtc_reg = {
 234         /* IGA2 Horizontal Total */
 235         {IGA2_HOR_TOTAL_REG_NUM, {{CR50, 0, 7}, {CR55, 0, 3} } },
 236         /* IGA2 Horizontal Addressable Video */
 237         {IGA2_HOR_ADDR_REG_NUM, {{CR51, 0, 7}, {CR55, 4, 6} } },
 238         /* IGA2 Horizontal Blank Start */
 239         {IGA2_HOR_BLANK_START_REG_NUM, {{CR52, 0, 7}, {CR54, 0, 2} } },
 240         /* IGA2 Horizontal Blank End */
 241         {IGA2_HOR_BLANK_END_REG_NUM,
 242          {{CR53, 0, 7}, {CR54, 3, 5}, {CR5D, 6, 6} } },
 243         /* IGA2 Horizontal Sync Start */
 244         {IGA2_HOR_SYNC_START_REG_NUM,
 245          {{CR56, 0, 7}, {CR54, 6, 7}, {CR5C, 7, 7}, {CR5D, 7, 7} } },
 246         /* IGA2 Horizontal Sync End */
 247         {IGA2_HOR_SYNC_END_REG_NUM, {{CR57, 0, 7}, {CR5C, 6, 6} } },
 248         /* IGA2 Vertical Total */
 249         {IGA2_VER_TOTAL_REG_NUM, {{CR58, 0, 7}, {CR5D, 0, 2} } },
 250         /* IGA2 Vertical Addressable Video */
 251         {IGA2_VER_ADDR_REG_NUM, {{CR59, 0, 7}, {CR5D, 3, 5} } },
 252         /* IGA2 Vertical Blank Start */
 253         {IGA2_VER_BLANK_START_REG_NUM, {{CR5A, 0, 7}, {CR5C, 0, 2} } },
 254         /* IGA2 Vertical Blank End */
 255         {IGA2_VER_BLANK_END_REG_NUM, {{CR5B, 0, 7}, {CR5C, 3, 5} } },
 256         /* IGA2 Vertical Sync Start */
 257         {IGA2_VER_SYNC_START_REG_NUM, {{CR5E, 0, 7}, {CR5F, 5, 7} } },
 258         /* IGA2 Vertical Sync End */
 259         {IGA2_VER_SYNC_END_REG_NUM, {{CR5F, 0, 4} } }
 260 };
 261
 262 static struct rgbLUT palLUT_table[] = {
 263         /* {R,G,B} */
 264         /* Index 0x00~0x03 */
 265         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00,
 266                                                                      0x2A,
 267                                                                      0x2A},
 268         /* Index 0x04~0x07 */
 269         {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A,
 270                                                                      0x2A,
 271                                                                      0x2A},
 272         /* Index 0x08~0x0B */
 273         {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15,
 274                                                                      0x3F,
 275                                                                      0x3F},
 276         /* Index 0x0C~0x0F */
 277         {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F,
 278                                                                      0x3F,
 279                                                                      0x3F},
 280         /* Index 0x10~0x13 */
 281         {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B,
 282                                                                      0x0B,
 283                                                                      0x0B},
 284         /* Index 0x14~0x17 */
 285         {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18,
 286                                                                      0x18,
 287                                                                      0x18},
 288         /* Index 0x18~0x1B */
 289         {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28,
 290                                                                      0x28,
 291                                                                      0x28},
 292         /* Index 0x1C~0x1F */
 293         {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F,
 294                                                                      0x3F,
 295                                                                      0x3F},
 296         /* Index 0x20~0x23 */
 297         {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F,
 298                                                                      0x00,
 299                                                                      0x3F},
 300         /* Index 0x24~0x27 */
 301         {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F,
 302                                                                      0x00,
 303                                                                      0x10},
 304         /* Index 0x28~0x2B */
 305         {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F,
 306                                                                      0x2F,
 307                                                                      0x00},
 308         /* Index 0x2C~0x2F */
 309         {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10,
 310                                                                      0x3F,
 311                                                                      0x00},
 312         /* Index 0x30~0x33 */
 313         {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00,
 314                                                                      0x3F,
 315                                                                      0x2F},
 316         /* Index 0x34~0x37 */
 317         {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00,
 318                                                                      0x10,
 319                                                                      0x3F},
 320         /* Index 0x38~0x3B */
 321         {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37,
 322                                                                      0x1F,
 323                                                                      0x3F},
 324         /* Index 0x3C~0x3F */
 325         {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F,
 326                                                                      0x1F,
 327                                                                      0x27},
 328         /* Index 0x40~0x43 */
 329         {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F,
 330                                                                      0x3F,
 331                                                                      0x1F},
 332         /* Index 0x44~0x47 */
 333         {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27,
 334                                                                      0x3F,
 335                                                                      0x1F},
 336         /* Index 0x48~0x4B */
 337         {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F,
 338                                                                      0x3F,
 339                                                                      0x37},
 340         /* Index 0x4C~0x4F */
 341         {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F,
 342                                                                      0x27,
 343                                                                      0x3F},
 344         /* Index 0x50~0x53 */
 345         {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A,
 346                                                                      0x2D,
 347                                                                      0x3F},
 348         /* Index 0x54~0x57 */
 349         {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F,
 350                                                                      0x2D,
 351                                                                      0x31},
 352         /* Index 0x58~0x5B */
 353         {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F,
 354                                                                      0x3A,
 355                                                                      0x2D},
 356         /* Index 0x5C~0x5F */
 357         {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31,
 358                                                                      0x3F,
 359                                                                      0x2D},
 360         /* Index 0x60~0x63 */
 361         {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D,
 362                                                                      0x3F,
 363                                                                      0x3A},
 364         /* Index 0x64~0x67 */
 365         {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D,
 366                                                                      0x31,
 367                                                                      0x3F},
 368         /* Index 0x68~0x6B */
 369         {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15,
 370                                                                      0x00,
 371                                                                      0x1C},
 372         /* Index 0x6C~0x6F */
 373         {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C,
 374                                                                      0x00,
 375                                                                      0x07},
 376         /* Index 0x70~0x73 */
 377         {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C,
 378                                                                      0x15,
 379                                                                      0x00},
 380         /* Index 0x74~0x77 */
 381         {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07,
 382                                                                      0x1C,
 383                                                                      0x00},
 384         /* Index 0x78~0x7B */
 385         {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00,
 386                                                                      0x1C,
 387                                                                      0x15},
 388         /* Index 0x7C~0x7F */
 389         {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00,
 390                                                                      0x07,
 391                                                                      0x1C},
 392         /* Index 0x80~0x83 */
 393         {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18,
 394                                                                      0x0E,
 395                                                                      0x1C},
 396         /* Index 0x84~0x87 */
 397         {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C,
 398                                                                      0x0E,
 399                                                                      0x11},
 400         /* Index 0x88~0x8B */
 401         {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C,
 402                                                                      0x18,
 403                                                                      0x0E},
 404         /* Index 0x8C~0x8F */
 405         {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11,
 406                                                                      0x1C,
 407                                                                      0x0E},
 408         /* Index 0x90~0x93 */
 409         {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E,
 410                                                                      0x1C,
 411                                                                      0x18},
 412         /* Index 0x94~0x97 */
 413         {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E,
 414                                                                      0x11,
 415                                                                      0x1C},
 416         /* Index 0x98~0x9B */
 417         {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A,
 418                                                                      0x14,
 419                                                                      0x1C},
 420         /* Index 0x9C~0x9F */
 421         {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C,
 422                                                                      0x14,
 423                                                                      0x16},
 424         /* Index 0xA0~0xA3 */
 425         {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C,
 426                                                                      0x1A,
 427                                                                      0x14},
 428         /* Index 0xA4~0xA7 */
 429         {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16,
 430                                                                      0x1C,
 431                                                                      0x14},
 432         /* Index 0xA8~0xAB */
 433         {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14,
 434                                                                      0x1C,
 435                                                                      0x1A},
 436         /* Index 0xAC~0xAF */
 437         {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14,
 438                                                                      0x16,
 439                                                                      0x1C},
 440         /* Index 0xB0~0xB3 */
 441         {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C,
 442                                                                      0x00,
 443                                                                      0x10},
 444         /* Index 0xB4~0xB7 */
 445         {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10,
 446                                                                      0x00,
 447                                                                      0x04},
 448         /* Index 0xB8~0xBB */
 449         {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10,
 450                                                                      0x0C,
 451                                                                      0x00},
 452         /* Index 0xBC~0xBF */
 453         {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04,
 454                                                                      0x10,
 455                                                                      0x00},
 456         /* Index 0xC0~0xC3 */
 457         {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00,
 458                                                                      0x10,
 459                                                                      0x0C},
 460         /* Index 0xC4~0xC7 */
 461         {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00,
 462                                                                      0x04,
 463                                                                      0x10},
 464         /* Index 0xC8~0xCB */
 465         {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E,
 466                                                                      0x08,
 467                                                                      0x10},
 468         /* Index 0xCC~0xCF */
 469         {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10,
 470                                                                      0x08,
 471                                                                      0x0A},
 472         /* Index 0xD0~0xD3 */
 473         {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10,
 474                                                                      0x0E,
 475                                                                      0x08},
 476         /* Index 0xD4~0xD7 */
 477         {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A,
 478                                                                      0x10,
 479                                                                      0x08},
 480         /* Index 0xD8~0xDB */
 481         {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08,
 482                                                                      0x10,
 483                                                                      0x0E},
 484         /* Index 0xDC~0xDF */
 485         {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08,
 486                                                                      0x0A,
 487                                                                      0x10},
 488         /* Index 0xE0~0xE3 */
 489         {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F,
 490                                                                      0x0B,
 491                                                                      0x10},
 492         /* Index 0xE4~0xE7 */
 493         {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10,
 494                                                                      0x0B,
 495                                                                      0x0C},
 496         /* Index 0xE8~0xEB */
 497         {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10,
 498                                                                      0x0F,
 499                                                                      0x0B},
 500         /* Index 0xEC~0xEF */
 501         {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C,
 502                                                                      0x10,
 503                                                                      0x0B},
 504         /* Index 0xF0~0xF3 */
 505         {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B,
 506                                                                      0x10,
 507                                                                      0x0F},
 508         /* Index 0xF4~0xF7 */
 509         {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B,
 510                                                                      0x0C,
 511                                                                      0x10},
 512         /* Index 0xF8~0xFB */
 513         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
 514                                                                      0x00,
 515                                                                      0x00},
 516         /* Index 0xFC~0xFF */
 517         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
 518                                                                      0x00,
 519                                                                      0x00}
 520 };
 521
 522 static void set_crt_output_path(int set_iga);
 523 static void dvi_patch_skew_dvp0(void);
 524 static void dvi_patch_skew_dvp1(void);
 525 static void dvi_patch_skew_dvp_low(void);
 526 static void set_dvi_output_path(int set_iga, int output_interface);
 527 static void set_lcd_output_path(int set_iga, int output_interface);
 528 static void load_fix_bit_crtc_reg(void);
 529 static void init_gfx_chip_info(int chip_type);
 530 static void init_tmds_chip_info(void);
 531 static void init_lvds_chip_info(void);
 532 static void device_screen_off(void);
 533 static void device_screen_on(void);
 534 static void set_display_channel(void);
 535 static void device_off(void);
 536 static void device_on(void);
 537 static void enable_second_display_channel(void);
 538 static void disable_second_display_channel(void);
 539
 540 void viafb_lock_crt(void)
 541 {
 542         viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);
 543 }
 544
 545 void viafb_unlock_crt(void)
 546 {
 547         viafb_write_reg_mask(CR11, VIACR, 0, BIT7);
 548         viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
 549 }
 550
 551 void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
 552 {
 553         outb(index, LUT_INDEX_WRITE);
 554         outb(r, LUT_DATA);
 555         outb(g, LUT_DATA);
 556         outb(b, LUT_DATA);
 557 }
 558
 559 /*Set IGA path for each device*/
 560 void viafb_set_iga_path(void)
 561 {
 562
 563         if (viafb_SAMM_ON == 1) {
 564                 if (viafb_CRT_ON) {
 565                         if (viafb_primary_dev == CRT_Device)
 566                                 viaparinfo->crt_setting_info->iga_path = IGA1;
 567                         else
 568                                 viaparinfo->crt_setting_info->iga_path = IGA2;
 569                 }
 570
 571                 if (viafb_DVI_ON) {
 572                         if (viafb_primary_dev == DVI_Device)
 573                                 viaparinfo->tmds_setting_info->iga_path = IGA1;
 574                         else
 575                                 viaparinfo->tmds_setting_info->iga_path = IGA2;
 576                 }
 577
 578                 if (viafb_LCD_ON) {
 579                         if (viafb_primary_dev == LCD_Device) {
 580                                 if (viafb_dual_fb &&
 581                                         (viaparinfo->chip_info->gfx_chip_name ==
 582                                         UNICHROME_CLE266)) {
 583                                         viaparinfo->
 584                                         lvds_setting_info->iga_path = IGA2;
 585                                         viaparinfo->
 586                                         crt_setting_info->iga_path = IGA1;
 587                                         viaparinfo->
 588                                         tmds_setting_info->iga_path = IGA1;
 589                                 } else
 590                                         viaparinfo->
 591                                         lvds_setting_info->iga_path = IGA1;
 592                         } else {
 593                                 viaparinfo->lvds_setting_info->iga_path = IGA2;
 594                         }
 595                 }
 596                 if (viafb_LCD2_ON) {
 597                         if (LCD2_Device == viafb_primary_dev)
 598                                 viaparinfo->lvds_setting_info2->iga_path = IGA1;
 599                         else
 600                                 viaparinfo->lvds_setting_info2->iga_path = IGA2;
 601                 }
 602         } else {
 603                 viafb_SAMM_ON = 0;
 604
 605                 if (viafb_CRT_ON && viafb_LCD_ON) {
 606                         viaparinfo->crt_setting_info->iga_path = IGA1;
 607                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 608                 } else if (viafb_CRT_ON && viafb_DVI_ON) {
 609                         viaparinfo->crt_setting_info->iga_path = IGA1;
 610                         viaparinfo->tmds_setting_info->iga_path = IGA2;
 611                 } else if (viafb_LCD_ON && viafb_DVI_ON) {
 612                         viaparinfo->tmds_setting_info->iga_path = IGA1;
 613                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 614                 } else if (viafb_LCD_ON && viafb_LCD2_ON) {
 615                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 616                         viaparinfo->lvds_setting_info2->iga_path = IGA2;
 617                 } else if (viafb_CRT_ON) {
 618                         viaparinfo->crt_setting_info->iga_path = IGA1;
 619                 } else if (viafb_LCD_ON) {
 620                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 621                 } else if (viafb_DVI_ON) {
 622                         viaparinfo->tmds_setting_info->iga_path = IGA1;
 623                 }
 624         }
 625 }
 626
 627 static void set_color_register(u8 index, u8 red, u8 green, u8 blue)
 628 {
 629         outb(0xFF, 0x3C6); /* bit mask of palette */
 630         outb(index, 0x3C8);
 631         outb(red, 0x3C9);
 632         outb(green, 0x3C9);
 633         outb(blue, 0x3C9);
 634 }
 635
 636 void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue)
 637 {
 638         viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01);
 639         set_color_register(index, red, green, blue);
 640 }
 641
 642 void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue)
 643 {
 644         viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01);
 645         set_color_register(index, red, green, blue);
 646 }
 647
 648 void viafb_set_output_path(int device, int set_iga, int output_interface)
 649 {
 650         switch (device) {
 651         case DEVICE_CRT:
 652                 set_crt_output_path(set_iga);
 653                 break;
 654         case DEVICE_DVI:
 655                 set_dvi_output_path(set_iga, output_interface);
 656                 break;
 657         case DEVICE_LCD:
 658                 set_lcd_output_path(set_iga, output_interface);
 659                 break;
 660         }
 661 }
 662
 663 static void set_crt_output_path(int set_iga)
 664 {
 665         viafb_write_reg_mask(CR36, VIACR, 0x00, BIT4 + BIT5);
 666
 667         switch (set_iga) {
 668         case IGA1:
 669                 viafb_write_reg_mask(SR16, VIASR, 0x00, BIT6);
 670                 break;
 671         case IGA2:
 672                 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
 673                 viafb_write_reg_mask(SR16, VIASR, 0x40, BIT6);
 674                 break;
 675         }
 676 }
 677
 678 static void dvi_patch_skew_dvp0(void)
 679 {
 680         /* Reset data driving first: */
 681         viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);
 682         viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);
 683
 684         switch (viaparinfo->chip_info->gfx_chip_name) {
 685         case UNICHROME_P4M890:
 686                 {
 687                         if ((viaparinfo->tmds_setting_info->h_active == 1600) &&
 688                                 (viaparinfo->tmds_setting_info->v_active ==
 689                                 1200))
 690                                 viafb_write_reg_mask(CR96, VIACR, 0x03,
 691                                                BIT0 + BIT1 + BIT2);
 692                         else
 693                                 viafb_write_reg_mask(CR96, VIACR, 0x07,
 694                                                BIT0 + BIT1 + BIT2);
 695                         break;
 696                 }
 697
 698         case UNICHROME_P4M900:
 699                 {
 700                         viafb_write_reg_mask(CR96, VIACR, 0x07,
 701                                        BIT0 + BIT1 + BIT2 + BIT3);
 702                         viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);
 703                         viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);
 704                         break;
 705                 }
 706
 707         default:
 708                 {
 709                         break;
 710                 }
 711         }
 712 }
 713
 714 static void dvi_patch_skew_dvp1(void)
 715 {
 716         switch (viaparinfo->chip_info->gfx_chip_name) {
 717         case UNICHROME_CX700:
 718                 {
 719                         break;
 720                 }
 721
 722         default:
 723                 {
 724                         break;
 725                 }
 726         }
 727 }
 728
 729 static void dvi_patch_skew_dvp_low(void)
 730 {
 731         switch (viaparinfo->chip_info->gfx_chip_name) {
 732         case UNICHROME_K8M890:
 733                 {
 734                         viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
 735                         break;
 736                 }
 737
 738         case UNICHROME_P4M900:
 739                 {
 740                         viafb_write_reg_mask(CR99, VIACR, 0x08,
 741                                        BIT0 + BIT1 + BIT2 + BIT3);
 742                         break;
 743                 }
 744
 745         case UNICHROME_P4M890:
 746                 {
 747                         viafb_write_reg_mask(CR99, VIACR, 0x0F,
 748                                        BIT0 + BIT1 + BIT2 + BIT3);
 749                         break;
 750                 }
 751
 752         default:
 753                 {
 754                         break;
 755                 }
 756         }
 757 }
 758
 759 static void set_dvi_output_path(int set_iga, int output_interface)
 760 {
 761         switch (output_interface) {
 762         case INTERFACE_DVP0:
 763                 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);
 764
 765                 if (set_iga == IGA1) {
 766                         viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
 767                         viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 +
 768                                 BIT5 + BIT7);
 769                 } else {
 770                         viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
 771                         viafb_write_reg_mask(CR6C, VIACR, 0xA1, BIT0 +
 772                                 BIT5 + BIT7);
 773                 }
 774
 775                 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT7 + BIT6);
 776
 777                 dvi_patch_skew_dvp0();
 778                 break;
 779
 780         case INTERFACE_DVP1:
 781                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
 782                         if (set_iga == IGA1)
 783                                 viafb_write_reg_mask(CR93, VIACR, 0x21,
 784                                                BIT0 + BIT5 + BIT7);
 785                         else
 786                                 viafb_write_reg_mask(CR93, VIACR, 0xA1,
 787                                                BIT0 + BIT5 + BIT7);
 788                 } else {
 789                         if (set_iga == IGA1)
 790                                 viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
 791                         else
 792                                 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
 793                 }
 794
 795                 viafb_write_reg_mask(SR1E, VIASR, 0x30, BIT4 + BIT5);
 796                 dvi_patch_skew_dvp1();
 797                 break;
 798         case INTERFACE_DFP_HIGH:
 799                 if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266) {
 800                         if (set_iga == IGA1) {
 801                                 viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
 802                                 viafb_write_reg_mask(CR97, VIACR, 0x03,
 803                                                BIT0 + BIT1 + BIT4);
 804                         } else {
 805                                 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
 806                                 viafb_write_reg_mask(CR97, VIACR, 0x13,
 807                                                BIT0 + BIT1 + BIT4);
 808                         }
 809                 }
 810                 viafb_write_reg_mask(SR2A, VIASR, 0x0C, BIT2 + BIT3);
 811                 break;
 812
 813         case INTERFACE_DFP_LOW:
 814                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
 815                         break;
 816
 817                 if (set_iga == IGA1) {
 818                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
 819                         viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
 820                 } else {
 821                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
 822                         viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
 823                 }
 824
 825                 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
 826                 dvi_patch_skew_dvp_low();
 827                 break;
 828
 829         case INTERFACE_TMDS:
 830                 if (set_iga == IGA1)
 831                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
 832                 else
 833                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
 834                 break;
 835         }
 836
 837         if (set_iga == IGA2) {
 838                 enable_second_display_channel();
 839                 /* Disable LCD Scaling */
 840                 viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);
 841         }
 842 }
 843
 844 static void set_lcd_output_path(int set_iga, int output_interface)
 845 {
 846         DEBUG_MSG(KERN_INFO
 847                   "set_lcd_output_path, iga:%d,out_interface:%d\n",
 848                   set_iga, output_interface);
 849         switch (set_iga) {
 850         case IGA1:
 851                 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
 852                 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
 853
 854                 disable_second_display_channel();
 855                 break;
 856
 857         case IGA2:
 858                 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
 859                 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
 860
 861                 enable_second_display_channel();
 862                 break;
 863         }
 864
 865         switch (output_interface) {
 866         case INTERFACE_DVP0:
 867                 if (set_iga == IGA1) {
 868                         viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
 869                 } else {
 870                         viafb_write_reg(CR91, VIACR, 0x00);
 871                         viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
 872                 }
 873                 break;
 874
 875         case INTERFACE_DVP1:
 876                 if (set_iga == IGA1)
 877                         viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
 878                 else {
 879                         viafb_write_reg(CR91, VIACR, 0x00);
 880                         viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
 881                 }
 882                 break;
 883
 884         case INTERFACE_DFP_HIGH:
 885                 if (set_iga == IGA1)
 886                         viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
 887                 else {
 888                         viafb_write_reg(CR91, VIACR, 0x00);
 889                         viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
 890                         viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
 891                 }
 892                 break;
 893
 894         case INTERFACE_DFP_LOW:
 895                 if (set_iga == IGA1)
 896                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
 897                 else {
 898                         viafb_write_reg(CR91, VIACR, 0x00);
 899                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
 900                         viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
 901                 }
 902
 903                 break;
 904
 905         case INTERFACE_DFP:
 906                 if ((UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name)
 907                     || (UNICHROME_P4M890 ==
 908                     viaparinfo->chip_info->gfx_chip_name))
 909                         viafb_write_reg_mask(CR97, VIACR, 0x84,
 910                                        BIT7 + BIT2 + BIT1 + BIT0);
 911                 if (set_iga == IGA1) {
 912                         viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
 913                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
 914                 } else {
 915                         viafb_write_reg(CR91, VIACR, 0x00);
 916                         viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
 917                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
 918                 }
 919                 break;
 920
 921         case INTERFACE_LVDS0:
 922         case INTERFACE_LVDS0LVDS1:
 923                 if (set_iga == IGA1)
 924                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
 925                 else
 926                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
 927
 928                 break;
 929
 930         case INTERFACE_LVDS1:
 931                 if (set_iga == IGA1)
 932                         viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
 933                 else
 934                         viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
 935                 break;
 936         }
 937 }
 938
 939 static void load_fix_bit_crtc_reg(void)
 940 {
 941         /* always set to 1 */
 942         viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
 943         /* line compare should set all bits = 1 (extend modes) */
 944         viafb_write_reg(CR18, VIACR, 0xff);
 945         /* line compare should set all bits = 1 (extend modes) */
 946         viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4);
 947         /* line compare should set all bits = 1 (extend modes) */
 948         viafb_write_reg_mask(CR09, VIACR, 0x40, BIT6);
 949         /* line compare should set all bits = 1 (extend modes) */
 950         viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
 951         /* line compare should set all bits = 1 (extend modes) */
 952         viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
 953         /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */
 954         /* extend mode always set to e3h */
 955         viafb_write_reg(CR17, VIACR, 0xe3);
 956         /* extend mode always set to 0h */
 957         viafb_write_reg(CR08, VIACR, 0x00);
 958         /* extend mode always set to 0h */
 959         viafb_write_reg(CR14, VIACR, 0x00);
 960
 961         /* If K8M800, enable Prefetch Mode. */
 962         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
 963                 || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890))
 964                 viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);
 965         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
 966             && (viaparinfo->chip_info->gfx_chip_revision == CLE266_REVISION_AX))
 967                 viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);
 968
 969 }
 970
 971 void viafb_load_reg(int timing_value, int viafb_load_reg_num,
 972         struct io_register *reg,
 973               int io_type)
 974 {
 975         int reg_mask;
 976         int bit_num = 0;
 977         int data;
 978         int i, j;
 979         int shift_next_reg;
 980         int start_index, end_index, cr_index;
 981         u16 get_bit;
 982
 983         for (i = 0; i < viafb_load_reg_num; i++) {
 984                 reg_mask = 0;
 985                 data = 0;
 986                 start_index = reg[i].start_bit;
 987                 end_index = reg[i].end_bit;
 988                 cr_index = reg[i].io_addr;
 989
 990                 shift_next_reg = bit_num;
 991                 for (j = start_index; j <= end_index; j++) {
 992                         /*if (bit_num==8) timing_value = timing_value >>8; */
 993                         reg_mask = reg_mask | (BIT0 << j);
 994                         get_bit = (timing_value & (BIT0 << bit_num));
 995                         data =
 996                             data | ((get_bit >> shift_next_reg) << start_index);
 997                         bit_num++;
 998                 }
 999                 if (io_type == VIACR)
1000                         viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);
1001                 else
1002                         viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);
1003         }
1004
1005 }
1006
1007 /* Write Registers */
1008 void viafb_write_regx(struct io_reg RegTable[], int ItemNum)
1009 {
1010         int i;
1011         unsigned char RegTemp;
1012
1013         /*DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum ); */
1014
1015         for (i = 0; i < ItemNum; i++) {
1016                 outb(RegTable[i].index, RegTable[i].port);
1017                 RegTemp = inb(RegTable[i].port + 1);
1018                 RegTemp = (RegTemp & (~RegTable[i].mask)) | RegTable[i].value;
1019                 outb(RegTemp, RegTable[i].port + 1);
1020         }
1021 }
1022
1023 void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga)
1024 {
1025         int reg_value;
1026         int viafb_load_reg_num;
1027         struct io_register *reg = NULL;
1028
1029         switch (set_iga) {
1030         case IGA1:
1031                 reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1032                 viafb_load_reg_num = fetch_count_reg.
1033                         iga1_fetch_count_reg.reg_num;
1034                 reg = fetch_count_reg.iga1_fetch_count_reg.reg;
1035                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1036                 break;
1037         case IGA2:
1038                 reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1039                 viafb_load_reg_num = fetch_count_reg.
1040                         iga2_fetch_count_reg.reg_num;
1041                 reg = fetch_count_reg.iga2_fetch_count_reg.reg;
1042                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1043                 break;
1044         }
1045
1046 }
1047
1048 void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1049 {
1050         int reg_value;
1051         int viafb_load_reg_num;
1052         struct io_register *reg = NULL;
1053         int iga1_fifo_max_depth = 0, iga1_fifo_threshold =
1054             0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0;
1055         int iga2_fifo_max_depth = 0, iga2_fifo_threshold =
1056             0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0;
1057
1058         if (set_iga == IGA1) {
1059                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1060                         iga1_fifo_max_depth = K800_IGA1_FIFO_MAX_DEPTH;
1061                         iga1_fifo_threshold = K800_IGA1_FIFO_THRESHOLD;
1062                         iga1_fifo_high_threshold =
1063                             K800_IGA1_FIFO_HIGH_THRESHOLD;
1064                         /* If resolution > 1280x1024, expire length = 64, else
1065                            expire length = 128 */
1066                         if ((hor_active > 1280) && (ver_active > 1024))
1067                                 iga1_display_queue_expire_num = 16;
1068                         else
1069                                 iga1_display_queue_expire_num =
1070                                     K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1071
1072                 }
1073
1074                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1075                         iga1_fifo_max_depth = P880_IGA1_FIFO_MAX_DEPTH;
1076                         iga1_fifo_threshold = P880_IGA1_FIFO_THRESHOLD;
1077                         iga1_fifo_high_threshold =
1078                             P880_IGA1_FIFO_HIGH_THRESHOLD;
1079                         iga1_display_queue_expire_num =
1080                             P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1081
1082                         /* If resolution > 1280x1024, expire length = 64, else
1083                            expire length = 128 */
1084                         if ((hor_active > 1280) && (ver_active > 1024))
1085                                 iga1_display_queue_expire_num = 16;
1086                         else
1087                                 iga1_display_queue_expire_num =
1088                                     P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1089                 }
1090
1091                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1092                         iga1_fifo_max_depth = CN700_IGA1_FIFO_MAX_DEPTH;
1093                         iga1_fifo_threshold = CN700_IGA1_FIFO_THRESHOLD;
1094                         iga1_fifo_high_threshold =
1095                             CN700_IGA1_FIFO_HIGH_THRESHOLD;
1096
1097                         /* If resolution > 1280x1024, expire length = 64,
1098                            else expire length = 128 */
1099                         if ((hor_active > 1280) && (ver_active > 1024))
1100                                 iga1_display_queue_expire_num = 16;
1101                         else
1102                                 iga1_display_queue_expire_num =
1103                                     CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1104                 }
1105
1106                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1107                         iga1_fifo_max_depth = CX700_IGA1_FIFO_MAX_DEPTH;
1108                         iga1_fifo_threshold = CX700_IGA1_FIFO_THRESHOLD;
1109                         iga1_fifo_high_threshold =
1110                             CX700_IGA1_FIFO_HIGH_THRESHOLD;
1111                         iga1_display_queue_expire_num =
1112                             CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1113                 }
1114
1115                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1116                         iga1_fifo_max_depth = K8M890_IGA1_FIFO_MAX_DEPTH;
1117                         iga1_fifo_threshold = K8M890_IGA1_FIFO_THRESHOLD;
1118                         iga1_fifo_high_threshold =
1119                             K8M890_IGA1_FIFO_HIGH_THRESHOLD;
1120                         iga1_display_queue_expire_num =
1121                             K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1122                 }
1123
1124                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1125                         iga1_fifo_max_depth = P4M890_IGA1_FIFO_MAX_DEPTH;
1126                         iga1_fifo_threshold = P4M890_IGA1_FIFO_THRESHOLD;
1127                         iga1_fifo_high_threshold =
1128                             P4M890_IGA1_FIFO_HIGH_THRESHOLD;
1129                         iga1_display_queue_expire_num =
1130                             P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1131                 }
1132
1133                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1134                         iga1_fifo_max_depth = P4M900_IGA1_FIFO_MAX_DEPTH;
1135                         iga1_fifo_threshold = P4M900_IGA1_FIFO_THRESHOLD;
1136                         iga1_fifo_high_threshold =
1137                             P4M900_IGA1_FIFO_HIGH_THRESHOLD;
1138                         iga1_display_queue_expire_num =
1139                             P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1140                 }
1141
1142                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1143                         iga1_fifo_max_depth = VX800_IGA1_FIFO_MAX_DEPTH;
1144                         iga1_fifo_threshold = VX800_IGA1_FIFO_THRESHOLD;
1145                         iga1_fifo_high_threshold =
1146                             VX800_IGA1_FIFO_HIGH_THRESHOLD;
1147                         iga1_display_queue_expire_num =
1148                             VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1149                 }
1150
1151                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1152                         iga1_fifo_max_depth = VX855_IGA1_FIFO_MAX_DEPTH;
1153                         iga1_fifo_threshold = VX855_IGA1_FIFO_THRESHOLD;
1154                         iga1_fifo_high_threshold =
1155                             VX855_IGA1_FIFO_HIGH_THRESHOLD;
1156                         iga1_display_queue_expire_num =
1157                             VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1158                 }
1159
1160                 /* Set Display FIFO Depath Select */
1161                 reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
1162                 viafb_load_reg_num =
1163                     display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num;
1164                 reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg;
1165                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1166
1167                 /* Set Display FIFO Threshold Select */
1168                 reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold);
1169                 viafb_load_reg_num =
1170                     fifo_threshold_select_reg.
1171                     iga1_fifo_threshold_select_reg.reg_num;
1172                 reg =
1173                     fifo_threshold_select_reg.
1174                     iga1_fifo_threshold_select_reg.reg;
1175                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1176
1177                 /* Set FIFO High Threshold Select */
1178                 reg_value =
1179                     IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold);
1180                 viafb_load_reg_num =
1181                     fifo_high_threshold_select_reg.
1182                     iga1_fifo_high_threshold_select_reg.reg_num;
1183                 reg =
1184                     fifo_high_threshold_select_reg.
1185                     iga1_fifo_high_threshold_select_reg.reg;
1186                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1187
1188                 /* Set Display Queue Expire Num */
1189                 reg_value =
1190                     IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1191                     (iga1_display_queue_expire_num);
1192                 viafb_load_reg_num =
1193                     display_queue_expire_num_reg.
1194                     iga1_display_queue_expire_num_reg.reg_num;
1195                 reg =
1196                     display_queue_expire_num_reg.
1197                     iga1_display_queue_expire_num_reg.reg;
1198                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1199
1200         } else {
1201                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1202                         iga2_fifo_max_depth = K800_IGA2_FIFO_MAX_DEPTH;
1203                         iga2_fifo_threshold = K800_IGA2_FIFO_THRESHOLD;
1204                         iga2_fifo_high_threshold =
1205                             K800_IGA2_FIFO_HIGH_THRESHOLD;
1206
1207                         /* If resolution > 1280x1024, expire length = 64,
1208                            else  expire length = 128 */
1209                         if ((hor_active > 1280) && (ver_active > 1024))
1210                                 iga2_display_queue_expire_num = 16;
1211                         else
1212                                 iga2_display_queue_expire_num =
1213                                     K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1214                 }
1215
1216                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1217                         iga2_fifo_max_depth = P880_IGA2_FIFO_MAX_DEPTH;
1218                         iga2_fifo_threshold = P880_IGA2_FIFO_THRESHOLD;
1219                         iga2_fifo_high_threshold =
1220                             P880_IGA2_FIFO_HIGH_THRESHOLD;
1221
1222                         /* If resolution > 1280x1024, expire length = 64,
1223                            else  expire length = 128 */
1224                         if ((hor_active > 1280) && (ver_active > 1024))
1225                                 iga2_display_queue_expire_num = 16;
1226                         else
1227                                 iga2_display_queue_expire_num =
1228                                     P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1229                 }
1230
1231                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1232                         iga2_fifo_max_depth = CN700_IGA2_FIFO_MAX_DEPTH;
1233                         iga2_fifo_threshold = CN700_IGA2_FIFO_THRESHOLD;
1234                         iga2_fifo_high_threshold =
1235                             CN700_IGA2_FIFO_HIGH_THRESHOLD;
1236
1237                         /* If resolution > 1280x1024, expire length = 64,
1238                            else expire length = 128 */
1239                         if ((hor_active > 1280) && (ver_active > 1024))
1240                                 iga2_display_queue_expire_num = 16;
1241                         else
1242                                 iga2_display_queue_expire_num =
1243                                     CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1244                 }
1245
1246                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1247                         iga2_fifo_max_depth = CX700_IGA2_FIFO_MAX_DEPTH;
1248                         iga2_fifo_threshold = CX700_IGA2_FIFO_THRESHOLD;
1249                         iga2_fifo_high_threshold =
1250                             CX700_IGA2_FIFO_HIGH_THRESHOLD;
1251                         iga2_display_queue_expire_num =
1252                             CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1253                 }
1254
1255                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1256                         iga2_fifo_max_depth = K8M890_IGA2_FIFO_MAX_DEPTH;
1257                         iga2_fifo_threshold = K8M890_IGA2_FIFO_THRESHOLD;
1258                         iga2_fifo_high_threshold =
1259                             K8M890_IGA2_FIFO_HIGH_THRESHOLD;
1260                         iga2_display_queue_expire_num =
1261                             K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1262                 }
1263
1264                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1265                         iga2_fifo_max_depth = P4M890_IGA2_FIFO_MAX_DEPTH;
1266                         iga2_fifo_threshold = P4M890_IGA2_FIFO_THRESHOLD;
1267                         iga2_fifo_high_threshold =
1268                             P4M890_IGA2_FIFO_HIGH_THRESHOLD;
1269                         iga2_display_queue_expire_num =
1270                             P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1271                 }
1272
1273                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1274                         iga2_fifo_max_depth = P4M900_IGA2_FIFO_MAX_DEPTH;
1275                         iga2_fifo_threshold = P4M900_IGA2_FIFO_THRESHOLD;
1276                         iga2_fifo_high_threshold =
1277                             P4M900_IGA2_FIFO_HIGH_THRESHOLD;
1278                         iga2_display_queue_expire_num =
1279                             P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1280                 }
1281
1282                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1283                         iga2_fifo_max_depth = VX800_IGA2_FIFO_MAX_DEPTH;
1284                         iga2_fifo_threshold = VX800_IGA2_FIFO_THRESHOLD;
1285                         iga2_fifo_high_threshold =
1286                             VX800_IGA2_FIFO_HIGH_THRESHOLD;
1287                         iga2_display_queue_expire_num =
1288                             VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1289                 }
1290
1291                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1292                         iga2_fifo_max_depth = VX855_IGA2_FIFO_MAX_DEPTH;
1293                         iga2_fifo_threshold = VX855_IGA2_FIFO_THRESHOLD;
1294                         iga2_fifo_high_threshold =
1295                             VX855_IGA2_FIFO_HIGH_THRESHOLD;
1296                         iga2_display_queue_expire_num =
1297                             VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1298                 }
1299
1300                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1301                         /* Set Display FIFO Depath Select */
1302                         reg_value =
1303                             IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth)
1304                             - 1;
1305                         /* Patch LCD in IGA2 case */
1306                         viafb_load_reg_num =
1307                             display_fifo_depth_reg.
1308                             iga2_fifo_depth_select_reg.reg_num;
1309                         reg =
1310                             display_fifo_depth_reg.
1311                             iga2_fifo_depth_select_reg.reg;
1312                         viafb_load_reg(reg_value,
1313                                 viafb_load_reg_num, reg, VIACR);
1314                 } else {
1315
1316                         /* Set Display FIFO Depath Select */
1317                         reg_value =
1318                             IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth);
1319                         viafb_load_reg_num =
1320                             display_fifo_depth_reg.
1321                             iga2_fifo_depth_select_reg.reg_num;
1322                         reg =
1323                             display_fifo_depth_reg.
1324                             iga2_fifo_depth_select_reg.reg;
1325                         viafb_load_reg(reg_value,
1326                                 viafb_load_reg_num, reg, VIACR);
1327                 }
1328
1329                 /* Set Display FIFO Threshold Select */
1330                 reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold);
1331                 viafb_load_reg_num =
1332                     fifo_threshold_select_reg.
1333                     iga2_fifo_threshold_select_reg.reg_num;
1334                 reg =
1335                     fifo_threshold_select_reg.
1336                     iga2_fifo_threshold_select_reg.reg;
1337                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1338
1339                 /* Set FIFO High Threshold Select */
1340                 reg_value =
1341                     IGA2_FIFO_HIGH_THRESHOLD_FORMULA(iga2_fifo_high_threshold);
1342                 viafb_load_reg_num =
1343                     fifo_high_threshold_select_reg.
1344                     iga2_fifo_high_threshold_select_reg.reg_num;
1345                 reg =
1346                     fifo_high_threshold_select_reg.
1347                     iga2_fifo_high_threshold_select_reg.reg;
1348                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1349
1350                 /* Set Display Queue Expire Num */
1351                 reg_value =
1352                     IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1353                     (iga2_display_queue_expire_num);
1354                 viafb_load_reg_num =
1355                     display_queue_expire_num_reg.
1356                     iga2_display_queue_expire_num_reg.reg_num;
1357                 reg =
1358                     display_queue_expire_num_reg.
1359                     iga2_display_queue_expire_num_reg.reg;
1360                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1361
1362         }
1363
1364 }
1365
1366 u32 viafb_get_clk_value(int clk)
1367 {
1368         int i;
1369
1370         for (i = 0; i < NUM_TOTAL_PLL_TABLE; i++) {
1371                 if (clk == pll_value[i].clk) {
1372                         switch (viaparinfo->chip_info->gfx_chip_name) {
1373                         case UNICHROME_CLE266:
1374                         case UNICHROME_K400:
1375                                 return pll_value[i].cle266_pll;
1376
1377                         case UNICHROME_K800:
1378                         case UNICHROME_PM800:
1379                         case UNICHROME_CN700:
1380                                 return pll_value[i].k800_pll;
1381
1382                         case UNICHROME_CX700:
1383                         case UNICHROME_K8M890:
1384                         case UNICHROME_P4M890:
1385                         case UNICHROME_P4M900:
1386                         case UNICHROME_VX800:
1387                                 return pll_value[i].cx700_pll;
1388                         case UNICHROME_VX855:
1389                                 return pll_value[i].vx855_pll;
1390                         }
1391                 }
1392         }
1393
1394         DEBUG_MSG(KERN_INFO "Can't find match PLL value\n\n");
1395         return 0;
1396 }
1397
1398 /* Set VCLK*/
1399 void viafb_set_vclock(u32 CLK, int set_iga)
1400 {
1401         unsigned char RegTemp;
1402
1403         /* H.W. Reset : ON */
1404         viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1405
1406         if (set_iga == IGA1) {
1407                 /* Change D,N FOR VCLK */
1408                 switch (viaparinfo->chip_info->gfx_chip_name) {
1409                 case UNICHROME_CLE266:
1410                 case UNICHROME_K400:
1411                         viafb_write_reg(SR46, VIASR, CLK / 0x100);
1412                         viafb_write_reg(SR47, VIASR, CLK % 0x100);
1413                         break;
1414
1415                 case UNICHROME_K800:
1416                 case UNICHROME_PM800:
1417                 case UNICHROME_CN700:
1418                 case UNICHROME_CX700:
1419                 case UNICHROME_K8M890:
1420                 case UNICHROME_P4M890:
1421                 case UNICHROME_P4M900:
1422                 case UNICHROME_VX800:
1423                 case UNICHROME_VX855:
1424                         viafb_write_reg(SR44, VIASR, CLK / 0x10000);
1425                         DEBUG_MSG(KERN_INFO "\nSR44=%x", CLK / 0x10000);
1426                         viafb_write_reg(SR45, VIASR, (CLK & 0xFFFF) / 0x100);
1427                         DEBUG_MSG(KERN_INFO "\nSR45=%x",
1428                                   (CLK & 0xFFFF) / 0x100);
1429                         viafb_write_reg(SR46, VIASR, CLK % 0x100);
1430                         DEBUG_MSG(KERN_INFO "\nSR46=%x", CLK % 0x100);
1431                         break;
1432                 }
1433         }
1434
1435         if (set_iga == IGA2) {
1436                 /* Change D,N FOR LCK */
1437                 switch (viaparinfo->chip_info->gfx_chip_name) {
1438                 case UNICHROME_CLE266:
1439                 case UNICHROME_K400:
1440                         viafb_write_reg(SR44, VIASR, CLK / 0x100);
1441                         viafb_write_reg(SR45, VIASR, CLK % 0x100);
1442                         break;
1443
1444                 case UNICHROME_K800:
1445                 case UNICHROME_PM800:
1446                 case UNICHROME_CN700:
1447                 case UNICHROME_CX700:
1448                 case UNICHROME_K8M890:
1449                 case UNICHROME_P4M890:
1450                 case UNICHROME_P4M900:
1451                 case UNICHROME_VX800:
1452                 case UNICHROME_VX855:
1453                         viafb_write_reg(SR4A, VIASR, CLK / 0x10000);
1454                         viafb_write_reg(SR4B, VIASR, (CLK & 0xFFFF) / 0x100);
1455                         viafb_write_reg(SR4C, VIASR, CLK % 0x100);
1456                         break;
1457                 }
1458         }
1459
1460         /* H.W. Reset : OFF */
1461         viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1462
1463         /* Reset PLL */
1464         if (set_iga == IGA1) {
1465                 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
1466                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
1467         }
1468
1469         if (set_iga == IGA2) {
1470                 viafb_write_reg_mask(SR40, VIASR, 0x01, BIT0);
1471                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT0);
1472         }
1473
1474         /* Fire! */
1475         RegTemp = inb(VIARMisc);
1476         outb(RegTemp | (BIT2 + BIT3), VIAWMisc);
1477 }
1478
1479 void viafb_load_crtc_timing(struct display_timing device_timing,
1480         int set_iga)
1481 {
1482         int i;
1483         int viafb_load_reg_num = 0;
1484         int reg_value = 0;
1485         struct io_register *reg = NULL;
1486
1487         viafb_unlock_crt();
1488
1489         for (i = 0; i < 12; i++) {
1490                 if (set_iga == IGA1) {
1491                         switch (i) {
1492                         case H_TOTAL_INDEX:
1493                                 reg_value =
1494                                     IGA1_HOR_TOTAL_FORMULA(device_timing.
1495                                                            hor_total);
1496                                 viafb_load_reg_num =
1497                                         iga1_crtc_reg.hor_total.reg_num;
1498                                 reg = iga1_crtc_reg.hor_total.reg;
1499                                 break;
1500                         case H_ADDR_INDEX:
1501                                 reg_value =
1502                                     IGA1_HOR_ADDR_FORMULA(device_timing.
1503                                                           hor_addr);
1504                                 viafb_load_reg_num =
1505                                         iga1_crtc_reg.hor_addr.reg_num;
1506                                 reg = iga1_crtc_reg.hor_addr.reg;
1507                                 break;
1508                         case H_BLANK_START_INDEX:
1509                                 reg_value =
1510                                     IGA1_HOR_BLANK_START_FORMULA
1511                                     (device_timing.hor_blank_start);
1512                                 viafb_load_reg_num =
1513                                     iga1_crtc_reg.hor_blank_start.reg_num;
1514                                 reg = iga1_crtc_reg.hor_blank_start.reg;
1515                                 break;
1516                         case H_BLANK_END_INDEX:
1517                                 reg_value =
1518                                     IGA1_HOR_BLANK_END_FORMULA
1519                                     (device_timing.hor_blank_start,
1520                                      device_timing.hor_blank_end);
1521                                 viafb_load_reg_num =
1522                                     iga1_crtc_reg.hor_blank_end.reg_num;
1523                                 reg = iga1_crtc_reg.hor_blank_end.reg;
1524                                 break;
1525                         case H_SYNC_START_INDEX:
1526                                 reg_value =
1527                                     IGA1_HOR_SYNC_START_FORMULA
1528                                     (device_timing.hor_sync_start);
1529                                 viafb_load_reg_num =
1530                                     iga1_crtc_reg.hor_sync_start.reg_num;
1531                                 reg = iga1_crtc_reg.hor_sync_start.reg;
1532                                 break;
1533                         case H_SYNC_END_INDEX:
1534                                 reg_value =
1535                                     IGA1_HOR_SYNC_END_FORMULA
1536                                     (device_timing.hor_sync_start,
1537                                      device_timing.hor_sync_end);
1538                                 viafb_load_reg_num =
1539                                     iga1_crtc_reg.hor_sync_end.reg_num;
1540                                 reg = iga1_crtc_reg.hor_sync_end.reg;
1541                                 break;
1542                         case V_TOTAL_INDEX:
1543                                 reg_value =
1544                                     IGA1_VER_TOTAL_FORMULA(device_timing.
1545                                                            ver_total);
1546                                 viafb_load_reg_num =
1547                                         iga1_crtc_reg.ver_total.reg_num;
1548                                 reg = iga1_crtc_reg.ver_total.reg;
1549                                 break;
1550                         case V_ADDR_INDEX:
1551                                 reg_value =
1552                                     IGA1_VER_ADDR_FORMULA(device_timing.
1553                                                           ver_addr);
1554                                 viafb_load_reg_num =
1555                                         iga1_crtc_reg.ver_addr.reg_num;
1556                                 reg = iga1_crtc_reg.ver_addr.reg;
1557                                 break;
1558                         case V_BLANK_START_INDEX:
1559                                 reg_value =
1560                                     IGA1_VER_BLANK_START_FORMULA
1561                                     (device_timing.ver_blank_start);
1562                                 viafb_load_reg_num =
1563                                     iga1_crtc_reg.ver_blank_start.reg_num;
1564                                 reg = iga1_crtc_reg.ver_blank_start.reg;
1565                                 break;
1566                         case V_BLANK_END_INDEX:
1567                                 reg_value =
1568                                     IGA1_VER_BLANK_END_FORMULA
1569                                     (device_timing.ver_blank_start,
1570                                      device_timing.ver_blank_end);
1571                                 viafb_load_reg_num =
1572                                     iga1_crtc_reg.ver_blank_end.reg_num;
1573                                 reg = iga1_crtc_reg.ver_blank_end.reg;
1574                                 break;
1575                         case V_SYNC_START_INDEX:
1576                                 reg_value =
1577                                     IGA1_VER_SYNC_START_FORMULA
1578                                     (device_timing.ver_sync_start);
1579                                 viafb_load_reg_num =
1580                                     iga1_crtc_reg.ver_sync_start.reg_num;
1581                                 reg = iga1_crtc_reg.ver_sync_start.reg;
1582                                 break;
1583                         case V_SYNC_END_INDEX:
1584                                 reg_value =
1585                                     IGA1_VER_SYNC_END_FORMULA
1586                                     (device_timing.ver_sync_start,
1587                                      device_timing.ver_sync_end);
1588                                 viafb_load_reg_num =
1589                                     iga1_crtc_reg.ver_sync_end.reg_num;
1590                                 reg = iga1_crtc_reg.ver_sync_end.reg;
1591                                 break;
1592
1593                         }
1594                 }
1595
1596                 if (set_iga == IGA2) {
1597                         switch (i) {
1598                         case H_TOTAL_INDEX:
1599                                 reg_value =
1600                                     IGA2_HOR_TOTAL_FORMULA(device_timing.
1601                                                            hor_total);
1602                                 viafb_load_reg_num =
1603                                         iga2_crtc_reg.hor_total.reg_num;
1604                                 reg = iga2_crtc_reg.hor_total.reg;
1605                                 break;
1606                         case H_ADDR_INDEX:
1607                                 reg_value =
1608                                     IGA2_HOR_ADDR_FORMULA(device_timing.
1609                                                           hor_addr);
1610                                 viafb_load_reg_num =
1611                                         iga2_crtc_reg.hor_addr.reg_num;
1612                                 reg = iga2_crtc_reg.hor_addr.reg;
1613                                 break;
1614                         case H_BLANK_START_INDEX:
1615                                 reg_value =
1616                                     IGA2_HOR_BLANK_START_FORMULA
1617                                     (device_timing.hor_blank_start);
1618                                 viafb_load_reg_num =
1619                                     iga2_crtc_reg.hor_blank_start.reg_num;
1620                                 reg = iga2_crtc_reg.hor_blank_start.reg;
1621                                 break;
1622                         case H_BLANK_END_INDEX:
1623                                 reg_value =
1624                                     IGA2_HOR_BLANK_END_FORMULA
1625                                     (device_timing.hor_blank_start,
1626                                      device_timing.hor_blank_end);
1627                                 viafb_load_reg_num =
1628                                     iga2_crtc_reg.hor_blank_end.reg_num;
1629                                 reg = iga2_crtc_reg.hor_blank_end.reg;
1630                                 break;
1631                         case H_SYNC_START_INDEX:
1632                                 reg_value =
1633                                     IGA2_HOR_SYNC_START_FORMULA
1634                                     (device_timing.hor_sync_start);
1635                                 if (UNICHROME_CN700 <=
1636                                         viaparinfo->chip_info->gfx_chip_name)
1637                                         viafb_load_reg_num =
1638                                             iga2_crtc_reg.hor_sync_start.
1639                                             reg_num;
1640                                 else
1641                                         viafb_load_reg_num = 3;
1642                                 reg = iga2_crtc_reg.hor_sync_start.reg;
1643                                 break;
1644                         case H_SYNC_END_INDEX:
1645                                 reg_value =
1646                                     IGA2_HOR_SYNC_END_FORMULA
1647                                     (device_timing.hor_sync_start,
1648                                      device_timing.hor_sync_end);
1649                                 viafb_load_reg_num =
1650                                     iga2_crtc_reg.hor_sync_end.reg_num;
1651                                 reg = iga2_crtc_reg.hor_sync_end.reg;
1652                                 break;
1653                         case V_TOTAL_INDEX:
1654                                 reg_value =
1655                                     IGA2_VER_TOTAL_FORMULA(device_timing.
1656                                                            ver_total);
1657                                 viafb_load_reg_num =
1658                                         iga2_crtc_reg.ver_total.reg_num;
1659                                 reg = iga2_crtc_reg.ver_total.reg;
1660                                 break;
1661                         case V_ADDR_INDEX:
1662                                 reg_value =
1663                                     IGA2_VER_ADDR_FORMULA(device_timing.
1664                                                           ver_addr);
1665                                 viafb_load_reg_num =
1666                                         iga2_crtc_reg.ver_addr.reg_num;
1667                                 reg = iga2_crtc_reg.ver_addr.reg;
1668                                 break;
1669                         case V_BLANK_START_INDEX:
1670                                 reg_value =
1671                                     IGA2_VER_BLANK_START_FORMULA
1672                                     (device_timing.ver_blank_start);
1673                                 viafb_load_reg_num =
1674                                     iga2_crtc_reg.ver_blank_start.reg_num;
1675                                 reg = iga2_crtc_reg.ver_blank_start.reg;
1676                                 break;
1677                         case V_BLANK_END_INDEX:
1678                                 reg_value =
1679                                     IGA2_VER_BLANK_END_FORMULA
1680                                     (device_timing.ver_blank_start,
1681                                      device_timing.ver_blank_end);
1682                                 viafb_load_reg_num =
1683                                     iga2_crtc_reg.ver_blank_end.reg_num;
1684                                 reg = iga2_crtc_reg.ver_blank_end.reg;
1685                                 break;
1686                         case V_SYNC_START_INDEX:
1687                                 reg_value =
1688                                     IGA2_VER_SYNC_START_FORMULA
1689                                     (device_timing.ver_sync_start);
1690                                 viafb_load_reg_num =
1691                                     iga2_crtc_reg.ver_sync_start.reg_num;
1692                                 reg = iga2_crtc_reg.ver_sync_start.reg;
1693                                 break;
1694                         case V_SYNC_END_INDEX:
1695                                 reg_value =
1696                                     IGA2_VER_SYNC_END_FORMULA
1697                                     (device_timing.ver_sync_start,
1698                                      device_timing.ver_sync_end);
1699                                 viafb_load_reg_num =
1700                                     iga2_crtc_reg.ver_sync_end.reg_num;
1701                                 reg = iga2_crtc_reg.ver_sync_end.reg;
1702                                 break;
1703
1704                         }
1705                 }
1706                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1707         }
1708
1709         viafb_lock_crt();
1710 }
1711
1712 void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1713         struct VideoModeTable *video_mode, int bpp_byte, int set_iga)
1714 {
1715         struct display_timing crt_reg;
1716         int i;
1717         int index = 0;
1718         int h_addr, v_addr;
1719         u32 pll_D_N;
1720
1721         for (i = 0; i < video_mode->mode_array; i++) {
1722                 index = i;
1723
1724                 if (crt_table[i].refresh_rate == viaparinfo->
1725                         crt_setting_info->refresh_rate)
1726                         break;
1727         }
1728
1729         crt_reg = crt_table[index].crtc;
1730
1731         /* Mode 640x480 has border, but LCD/DFP didn't have border. */
1732         /* So we would delete border. */
1733         if ((viafb_LCD_ON | viafb_DVI_ON)
1734             && video_mode->crtc[0].crtc.hor_addr == 640
1735             && video_mode->crtc[0].crtc.ver_addr == 480
1736             && viaparinfo->crt_setting_info->refresh_rate == 60) {
1737                 /* The border is 8 pixels. */
1738                 crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8;
1739
1740                 /* Blanking time should add left and right borders. */
1741                 crt_reg.hor_blank_end = crt_reg.hor_blank_end + 16;
1742         }
1743
1744         h_addr = crt_reg.hor_addr;
1745         v_addr = crt_reg.ver_addr;
1746
1747         /* update polarity for CRT timing */
1748         if (crt_table[index].h_sync_polarity == NEGATIVE) {
1749                 if (crt_table[index].v_sync_polarity == NEGATIVE)
1750                         outb((inb(VIARMisc) & (~(BIT6 + BIT7))) |
1751                              (BIT6 + BIT7), VIAWMisc);
1752                 else
1753                         outb((inb(VIARMisc) & (~(BIT6 + BIT7))) | (BIT6),
1754                              VIAWMisc);
1755         } else {
1756                 if (crt_table[index].v_sync_polarity == NEGATIVE)
1757                         outb((inb(VIARMisc) & (~(BIT6 + BIT7))) | (BIT7),
1758                              VIAWMisc);
1759                 else
1760                         outb((inb(VIARMisc) & (~(BIT6 + BIT7))), VIAWMisc);
1761         }
1762
1763         if (set_iga == IGA1) {
1764                 viafb_unlock_crt();
1765                 viafb_write_reg(CR09, VIACR, 0x00);     /*initial CR09=0 */
1766                 viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6);
1767                 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1768         }
1769
1770         switch (set_iga) {
1771         case IGA1:
1772                 viafb_load_crtc_timing(crt_reg, IGA1);
1773                 break;
1774         case IGA2:
1775                 viafb_load_crtc_timing(crt_reg, IGA2);
1776                 break;
1777         }
1778
1779         load_fix_bit_crtc_reg();
1780         viafb_lock_crt();
1781         viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1782         viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga);
1783
1784         /* load FIFO */
1785         if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
1786             && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
1787                 viafb_load_FIFO_reg(set_iga, h_addr, v_addr);
1788
1789         pll_D_N = viafb_get_clk_value(crt_table[index].clk);
1790         DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);
1791         viafb_set_vclock(pll_D_N, set_iga);
1792
1793 }
1794
1795 void viafb_init_chip_info(int chip_type)
1796 {
1797         init_gfx_chip_info(chip_type);
1798         init_tmds_chip_info();
1799         init_lvds_chip_info();
1800
1801         viaparinfo->crt_setting_info->iga_path = IGA1;
1802         viaparinfo->crt_setting_info->refresh_rate = viafb_refresh;
1803
1804         /*Set IGA path for each device */
1805         viafb_set_iga_path();
1806
1807         viaparinfo->lvds_setting_info->display_method = viafb_lcd_dsp_method;
1808         viaparinfo->lvds_setting_info->get_lcd_size_method =
1809                 GET_LCD_SIZE_BY_USER_SETTING;
1810         viaparinfo->lvds_setting_info->lcd_mode = viafb_lcd_mode;
1811         viaparinfo->lvds_setting_info2->display_method =
1812                 viaparinfo->lvds_setting_info->display_method;
1813         viaparinfo->lvds_setting_info2->lcd_mode =
1814                 viaparinfo->lvds_setting_info->lcd_mode;
1815 }
1816
1817 void viafb_update_device_setting(int hres, int vres,
1818         int bpp, int vmode_refresh, int flag)
1819 {
1820         if (flag == 0) {
1821                 viaparinfo->crt_setting_info->h_active = hres;
1822                 viaparinfo->crt_setting_info->v_active = vres;
1823                 viaparinfo->crt_setting_info->bpp = bpp;
1824                 viaparinfo->crt_setting_info->refresh_rate =
1825                         vmode_refresh;
1826
1827                 viaparinfo->tmds_setting_info->h_active = hres;
1828                 viaparinfo->tmds_setting_info->v_active = vres;
1829
1830                 viaparinfo->lvds_setting_info->h_active = hres;
1831                 viaparinfo->lvds_setting_info->v_active = vres;
1832                 viaparinfo->lvds_setting_info->bpp = bpp;
1833                 viaparinfo->lvds_setting_info->refresh_rate =
1834                         vmode_refresh;
1835                 viaparinfo->lvds_setting_info2->h_active = hres;
1836                 viaparinfo->lvds_setting_info2->v_active = vres;
1837                 viaparinfo->lvds_setting_info2->bpp = bpp;
1838                 viaparinfo->lvds_setting_info2->refresh_rate =
1839                         vmode_refresh;
1840         } else {
1841
1842                 if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
1843                         viaparinfo->tmds_setting_info->h_active = hres;
1844                         viaparinfo->tmds_setting_info->v_active = vres;
1845                 }
1846
1847                 if (viaparinfo->lvds_setting_info->iga_path == IGA2) {
1848                         viaparinfo->lvds_setting_info->h_active = hres;
1849                         viaparinfo->lvds_setting_info->v_active = vres;
1850                         viaparinfo->lvds_setting_info->bpp = bpp;
1851                         viaparinfo->lvds_setting_info->refresh_rate =
1852                                 vmode_refresh;
1853                 }
1854                 if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) {
1855                         viaparinfo->lvds_setting_info2->h_active = hres;
1856                         viaparinfo->lvds_setting_info2->v_active = vres;
1857                         viaparinfo->lvds_setting_info2->bpp = bpp;
1858                         viaparinfo->lvds_setting_info2->refresh_rate =
1859                                 vmode_refresh;
1860                 }
1861         }
1862 }
1863
1864 static void init_gfx_chip_info(int chip_type)
1865 {
1866         u8 tmp;
1867
1868         viaparinfo->chip_info->gfx_chip_name = chip_type;
1869
1870         /* Check revision of CLE266 Chip */
1871         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
1872                 /* CR4F only define in CLE266.CX chip */
1873                 tmp = viafb_read_reg(VIACR, CR4F);
1874                 viafb_write_reg(CR4F, VIACR, 0x55);
1875                 if (viafb_read_reg(VIACR, CR4F) != 0x55)
1876                         viaparinfo->chip_info->gfx_chip_revision =
1877                         CLE266_REVISION_AX;
1878                 else
1879                         viaparinfo->chip_info->gfx_chip_revision =
1880                         CLE266_REVISION_CX;
1881                 /* restore orignal CR4F value */
1882                 viafb_write_reg(CR4F, VIACR, tmp);
1883         }
1884
1885         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1886                 tmp = viafb_read_reg(VIASR, SR43);
1887                 DEBUG_MSG(KERN_INFO "SR43:%X\n", tmp);
1888                 if (tmp & 0x02) {
1889                         viaparinfo->chip_info->gfx_chip_revision =
1890                                 CX700_REVISION_700M2;
1891                 } else if (tmp & 0x40) {
1892                         viaparinfo->chip_info->gfx_chip_revision =
1893                                 CX700_REVISION_700M;
1894                 } else {
1895                         viaparinfo->chip_info->gfx_chip_revision =
1896                                 CX700_REVISION_700;
1897                 }
1898         }
1899
1900         /* Determine which 2D engine we have */
1901         switch (viaparinfo->chip_info->gfx_chip_name) {
1902         case UNICHROME_VX800:
1903         case UNICHROME_VX855:
1904                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_M1;
1905                 break;
1906         case UNICHROME_K8M890:
1907         case UNICHROME_P4M900:
1908                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H5;
1909                 break;
1910         default:
1911                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H2;
1912                 break;
1913         }
1914 }
1915
1916 static void init_tmds_chip_info(void)
1917 {
1918         viafb_tmds_trasmitter_identify();
1919
1920         if (INTERFACE_NONE == viaparinfo->chip_info->tmds_chip_info.
1921                 output_interface) {
1922                 switch (viaparinfo->chip_info->gfx_chip_name) {
1923                 case UNICHROME_CX700:
1924                         {
1925                                 /* we should check support by hardware layout.*/
1926                                 if ((viafb_display_hardware_layout ==
1927                                      HW_LAYOUT_DVI_ONLY)
1928                                     || (viafb_display_hardware_layout ==
1929                                         HW_LAYOUT_LCD_DVI)) {
1930                                         viaparinfo->chip_info->tmds_chip_info.
1931                                             output_interface = INTERFACE_TMDS;
1932                                 } else {
1933                                         viaparinfo->chip_info->tmds_chip_info.
1934                                                 output_interface =
1935                                                 INTERFACE_NONE;
1936                                 }
1937                                 break;
1938                         }
1939                 case UNICHROME_K8M890:
1940                 case UNICHROME_P4M900:
1941                 case UNICHROME_P4M890:
1942                         /* TMDS on PCIE, we set DFPLOW as default. */
1943                         viaparinfo->chip_info->tmds_chip_info.output_interface =
1944                             INTERFACE_DFP_LOW;
1945                         break;
1946                 default:
1947                         {
1948                                 /* set DVP1 default for DVI */
1949                                 viaparinfo->chip_info->tmds_chip_info
1950                                 .output_interface = INTERFACE_DVP1;
1951                         }
1952                 }
1953         }
1954
1955         DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n",
1956                   viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
1957         viafb_init_dvi_size(&viaparinfo->shared->chip_info.tmds_chip_info,
1958                 &viaparinfo->shared->tmds_setting_info);
1959 }
1960
1961 static void init_lvds_chip_info(void)
1962 {
1963         if (viafb_lcd_panel_id > LCD_PANEL_ID_MAXIMUM)
1964                 viaparinfo->lvds_setting_info->get_lcd_size_method =
1965                     GET_LCD_SIZE_BY_VGA_BIOS;
1966         else
1967                 viaparinfo->lvds_setting_info->get_lcd_size_method =
1968                     GET_LCD_SIZE_BY_USER_SETTING;
1969
1970         viafb_lvds_trasmitter_identify();
1971         viafb_init_lcd_size();
1972         viafb_init_lvds_output_interface(&viaparinfo->chip_info->lvds_chip_info,
1973                                    viaparinfo->lvds_setting_info);
1974         if (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) {
1975                 viafb_init_lvds_output_interface(&viaparinfo->chip_info->
1976                         lvds_chip_info2, viaparinfo->lvds_setting_info2);
1977         }
1978         /*If CX700,two singel LCD, we need to reassign
1979            LCD interface to different LVDS port */
1980         if ((UNICHROME_CX700 == viaparinfo->chip_info->gfx_chip_name)
1981             && (HW_LAYOUT_LCD1_LCD2 == viafb_display_hardware_layout)) {
1982                 if ((INTEGRATED_LVDS == viaparinfo->chip_info->lvds_chip_info.
1983                         lvds_chip_name) && (INTEGRATED_LVDS ==
1984                         viaparinfo->chip_info->
1985                         lvds_chip_info2.lvds_chip_name)) {
1986                         viaparinfo->chip_info->lvds_chip_info.output_interface =
1987                                 INTERFACE_LVDS0;
1988                         viaparinfo->chip_info->lvds_chip_info2.
1989                                 output_interface =
1990                             INTERFACE_LVDS1;
1991                 }
1992         }
1993
1994         DEBUG_MSG(KERN_INFO "LVDS Chip = %d\n",
1995                   viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
1996         DEBUG_MSG(KERN_INFO "LVDS1 output_interface = %d\n",
1997                   viaparinfo->chip_info->lvds_chip_info.output_interface);
1998         DEBUG_MSG(KERN_INFO "LVDS2 output_interface = %d\n",
1999                   viaparinfo->chip_info->lvds_chip_info.output_interface);
2000 }
2001
2002 void viafb_init_dac(int set_iga)
2003 {
2004         int i;
2005         u8 tmp;
2006
2007         if (set_iga == IGA1) {
2008                 /* access Primary Display's LUT */
2009                 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2010                 /* turn off LCK */
2011                 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);
2012                 for (i = 0; i < 256; i++) {
2013                         write_dac_reg(i, palLUT_table[i].red,
2014                                       palLUT_table[i].green,
2015                                       palLUT_table[i].blue);
2016                 }
2017                 /* turn on LCK */
2018                 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);
2019         } else {
2020                 tmp = viafb_read_reg(VIACR, CR6A);
2021                 /* access Secondary Display's LUT */
2022                 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);
2023                 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
2024                 for (i = 0; i < 256; i++) {
2025                         write_dac_reg(i, palLUT_table[i].red,
2026                                       palLUT_table[i].green,
2027                                       palLUT_table[i].blue);
2028                 }
2029                 /* set IGA1 DAC for default */
2030                 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2031                 viafb_write_reg(CR6A, VIACR, tmp);
2032         }
2033 }
2034
2035 static void device_screen_off(void)
2036 {
2037         /* turn off CRT screen (IGA1) */
2038         viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);
2039 }
2040
2041 static void device_screen_on(void)
2042 {
2043         /* turn on CRT screen (IGA1) */
2044         viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);
2045 }
2046
2047 static void set_display_channel(void)
2048 {
2049         /*If viafb_LCD2_ON, on cx700, internal lvds's information
2050         is keeped on lvds_setting_info2 */
2051         if (viafb_LCD2_ON &&
2052                 viaparinfo->lvds_setting_info2->device_lcd_dualedge) {
2053                 /* For dual channel LCD: */
2054                 /* Set to Dual LVDS channel. */
2055                 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2056         } else if (viafb_LCD_ON && viafb_DVI_ON) {
2057                 /* For LCD+DFP: */
2058                 /* Set to LVDS1 + TMDS channel. */
2059                 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);
2060         } else if (viafb_DVI_ON) {
2061                 /* Set to single TMDS channel. */
2062                 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);
2063         } else if (viafb_LCD_ON) {
2064                 if (viaparinfo->lvds_setting_info->device_lcd_dualedge) {
2065                         /* For dual channel LCD: */
2066                         /* Set to Dual LVDS channel. */
2067                         viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2068                 } else {
2069                         /* Set to LVDS0 + LVDS1 channel. */
2070                         viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);
2071                 }
2072         }
2073 }
2074
2075 int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2076         struct VideoModeTable *vmode_tbl1, int video_bpp1)
2077 {
2078         int i, j;
2079         int port;
2080         u8 value, index, mask;
2081         struct crt_mode_table *crt_timing;
2082         struct crt_mode_table *crt_timing1 = NULL;
2083
2084         device_screen_off();
2085         crt_timing = vmode_tbl->crtc;
2086
2087         if (viafb_SAMM_ON == 1) {
2088                 crt_timing1 = vmode_tbl1->crtc;
2089         }
2090
2091         inb(VIAStatus);
2092         outb(0x00, VIAAR);
2093
2094         /* Write Common Setting for Video Mode */
2095         switch (viaparinfo->chip_info->gfx_chip_name) {
2096         case UNICHROME_CLE266:
2097                 viafb_write_regx(CLE266_ModeXregs, NUM_TOTAL_CLE266_ModeXregs);
2098                 break;
2099
2100         case UNICHROME_K400:
2101                 viafb_write_regx(KM400_ModeXregs, NUM_TOTAL_KM400_ModeXregs);
2102                 break;
2103
2104         case UNICHROME_K800:
2105         case UNICHROME_PM800:
2106                 viafb_write_regx(CN400_ModeXregs, NUM_TOTAL_CN400_ModeXregs);
2107                 break;
2108
2109         case UNICHROME_CN700:
2110         case UNICHROME_K8M890:
2111         case UNICHROME_P4M890:
2112         case UNICHROME_P4M900:
2113                 viafb_write_regx(CN700_ModeXregs, NUM_TOTAL_CN700_ModeXregs);
2114                 break;
2115
2116         case UNICHROME_CX700:
2117         case UNICHROME_VX800:
2118                 viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs);
2119                 break;
2120
2121         case UNICHROME_VX855:
2122                 viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs);
2123                 break;
2124         }
2125
2126         device_off();
2127
2128         /* Fill VPIT Parameters */
2129         /* Write Misc Register */
2130         outb(VPIT.Misc, VIAWMisc);
2131
2132         /* Write Sequencer */
2133         for (i = 1; i <= StdSR; i++) {
2134                 outb(i, VIASR);
2135                 outb(VPIT.SR[i - 1], VIASR + 1);
2136         }
2137
2138         viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2);
2139         viafb_set_iga_path();
2140
2141         /* Write CRTC */
2142         viafb_fill_crtc_timing(crt_timing, vmode_tbl, video_bpp / 8, IGA1);
2143
2144         /* Write Graphic Controller */
2145         for (i = 0; i < StdGR; i++) {
2146                 outb(i, VIAGR);
2147                 outb(VPIT.GR[i], VIAGR + 1);
2148         }
2149
2150         /* Write Attribute Controller */
2151         for (i = 0; i < StdAR; i++) {
2152                 inb(VIAStatus);
2153                 outb(i, VIAAR);
2154                 outb(VPIT.AR[i], VIAAR);
2155         }
2156
2157         inb(VIAStatus);
2158         outb(0x20, VIAAR);
2159
2160         /* Update Patch Register */
2161
2162         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266
2163             || viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400)
2164             && vmode_tbl->crtc[0].crtc.hor_addr == 1024
2165             && vmode_tbl->crtc[0].crtc.ver_addr == 768) {
2166                 for (j = 0; j < res_patch_table[0].table_length; j++) {
2167                         index = res_patch_table[0].io_reg_table[j].index;
2168                         port = res_patch_table[0].io_reg_table[j].port;
2169                         value = res_patch_table[0].io_reg_table[j].value;
2170                         mask = res_patch_table[0].io_reg_table[j].mask;
2171                         viafb_write_reg_mask(index, port, value, mask);
2172                 }
2173         }
2174
2175         via_set_primary_pitch(viafbinfo->fix.line_length);
2176         via_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length
2177                 : viafbinfo->fix.line_length);
2178         via_set_primary_color_depth(viaparinfo->depth);
2179         via_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth
2180                 : viaparinfo->depth);
2181         /* Update Refresh Rate Setting */
2182
2183         /* Clear On Screen */
2184
2185         /* CRT set mode */
2186         if (viafb_CRT_ON) {
2187                 if (viafb_SAMM_ON && (viaparinfo->crt_setting_info->iga_path ==
2188                         IGA2)) {
2189                         viafb_fill_crtc_timing(crt_timing1, vmode_tbl1,
2190                                 video_bpp1 / 8,
2191                                 viaparinfo->crt_setting_info->iga_path);
2192                 } else {
2193                         viafb_fill_crtc_timing(crt_timing, vmode_tbl,
2194                                 video_bpp / 8,
2195                                 viaparinfo->crt_setting_info->iga_path);
2196                 }
2197
2198                 set_crt_output_path(viaparinfo->crt_setting_info->iga_path);
2199
2200                 /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode
2201                 to 8 alignment (1368),there is several pixels (2 pixels)
2202                 on right side of screen. */
2203                 if (vmode_tbl->crtc[0].crtc.hor_addr % 8) {
2204                         viafb_unlock_crt();
2205                         viafb_write_reg(CR02, VIACR,
2206                                 viafb_read_reg(VIACR, CR02) - 1);
2207                         viafb_lock_crt();
2208                 }
2209         }
2210
2211         if (viafb_DVI_ON) {
2212                 if (viafb_SAMM_ON &&
2213                         (viaparinfo->tmds_setting_info->iga_path == IGA2)) {
2214                         viafb_dvi_set_mode(viafb_get_mode
2215                                      (viaparinfo->tmds_setting_info->h_active,
2216                                       viaparinfo->tmds_setting_info->
2217                                       v_active),
2218                                      video_bpp1, viaparinfo->
2219                                      tmds_setting_info->iga_path);
2220                 } else {
2221                         viafb_dvi_set_mode(viafb_get_mode
2222                                      (viaparinfo->tmds_setting_info->h_active,
2223                                       viaparinfo->
2224                                       tmds_setting_info->v_active),
2225                                      video_bpp, viaparinfo->
2226                                      tmds_setting_info->iga_path);
2227                 }
2228         }
2229
2230         if (viafb_LCD_ON) {
2231                 if (viafb_SAMM_ON &&
2232                         (viaparinfo->lvds_setting_info->iga_path == IGA2)) {
2233                         viaparinfo->lvds_setting_info->bpp = video_bpp1;
2234                         viafb_lcd_set_mode(crt_timing1, viaparinfo->
2235                                 lvds_setting_info,
2236                                      &viaparinfo->chip_info->lvds_chip_info);
2237                 } else {
2238                         /* IGA1 doesn't have LCD scaling, so set it center. */
2239                         if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
2240                                 viaparinfo->lvds_setting_info->display_method =
2241                                     LCD_CENTERING;
2242                         }
2243                         viaparinfo->lvds_setting_info->bpp = video_bpp;
2244                         viafb_lcd_set_mode(crt_timing, viaparinfo->
2245                                 lvds_setting_info,
2246                                      &viaparinfo->chip_info->lvds_chip_info);
2247                 }
2248         }
2249         if (viafb_LCD2_ON) {
2250                 if (viafb_SAMM_ON &&
2251                         (viaparinfo->lvds_setting_info2->iga_path == IGA2)) {
2252                         viaparinfo->lvds_setting_info2->bpp = video_bpp1;
2253                         viafb_lcd_set_mode(crt_timing1, viaparinfo->
2254                                 lvds_setting_info2,
2255                                      &viaparinfo->chip_info->lvds_chip_info2);
2256                 } else {
2257                         /* IGA1 doesn't have LCD scaling, so set it center. */
2258                         if (viaparinfo->lvds_setting_info2->iga_path == IGA1) {
2259                                 viaparinfo->lvds_setting_info2->display_method =
2260                                     LCD_CENTERING;
2261                         }
2262                         viaparinfo->lvds_setting_info2->bpp = video_bpp;
2263                         viafb_lcd_set_mode(crt_timing, viaparinfo->
2264                                 lvds_setting_info2,
2265                                      &viaparinfo->chip_info->lvds_chip_info2);
2266                 }
2267         }
2268
2269         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
2270             && (viafb_LCD_ON || viafb_DVI_ON))
2271                 set_display_channel();
2272
2273         /* If set mode normally, save resolution information for hot-plug . */
2274         if (!viafb_hotplug) {
2275                 viafb_hotplug_Xres = vmode_tbl->crtc[0].crtc.hor_addr;
2276                 viafb_hotplug_Yres = vmode_tbl->crtc[0].crtc.ver_addr;
2277                 viafb_hotplug_bpp = video_bpp;
2278                 viafb_hotplug_refresh = viafb_refresh;
2279
2280                 if (viafb_DVI_ON)
2281                         viafb_DeviceStatus = DVI_Device;
2282                 else
2283                         viafb_DeviceStatus = CRT_Device;
2284         }
2285         device_on();
2286
2287         if (viafb_SAMM_ON == 1)
2288                 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
2289
2290         device_screen_on();
2291         return 1;
2292 }
2293
2294 int viafb_get_pixclock(int hres, int vres, int vmode_refresh)
2295 {
2296         int i;
2297
2298         for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2299                 if ((hres == res_map_refresh_tbl[i].hres)
2300                     && (vres == res_map_refresh_tbl[i].vres)
2301                     && (vmode_refresh == res_map_refresh_tbl[i].vmode_refresh))
2302                         return res_map_refresh_tbl[i].pixclock;
2303         }
2304         return RES_640X480_60HZ_PIXCLOCK;
2305
2306 }
2307
2308 int viafb_get_refresh(int hres, int vres, u32 long_refresh)
2309 {
2310 #define REFRESH_TOLERANCE 3
2311         int i, nearest = -1, diff = REFRESH_TOLERANCE;
2312         for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2313                 if ((hres == res_map_refresh_tbl[i].hres)
2314                     && (vres == res_map_refresh_tbl[i].vres)
2315                     && (diff > (abs(long_refresh -
2316                     res_map_refresh_tbl[i].vmode_refresh)))) {
2317                         diff = abs(long_refresh - res_map_refresh_tbl[i].
2318                                 vmode_refresh);
2319                         nearest = i;
2320                 }
2321         }
2322 #undef REFRESH_TOLERANCE
2323         if (nearest > 0)
2324                 return res_map_refresh_tbl[nearest].vmode_refresh;
2325         return 60;
2326 }
2327
2328 static void device_off(void)
2329 {
2330         viafb_crt_disable();
2331         viafb_dvi_disable();
2332         viafb_lcd_disable();
2333 }
2334
2335 static void device_on(void)
2336 {
2337         if (viafb_CRT_ON == 1)
2338                 viafb_crt_enable();
2339         if (viafb_DVI_ON == 1)
2340                 viafb_dvi_enable();
2341         if (viafb_LCD_ON == 1)
2342                 viafb_lcd_enable();
2343 }
2344
2345 void viafb_crt_disable(void)
2346 {
2347         viafb_write_reg_mask(CR36, VIACR, BIT5 + BIT4, BIT5 + BIT4);
2348 }
2349
2350 void viafb_crt_enable(void)
2351 {
2352         viafb_write_reg_mask(CR36, VIACR, 0x0, BIT5 + BIT4);
2353 }
2354
2355 static void enable_second_display_channel(void)
2356 {
2357         /* to enable second display channel. */
2358         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2359         viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);
2360         viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2361 }
2362
2363 static void disable_second_display_channel(void)
2364 {
2365         /* to disable second display channel. */
2366         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2367         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7);
2368         viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2369 }
2370
2371
2372 void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
2373                                         *p_gfx_dpa_setting)
2374 {
2375         switch (output_interface) {
2376         case INTERFACE_DVP0:
2377                 {
2378                         /* DVP0 Clock Polarity and Adjust: */
2379                         viafb_write_reg_mask(CR96, VIACR,
2380                                        p_gfx_dpa_setting->DVP0, 0x0F);
2381
2382                         /* DVP0 Clock and Data Pads Driving: */
2383                         viafb_write_reg_mask(SR1E, VIASR,
2384                                        p_gfx_dpa_setting->DVP0ClockDri_S, BIT2);
2385                         viafb_write_reg_mask(SR2A, VIASR,
2386                                        p_gfx_dpa_setting->DVP0ClockDri_S1,
2387                                        BIT4);
2388                         viafb_write_reg_mask(SR1B, VIASR,
2389                                        p_gfx_dpa_setting->DVP0DataDri_S, BIT1);
2390                         viafb_write_reg_mask(SR2A, VIASR,
2391                                        p_gfx_dpa_setting->DVP0DataDri_S1, BIT5);
2392                         break;
2393                 }
2394
2395         case INTERFACE_DVP1:
2396                 {
2397                         /* DVP1 Clock Polarity and Adjust: */
2398                         viafb_write_reg_mask(CR9B, VIACR,
2399                                        p_gfx_dpa_setting->DVP1, 0x0F);
2400
2401                         /* DVP1 Clock and Data Pads Driving: */
2402                         viafb_write_reg_mask(SR65, VIASR,
2403                                        p_gfx_dpa_setting->DVP1Driving, 0x0F);
2404                         break;
2405                 }
2406
2407         case INTERFACE_DFP_HIGH:
2408                 {
2409                         viafb_write_reg_mask(CR97, VIACR,
2410                                        p_gfx_dpa_setting->DFPHigh, 0x0F);
2411                         break;
2412                 }
2413
2414         case INTERFACE_DFP_LOW:
2415                 {
2416                         viafb_write_reg_mask(CR99, VIACR,
2417                                        p_gfx_dpa_setting->DFPLow, 0x0F);
2418                         break;
2419                 }
2420
2421         case INTERFACE_DFP:
2422                 {
2423                         viafb_write_reg_mask(CR97, VIACR,
2424                                        p_gfx_dpa_setting->DFPHigh, 0x0F);
2425                         viafb_write_reg_mask(CR99, VIACR,
2426                                        p_gfx_dpa_setting->DFPLow, 0x0F);
2427                         break;
2428                 }
2429         }
2430 }
2431
2432 /*According var's xres, yres fill var's other timing information*/
2433 void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
2434         struct VideoModeTable *vmode_tbl)
2435 {
2436         struct crt_mode_table *crt_timing = NULL;
2437         struct display_timing crt_reg;
2438         int i = 0, index = 0;
2439         crt_timing = vmode_tbl->crtc;
2440         for (i = 0; i < vmode_tbl->mode_array; i++) {
2441                 index = i;
2442                 if (crt_timing[i].refresh_rate == refresh)
2443                         break;
2444         }
2445
2446         crt_reg = crt_timing[index].crtc;
2447         var->pixclock = viafb_get_pixclock(var->xres, var->yres, refresh);
2448         var->left_margin =
2449             crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end);
2450         var->right_margin = crt_reg.hor_sync_start - crt_reg.hor_addr;
2451         var->hsync_len = crt_reg.hor_sync_end;
2452         var->upper_margin =
2453             crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end);
2454         var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr;
2455         var->vsync_len = crt_reg.ver_sync_end;
2456 }