drivers/video/via/hw.c

   1 /*
   2  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
   3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
   4
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public
   7  * License as published by the Free Software Foundation;
   8  * either version 2, or (at your option) any later version.
   9
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
  12  * the implied warranty of MERCHANTABILITY or FITNESS FOR
  13  * A PARTICULAR PURPOSE.See the GNU General Public License
  14  * for more details.
  15
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc.,
  19  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20  */
  21 #include "via-core.h"
  22 #include "global.h"
  23
  24 static struct pll_map pll_value[] = {
  25         {CLK_25_175M, CLE266_PLL_25_175M, K800_PLL_25_175M,
  26          CX700_25_175M, VX855_25_175M},
  27         {CLK_29_581M, CLE266_PLL_29_581M, K800_PLL_29_581M,
  28          CX700_29_581M, VX855_29_581M},
  29         {CLK_26_880M, CLE266_PLL_26_880M, K800_PLL_26_880M,
  30          CX700_26_880M, VX855_26_880M},
  31         {CLK_31_490M, CLE266_PLL_31_490M, K800_PLL_31_490M,
  32          CX700_31_490M, VX855_31_490M},
  33         {CLK_31_500M, CLE266_PLL_31_500M, K800_PLL_31_500M,
  34          CX700_31_500M, VX855_31_500M},
  35         {CLK_31_728M, CLE266_PLL_31_728M, K800_PLL_31_728M,
  36          CX700_31_728M, VX855_31_728M},
  37         {CLK_32_668M, CLE266_PLL_32_668M, K800_PLL_32_668M,
  38          CX700_32_668M, VX855_32_668M},
  39         {CLK_36_000M, CLE266_PLL_36_000M, K800_PLL_36_000M,
  40          CX700_36_000M, VX855_36_000M},
  41         {CLK_40_000M, CLE266_PLL_40_000M, K800_PLL_40_000M,
  42          CX700_40_000M, VX855_40_000M},
  43         {CLK_41_291M, CLE266_PLL_41_291M, K800_PLL_41_291M,
  44          CX700_41_291M, VX855_41_291M},
  45         {CLK_43_163M, CLE266_PLL_43_163M, K800_PLL_43_163M,
  46          CX700_43_163M, VX855_43_163M},
  47         {CLK_45_250M, CLE266_PLL_45_250M, K800_PLL_45_250M,
  48          CX700_45_250M, VX855_45_250M},
  49         {CLK_46_000M, CLE266_PLL_46_000M, K800_PLL_46_000M,
  50          CX700_46_000M, VX855_46_000M},
  51         {CLK_46_996M, CLE266_PLL_46_996M, K800_PLL_46_996M,
  52          CX700_46_996M, VX855_46_996M},
  53         {CLK_48_000M, CLE266_PLL_48_000M, K800_PLL_48_000M,
  54          CX700_48_000M, VX855_48_000M},
  55         {CLK_48_875M, CLE266_PLL_48_875M, K800_PLL_48_875M,
  56          CX700_48_875M, VX855_48_875M},
  57         {CLK_49_500M, CLE266_PLL_49_500M, K800_PLL_49_500M,
  58          CX700_49_500M, VX855_49_500M},
  59         {CLK_52_406M, CLE266_PLL_52_406M, K800_PLL_52_406M,
  60          CX700_52_406M, VX855_52_406M},
  61         {CLK_52_977M, CLE266_PLL_52_977M, K800_PLL_52_977M,
  62          CX700_52_977M, VX855_52_977M},
  63         {CLK_56_250M, CLE266_PLL_56_250M, K800_PLL_56_250M,
  64          CX700_56_250M, VX855_56_250M},
  65         {CLK_57_275M, 0, 0, 0, VX855_57_275M},
  66         {CLK_60_466M, CLE266_PLL_60_466M, K800_PLL_60_466M,
  67          CX700_60_466M, VX855_60_466M},
  68         {CLK_61_500M, CLE266_PLL_61_500M, K800_PLL_61_500M,
  69          CX700_61_500M, VX855_61_500M},
  70         {CLK_65_000M, CLE266_PLL_65_000M, K800_PLL_65_000M,
  71          CX700_65_000M, VX855_65_000M},
  72         {CLK_65_178M, CLE266_PLL_65_178M, K800_PLL_65_178M,
  73          CX700_65_178M, VX855_65_178M},
  74         {CLK_66_750M, CLE266_PLL_66_750M, K800_PLL_66_750M,
  75          CX700_66_750M, VX855_66_750M},
  76         {CLK_68_179M, CLE266_PLL_68_179M, K800_PLL_68_179M,
  77          CX700_68_179M, VX855_68_179M},
  78         {CLK_69_924M, CLE266_PLL_69_924M, K800_PLL_69_924M,
  79          CX700_69_924M, VX855_69_924M},
  80         {CLK_70_159M, CLE266_PLL_70_159M, K800_PLL_70_159M,
  81          CX700_70_159M, VX855_70_159M},
  82         {CLK_72_000M, CLE266_PLL_72_000M, K800_PLL_72_000M,
  83          CX700_72_000M, VX855_72_000M},
  84         {CLK_78_750M, CLE266_PLL_78_750M, K800_PLL_78_750M,
  85          CX700_78_750M, VX855_78_750M},
  86         {CLK_80_136M, CLE266_PLL_80_136M, K800_PLL_80_136M,
  87          CX700_80_136M, VX855_80_136M},
  88         {CLK_83_375M, CLE266_PLL_83_375M, K800_PLL_83_375M,
  89          CX700_83_375M, VX855_83_375M},
  90         {CLK_83_950M, CLE266_PLL_83_950M, K800_PLL_83_950M,
  91          CX700_83_950M, VX855_83_950M},
  92         {CLK_84_750M, CLE266_PLL_84_750M, K800_PLL_84_750M,
  93          CX700_84_750M, VX855_84_750M},
  94         {CLK_85_860M, CLE266_PLL_85_860M, K800_PLL_85_860M,
  95          CX700_85_860M, VX855_85_860M},
  96         {CLK_88_750M, CLE266_PLL_88_750M, K800_PLL_88_750M,
  97          CX700_88_750M, VX855_88_750M},
  98         {CLK_94_500M, CLE266_PLL_94_500M, K800_PLL_94_500M,
  99          CX700_94_500M, VX855_94_500M},
 100         {CLK_97_750M, CLE266_PLL_97_750M, K800_PLL_97_750M,
 101          CX700_97_750M, VX855_97_750M},
 102         {CLK_101_000M, CLE266_PLL_101_000M, K800_PLL_101_000M,
 103          CX700_101_000M, VX855_101_000M},
 104         {CLK_106_500M, CLE266_PLL_106_500M, K800_PLL_106_500M,
 105          CX700_106_500M, VX855_106_500M},
 106         {CLK_108_000M, CLE266_PLL_108_000M, K800_PLL_108_000M,
 107          CX700_108_000M, VX855_108_000M},
 108         {CLK_113_309M, CLE266_PLL_113_309M, K800_PLL_113_309M,
 109          CX700_113_309M, VX855_113_309M},
 110         {CLK_118_840M, CLE266_PLL_118_840M, K800_PLL_118_840M,
 111          CX700_118_840M, VX855_118_840M},
 112         {CLK_119_000M, CLE266_PLL_119_000M, K800_PLL_119_000M,
 113          CX700_119_000M, VX855_119_000M},
 114         {CLK_121_750M, CLE266_PLL_121_750M, K800_PLL_121_750M,
 115          CX700_121_750M, 0},
 116         {CLK_125_104M, CLE266_PLL_125_104M, K800_PLL_125_104M,
 117          CX700_125_104M, 0},
 118         {CLK_133_308M, CLE266_PLL_133_308M, K800_PLL_133_308M,
 119          CX700_133_308M, 0},
 120         {CLK_135_000M, CLE266_PLL_135_000M, K800_PLL_135_000M,
 121          CX700_135_000M, VX855_135_000M},
 122         {CLK_136_700M, CLE266_PLL_136_700M, K800_PLL_136_700M,
 123          CX700_136_700M, VX855_136_700M},
 124         {CLK_138_400M, CLE266_PLL_138_400M, K800_PLL_138_400M,
 125          CX700_138_400M, VX855_138_400M},
 126         {CLK_146_760M, CLE266_PLL_146_760M, K800_PLL_146_760M,
 127          CX700_146_760M, VX855_146_760M},
 128         {CLK_153_920M, CLE266_PLL_153_920M, K800_PLL_153_920M,
 129          CX700_153_920M, VX855_153_920M},
 130         {CLK_156_000M, CLE266_PLL_156_000M, K800_PLL_156_000M,
 131          CX700_156_000M, VX855_156_000M},
 132         {CLK_157_500M, CLE266_PLL_157_500M, K800_PLL_157_500M,
 133          CX700_157_500M, VX855_157_500M},
 134         {CLK_162_000M, CLE266_PLL_162_000M, K800_PLL_162_000M,
 135          CX700_162_000M, VX855_162_000M},
 136         {CLK_187_000M, CLE266_PLL_187_000M, K800_PLL_187_000M,
 137          CX700_187_000M, VX855_187_000M},
 138         {CLK_193_295M, CLE266_PLL_193_295M, K800_PLL_193_295M,
 139          CX700_193_295M, VX855_193_295M},
 140         {CLK_202_500M, CLE266_PLL_202_500M, K800_PLL_202_500M,
 141          CX700_202_500M, VX855_202_500M},
 142         {CLK_204_000M, CLE266_PLL_204_000M, K800_PLL_204_000M,
 143          CX700_204_000M, VX855_204_000M},
 144         {CLK_218_500M, CLE266_PLL_218_500M, K800_PLL_218_500M,
 145          CX700_218_500M, VX855_218_500M},
 146         {CLK_234_000M, CLE266_PLL_234_000M, K800_PLL_234_000M,
 147          CX700_234_000M, VX855_234_000M},
 148         {CLK_267_250M, CLE266_PLL_267_250M, K800_PLL_267_250M,
 149          CX700_267_250M, VX855_267_250M},
 150         {CLK_297_500M, CLE266_PLL_297_500M, K800_PLL_297_500M,
 151          CX700_297_500M, VX855_297_500M},
 152         {CLK_74_481M, CLE266_PLL_74_481M, K800_PLL_74_481M,
 153          CX700_74_481M, VX855_74_481M},
 154         {CLK_172_798M, CLE266_PLL_172_798M, K800_PLL_172_798M,
 155          CX700_172_798M, VX855_172_798M},
 156         {CLK_122_614M, CLE266_PLL_122_614M, K800_PLL_122_614M,
 157          CX700_122_614M, VX855_122_614M},
 158         {CLK_74_270M, CLE266_PLL_74_270M, K800_PLL_74_270M,
 159          CX700_74_270M, 0},
 160         {CLK_148_500M, CLE266_PLL_148_500M, K800_PLL_148_500M,
 161          CX700_148_500M, VX855_148_500M}
 162 };
 163
 164 static struct fifo_depth_select display_fifo_depth_reg = {
 165         /* IGA1 FIFO Depth_Select */
 166         {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } },
 167         /* IGA2 FIFO Depth_Select */
 168         {IGA2_FIFO_DEPTH_SELECT_REG_NUM,
 169          {{CR68, 4, 7}, {CR94, 7, 7}, {CR95, 7, 7} } }
 170 };
 171
 172 static struct fifo_threshold_select fifo_threshold_select_reg = {
 173         /* IGA1 FIFO Threshold Select */
 174         {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } },
 175         /* IGA2 FIFO Threshold Select */
 176         {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68, 0, 3}, {CR95, 4, 6} } }
 177 };
 178
 179 static struct fifo_high_threshold_select fifo_high_threshold_select_reg = {
 180         /* IGA1 FIFO High Threshold Select */
 181         {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18, 0, 5}, {SR18, 7, 7} } },
 182         /* IGA2 FIFO High Threshold Select */
 183         {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92, 0, 3}, {CR95, 0, 2} } }
 184 };
 185
 186 static struct display_queue_expire_num display_queue_expire_num_reg = {
 187         /* IGA1 Display Queue Expire Num */
 188         {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22, 0, 4} } },
 189         /* IGA2 Display Queue Expire Num */
 190         {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94, 0, 6} } }
 191 };
 192
 193 /* Definition Fetch Count Registers*/
 194 static struct fetch_count fetch_count_reg = {
 195         /* IGA1 Fetch Count Register */
 196         {IGA1_FETCH_COUNT_REG_NUM, {{SR1C, 0, 7}, {SR1D, 0, 1} } },
 197         /* IGA2 Fetch Count Register */
 198         {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } }
 199 };
 200
 201 static struct iga1_crtc_timing iga1_crtc_reg = {
 202         /* IGA1 Horizontal Total */
 203         {IGA1_HOR_TOTAL_REG_NUM, {{CR00, 0, 7}, {CR36, 3, 3} } },
 204         /* IGA1 Horizontal Addressable Video */
 205         {IGA1_HOR_ADDR_REG_NUM, {{CR01, 0, 7} } },
 206         /* IGA1 Horizontal Blank Start */
 207         {IGA1_HOR_BLANK_START_REG_NUM, {{CR02, 0, 7} } },
 208         /* IGA1 Horizontal Blank End */
 209         {IGA1_HOR_BLANK_END_REG_NUM,
 210          {{CR03, 0, 4}, {CR05, 7, 7}, {CR33, 5, 5} } },
 211         /* IGA1 Horizontal Sync Start */
 212         {IGA1_HOR_SYNC_START_REG_NUM, {{CR04, 0, 7}, {CR33, 4, 4} } },
 213         /* IGA1 Horizontal Sync End */
 214         {IGA1_HOR_SYNC_END_REG_NUM, {{CR05, 0, 4} } },
 215         /* IGA1 Vertical Total */
 216         {IGA1_VER_TOTAL_REG_NUM,
 217          {{CR06, 0, 7}, {CR07, 0, 0}, {CR07, 5, 5}, {CR35, 0, 0} } },
 218         /* IGA1 Vertical Addressable Video */
 219         {IGA1_VER_ADDR_REG_NUM,
 220          {{CR12, 0, 7}, {CR07, 1, 1}, {CR07, 6, 6}, {CR35, 2, 2} } },
 221         /* IGA1 Vertical Blank Start */
 222         {IGA1_VER_BLANK_START_REG_NUM,
 223          {{CR15, 0, 7}, {CR07, 3, 3}, {CR09, 5, 5}, {CR35, 3, 3} } },
 224         /* IGA1 Vertical Blank End */
 225         {IGA1_VER_BLANK_END_REG_NUM, {{CR16, 0, 7} } },
 226         /* IGA1 Vertical Sync Start */
 227         {IGA1_VER_SYNC_START_REG_NUM,
 228          {{CR10, 0, 7}, {CR07, 2, 2}, {CR07, 7, 7}, {CR35, 1, 1} } },
 229         /* IGA1 Vertical Sync End */
 230         {IGA1_VER_SYNC_END_REG_NUM, {{CR11, 0, 3} } }
 231 };
 232
 233 static struct iga2_crtc_timing iga2_crtc_reg = {
 234         /* IGA2 Horizontal Total */
 235         {IGA2_HOR_TOTAL_REG_NUM, {{CR50, 0, 7}, {CR55, 0, 3} } },
 236         /* IGA2 Horizontal Addressable Video */
 237         {IGA2_HOR_ADDR_REG_NUM, {{CR51, 0, 7}, {CR55, 4, 6} } },
 238         /* IGA2 Horizontal Blank Start */
 239         {IGA2_HOR_BLANK_START_REG_NUM, {{CR52, 0, 7}, {CR54, 0, 2} } },
 240         /* IGA2 Horizontal Blank End */
 241         {IGA2_HOR_BLANK_END_REG_NUM,
 242          {{CR53, 0, 7}, {CR54, 3, 5}, {CR5D, 6, 6} } },
 243         /* IGA2 Horizontal Sync Start */
 244         {IGA2_HOR_SYNC_START_REG_NUM,
 245          {{CR56, 0, 7}, {CR54, 6, 7}, {CR5C, 7, 7}, {CR5D, 7, 7} } },
 246         /* IGA2 Horizontal Sync End */
 247         {IGA2_HOR_SYNC_END_REG_NUM, {{CR57, 0, 7}, {CR5C, 6, 6} } },
 248         /* IGA2 Vertical Total */
 249         {IGA2_VER_TOTAL_REG_NUM, {{CR58, 0, 7}, {CR5D, 0, 2} } },
 250         /* IGA2 Vertical Addressable Video */
 251         {IGA2_VER_ADDR_REG_NUM, {{CR59, 0, 7}, {CR5D, 3, 5} } },
 252         /* IGA2 Vertical Blank Start */
 253         {IGA2_VER_BLANK_START_REG_NUM, {{CR5A, 0, 7}, {CR5C, 0, 2} } },
 254         /* IGA2 Vertical Blank End */
 255         {IGA2_VER_BLANK_END_REG_NUM, {{CR5B, 0, 7}, {CR5C, 3, 5} } },
 256         /* IGA2 Vertical Sync Start */
 257         {IGA2_VER_SYNC_START_REG_NUM, {{CR5E, 0, 7}, {CR5F, 5, 7} } },
 258         /* IGA2 Vertical Sync End */
 259         {IGA2_VER_SYNC_END_REG_NUM, {{CR5F, 0, 4} } }
 260 };
 261
 262 static struct rgbLUT palLUT_table[] = {
 263         /* {R,G,B} */
 264         /* Index 0x00~0x03 */
 265         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00,
 266                                                                      0x2A,
 267                                                                      0x2A},
 268         /* Index 0x04~0x07 */
 269         {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A,
 270                                                                      0x2A,
 271                                                                      0x2A},
 272         /* Index 0x08~0x0B */
 273         {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15,
 274                                                                      0x3F,
 275                                                                      0x3F},
 276         /* Index 0x0C~0x0F */
 277         {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F,
 278                                                                      0x3F,
 279                                                                      0x3F},
 280         /* Index 0x10~0x13 */
 281         {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B,
 282                                                                      0x0B,
 283                                                                      0x0B},
 284         /* Index 0x14~0x17 */
 285         {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18,
 286                                                                      0x18,
 287                                                                      0x18},
 288         /* Index 0x18~0x1B */
 289         {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28,
 290                                                                      0x28,
 291                                                                      0x28},
 292         /* Index 0x1C~0x1F */
 293         {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F,
 294                                                                      0x3F,
 295                                                                      0x3F},
 296         /* Index 0x20~0x23 */
 297         {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F,
 298                                                                      0x00,
 299                                                                      0x3F},
 300         /* Index 0x24~0x27 */
 301         {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F,
 302                                                                      0x00,
 303                                                                      0x10},
 304         /* Index 0x28~0x2B */
 305         {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F,
 306                                                                      0x2F,
 307                                                                      0x00},
 308         /* Index 0x2C~0x2F */
 309         {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10,
 310                                                                      0x3F,
 311                                                                      0x00},
 312         /* Index 0x30~0x33 */
 313         {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00,
 314                                                                      0x3F,
 315                                                                      0x2F},
 316         /* Index 0x34~0x37 */
 317         {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00,
 318                                                                      0x10,
 319                                                                      0x3F},
 320         /* Index 0x38~0x3B */
 321         {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37,
 322                                                                      0x1F,
 323                                                                      0x3F},
 324         /* Index 0x3C~0x3F */
 325         {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F,
 326                                                                      0x1F,
 327                                                                      0x27},
 328         /* Index 0x40~0x43 */
 329         {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F,
 330                                                                      0x3F,
 331                                                                      0x1F},
 332         /* Index 0x44~0x47 */
 333         {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27,
 334                                                                      0x3F,
 335                                                                      0x1F},
 336         /* Index 0x48~0x4B */
 337         {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F,
 338                                                                      0x3F,
 339                                                                      0x37},
 340         /* Index 0x4C~0x4F */
 341         {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F,
 342                                                                      0x27,
 343                                                                      0x3F},
 344         /* Index 0x50~0x53 */
 345         {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A,
 346                                                                      0x2D,
 347                                                                      0x3F},
 348         /* Index 0x54~0x57 */
 349         {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F,
 350                                                                      0x2D,
 351                                                                      0x31},
 352         /* Index 0x58~0x5B */
 353         {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F,
 354                                                                      0x3A,
 355                                                                      0x2D},
 356         /* Index 0x5C~0x5F */
 357         {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31,
 358                                                                      0x3F,
 359                                                                      0x2D},
 360         /* Index 0x60~0x63 */
 361         {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D,
 362                                                                      0x3F,
 363                                                                      0x3A},
 364         /* Index 0x64~0x67 */
 365         {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D,
 366                                                                      0x31,
 367                                                                      0x3F},
 368         /* Index 0x68~0x6B */
 369         {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15,
 370                                                                      0x00,
 371                                                                      0x1C},
 372         /* Index 0x6C~0x6F */
 373         {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C,
 374                                                                      0x00,
 375                                                                      0x07},
 376         /* Index 0x70~0x73 */
 377         {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C,
 378                                                                      0x15,
 379                                                                      0x00},
 380         /* Index 0x74~0x77 */
 381         {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07,
 382                                                                      0x1C,
 383                                                                      0x00},
 384         /* Index 0x78~0x7B */
 385         {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00,
 386                                                                      0x1C,
 387                                                                      0x15},
 388         /* Index 0x7C~0x7F */
 389         {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00,
 390                                                                      0x07,
 391                                                                      0x1C},
 392         /* Index 0x80~0x83 */
 393         {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18,
 394                                                                      0x0E,
 395                                                                      0x1C},
 396         /* Index 0x84~0x87 */
 397         {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C,
 398                                                                      0x0E,
 399                                                                      0x11},
 400         /* Index 0x88~0x8B */
 401         {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C,
 402                                                                      0x18,
 403                                                                      0x0E},
 404         /* Index 0x8C~0x8F */
 405         {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11,
 406                                                                      0x1C,
 407                                                                      0x0E},
 408         /* Index 0x90~0x93 */
 409         {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E,
 410                                                                      0x1C,
 411                                                                      0x18},
 412         /* Index 0x94~0x97 */
 413         {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E,
 414                                                                      0x11,
 415                                                                      0x1C},
 416         /* Index 0x98~0x9B */
 417         {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A,
 418                                                                      0x14,
 419                                                                      0x1C},
 420         /* Index 0x9C~0x9F */
 421         {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C,
 422                                                                      0x14,
 423                                                                      0x16},
 424         /* Index 0xA0~0xA3 */
 425         {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C,
 426                                                                      0x1A,
 427                                                                      0x14},
 428         /* Index 0xA4~0xA7 */
 429         {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16,
 430                                                                      0x1C,
 431                                                                      0x14},
 432         /* Index 0xA8~0xAB */
 433         {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14,
 434                                                                      0x1C,
 435                                                                      0x1A},
 436         /* Index 0xAC~0xAF */
 437         {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14,
 438                                                                      0x16,
 439                                                                      0x1C},
 440         /* Index 0xB0~0xB3 */
 441         {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C,
 442                                                                      0x00,
 443                                                                      0x10},
 444         /* Index 0xB4~0xB7 */
 445         {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10,
 446                                                                      0x00,
 447                                                                      0x04},
 448         /* Index 0xB8~0xBB */
 449         {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10,
 450                                                                      0x0C,
 451                                                                      0x00},
 452         /* Index 0xBC~0xBF */
 453         {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04,
 454                                                                      0x10,
 455                                                                      0x00},
 456         /* Index 0xC0~0xC3 */
 457         {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00,
 458                                                                      0x10,
 459                                                                      0x0C},
 460         /* Index 0xC4~0xC7 */
 461         {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00,
 462                                                                      0x04,
 463                                                                      0x10},
 464         /* Index 0xC8~0xCB */
 465         {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E,
 466                                                                      0x08,
 467                                                                      0x10},
 468         /* Index 0xCC~0xCF */
 469         {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10,
 470                                                                      0x08,
 471                                                                      0x0A},
 472         /* Index 0xD0~0xD3 */
 473         {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10,
 474                                                                      0x0E,
 475                                                                      0x08},
 476         /* Index 0xD4~0xD7 */
 477         {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A,
 478                                                                      0x10,
 479                                                                      0x08},
 480         /* Index 0xD8~0xDB */
 481         {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08,
 482                                                                      0x10,
 483                                                                      0x0E},
 484         /* Index 0xDC~0xDF */
 485         {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08,
 486                                                                      0x0A,
 487                                                                      0x10},
 488         /* Index 0xE0~0xE3 */
 489         {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F,
 490                                                                      0x0B,
 491                                                                      0x10},
 492         /* Index 0xE4~0xE7 */
 493         {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10,
 494                                                                      0x0B,
 495                                                                      0x0C},
 496         /* Index 0xE8~0xEB */
 497         {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10,
 498                                                                      0x0F,
 499                                                                      0x0B},
 500         /* Index 0xEC~0xEF */
 501         {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C,
 502                                                                      0x10,
 503                                                                      0x0B},
 504         /* Index 0xF0~0xF3 */
 505         {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B,
 506                                                                      0x10,
 507                                                                      0x0F},
 508         /* Index 0xF4~0xF7 */
 509         {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B,
 510                                                                      0x0C,
 511                                                                      0x10},
 512         /* Index 0xF8~0xFB */
 513         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
 514                                                                      0x00,
 515                                                                      0x00},
 516         /* Index 0xFC~0xFF */
 517         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
 518                                                                      0x00,
 519                                                                      0x00}
 520 };
 521
 522 static void set_crt_output_path(int set_iga);
 523 static void dvi_patch_skew_dvp0(void);
 524 static void dvi_patch_skew_dvp1(void);
 525 static void dvi_patch_skew_dvp_low(void);
 526 static void set_dvi_output_path(int set_iga, int output_interface);
 527 static void set_lcd_output_path(int set_iga, int output_interface);
 528 static void load_fix_bit_crtc_reg(void);
 529 static void init_gfx_chip_info(int chip_type);
 530 static void init_tmds_chip_info(void);
 531 static void init_lvds_chip_info(void);
 532 static void device_screen_off(void);
 533 static void device_screen_on(void);
 534 static void set_display_channel(void);
 535 static void device_off(void);
 536 static void device_on(void);
 537 static void enable_second_display_channel(void);
 538 static void disable_second_display_channel(void);
 539
 540 void viafb_lock_crt(void)
 541 {
 542         viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);
 543 }
 544
 545 void viafb_unlock_crt(void)
 546 {
 547         viafb_write_reg_mask(CR11, VIACR, 0, BIT7);
 548         viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
 549 }
 550
 551 void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
 552 {
 553         outb(index, LUT_INDEX_WRITE);
 554         outb(r, LUT_DATA);
 555         outb(g, LUT_DATA);
 556         outb(b, LUT_DATA);
 557 }
 558
 559 /*Set IGA path for each device*/
 560 void viafb_set_iga_path(void)
 561 {
 562
 563         if (viafb_SAMM_ON == 1) {
 564                 if (viafb_CRT_ON) {
 565                         if (viafb_primary_dev == CRT_Device)
 566                                 viaparinfo->crt_setting_info->iga_path = IGA1;
 567                         else
 568                                 viaparinfo->crt_setting_info->iga_path = IGA2;
 569                 }
 570
 571                 if (viafb_DVI_ON) {
 572                         if (viafb_primary_dev == DVI_Device)
 573                                 viaparinfo->tmds_setting_info->iga_path = IGA1;
 574                         else
 575                                 viaparinfo->tmds_setting_info->iga_path = IGA2;
 576                 }
 577
 578                 if (viafb_LCD_ON) {
 579                         if (viafb_primary_dev == LCD_Device) {
 580                                 if (viafb_dual_fb &&
 581                                         (viaparinfo->chip_info->gfx_chip_name ==
 582                                         UNICHROME_CLE266)) {
 583                                         viaparinfo->
 584                                         lvds_setting_info->iga_path = IGA2;
 585                                         viaparinfo->
 586                                         crt_setting_info->iga_path = IGA1;
 587                                         viaparinfo->
 588                                         tmds_setting_info->iga_path = IGA1;
 589                                 } else
 590                                         viaparinfo->
 591                                         lvds_setting_info->iga_path = IGA1;
 592                         } else {
 593                                 viaparinfo->lvds_setting_info->iga_path = IGA2;
 594                         }
 595                 }
 596                 if (viafb_LCD2_ON) {
 597                         if (LCD2_Device == viafb_primary_dev)
 598                                 viaparinfo->lvds_setting_info2->iga_path = IGA1;
 599                         else
 600                                 viaparinfo->lvds_setting_info2->iga_path = IGA2;
 601                 }
 602         } else {
 603                 viafb_SAMM_ON = 0;
 604
 605                 if (viafb_CRT_ON && viafb_LCD_ON) {
 606                         viaparinfo->crt_setting_info->iga_path = IGA1;
 607                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 608                 } else if (viafb_CRT_ON && viafb_DVI_ON) {
 609                         viaparinfo->crt_setting_info->iga_path = IGA1;
 610                         viaparinfo->tmds_setting_info->iga_path = IGA2;
 611                 } else if (viafb_LCD_ON && viafb_DVI_ON) {
 612                         viaparinfo->tmds_setting_info->iga_path = IGA1;
 613                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 614                 } else if (viafb_LCD_ON && viafb_LCD2_ON) {
 615                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 616                         viaparinfo->lvds_setting_info2->iga_path = IGA2;
 617                 } else if (viafb_CRT_ON) {
 618                         viaparinfo->crt_setting_info->iga_path = IGA1;
 619                 } else if (viafb_LCD_ON) {
 620                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 621                 } else if (viafb_DVI_ON) {
 622                         viaparinfo->tmds_setting_info->iga_path = IGA1;
 623                 }
 624         }
 625 }
 626
 627 void via_set_primary_address(u32 addr)
 628 {
 629         DEBUG_MSG(KERN_DEBUG "via_set_primary_address(0x%08X)\n", addr);
 630         via_write_reg(VIACR, 0x0D, addr & 0xFF);
 631         via_write_reg(VIACR, 0x0C, (addr >> 8) & 0xFF);
 632         via_write_reg(VIACR, 0x34, (addr >> 16) & 0xFF);
 633         via_write_reg_mask(VIACR, 0x48, (addr >> 24) & 0x1F, 0x1F);
 634 }
 635
 636 void via_set_secondary_address(u32 addr)
 637 {
 638         DEBUG_MSG(KERN_DEBUG "via_set_secondary_address(0x%08X)\n", addr);
 639         /* secondary display supports only quadword aligned memory */
 640         via_write_reg_mask(VIACR, 0x62, (addr >> 2) & 0xFE, 0xFE);
 641         via_write_reg(VIACR, 0x63, (addr >> 10) & 0xFF);
 642         via_write_reg(VIACR, 0x64, (addr >> 18) & 0xFF);
 643         via_write_reg_mask(VIACR, 0xA3, (addr >> 26) & 0x07, 0x07);
 644 }
 645
 646 void via_set_primary_pitch(u32 pitch)
 647 {
 648         DEBUG_MSG(KERN_DEBUG "via_set_primary_pitch(0x%08X)\n", pitch);
 649         /* spec does not say that first adapter skips 3 bits but old
 650          * code did it and seems to be reasonable in analogy to 2nd adapter
 651          */
 652         pitch = pitch >> 3;
 653         via_write_reg(VIACR, 0x13, pitch & 0xFF);
 654         via_write_reg_mask(VIACR, 0x35, (pitch >> (8 - 5)) & 0xE0, 0xE0);
 655 }
 656
 657 void via_set_secondary_pitch(u32 pitch)
 658 {
 659         DEBUG_MSG(KERN_DEBUG "via_set_secondary_pitch(0x%08X)\n", pitch);
 660         pitch = pitch >> 3;
 661         via_write_reg(VIACR, 0x66, pitch & 0xFF);
 662         via_write_reg_mask(VIACR, 0x67, (pitch >> 8) & 0x03, 0x03);
 663         via_write_reg_mask(VIACR, 0x71, (pitch >> (10 - 7)) & 0x80, 0x80);
 664 }
 665
 666 void via_set_primary_color_depth(u8 depth)
 667 {
 668         u8 value;
 669
 670         DEBUG_MSG(KERN_DEBUG "via_set_primary_color_depth(%d)\n", depth);
 671         switch (depth) {
 672         case 8:
 673                 value = 0x00;
 674                 break;
 675         case 15:
 676                 value = 0x04;
 677                 break;
 678         case 16:
 679                 value = 0x14;
 680                 break;
 681         case 24:
 682                 value = 0x0C;
 683                 break;
 684         case 30:
 685                 value = 0x08;
 686                 break;
 687         default:
 688                 printk(KERN_WARNING "via_set_primary_color_depth: "
 689                         "Unsupported depth: %d\n", depth);
 690                 return;
 691         }
 692
 693         via_write_reg_mask(VIASR, 0x15, value, 0x1C);
 694 }
 695
 696 void via_set_secondary_color_depth(u8 depth)
 697 {
 698         u8 value;
 699
 700         DEBUG_MSG(KERN_DEBUG "via_set_secondary_color_depth(%d)\n", depth);
 701         switch (depth) {
 702         case 8:
 703                 value = 0x00;
 704                 break;
 705         case 16:
 706                 value = 0x40;
 707                 break;
 708         case 24:
 709                 value = 0xC0;
 710                 break;
 711         case 30:
 712                 value = 0x80;
 713                 break;
 714         default:
 715                 printk(KERN_WARNING "via_set_secondary_color_depth: "
 716                         "Unsupported depth: %d\n", depth);
 717                 return;
 718         }
 719
 720         via_write_reg_mask(VIACR, 0x67, value, 0xC0);
 721 }
 722
 723 static void set_color_register(u8 index, u8 red, u8 green, u8 blue)
 724 {
 725         outb(0xFF, 0x3C6); /* bit mask of palette */
 726         outb(index, 0x3C8);
 727         outb(red, 0x3C9);
 728         outb(green, 0x3C9);
 729         outb(blue, 0x3C9);
 730 }
 731
 732 void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue)
 733 {
 734         viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01);
 735         set_color_register(index, red, green, blue);
 736 }
 737
 738 void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue)
 739 {
 740         viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01);
 741         set_color_register(index, red, green, blue);
 742 }
 743
 744 void viafb_set_output_path(int device, int set_iga, int output_interface)
 745 {
 746         switch (device) {
 747         case DEVICE_CRT:
 748                 set_crt_output_path(set_iga);
 749                 break;
 750         case DEVICE_DVI:
 751                 set_dvi_output_path(set_iga, output_interface);
 752                 break;
 753         case DEVICE_LCD:
 754                 set_lcd_output_path(set_iga, output_interface);
 755                 break;
 756         }
 757 }
 758
 759 static void set_crt_output_path(int set_iga)
 760 {
 761         viafb_write_reg_mask(CR36, VIACR, 0x00, BIT4 + BIT5);
 762
 763         switch (set_iga) {
 764         case IGA1:
 765                 viafb_write_reg_mask(SR16, VIASR, 0x00, BIT6);
 766                 break;
 767         case IGA2:
 768                 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
 769                 viafb_write_reg_mask(SR16, VIASR, 0x40, BIT6);
 770                 break;
 771         }
 772 }
 773
 774 static void dvi_patch_skew_dvp0(void)
 775 {
 776         /* Reset data driving first: */
 777         viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);
 778         viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);
 779
 780         switch (viaparinfo->chip_info->gfx_chip_name) {
 781         case UNICHROME_P4M890:
 782                 {
 783                         if ((viaparinfo->tmds_setting_info->h_active == 1600) &&
 784                                 (viaparinfo->tmds_setting_info->v_active ==
 785                                 1200))
 786                                 viafb_write_reg_mask(CR96, VIACR, 0x03,
 787                                                BIT0 + BIT1 + BIT2);
 788                         else
 789                                 viafb_write_reg_mask(CR96, VIACR, 0x07,
 790                                                BIT0 + BIT1 + BIT2);
 791                         break;
 792                 }
 793
 794         case UNICHROME_P4M900:
 795                 {
 796                         viafb_write_reg_mask(CR96, VIACR, 0x07,
 797                                        BIT0 + BIT1 + BIT2 + BIT3);
 798                         viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);
 799                         viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);
 800                         break;
 801                 }
 802
 803         default:
 804                 {
 805                         break;
 806                 }
 807         }
 808 }
 809
 810 static void dvi_patch_skew_dvp1(void)
 811 {
 812         switch (viaparinfo->chip_info->gfx_chip_name) {
 813         case UNICHROME_CX700:
 814                 {
 815                         break;
 816                 }
 817
 818         default:
 819                 {
 820                         break;
 821                 }
 822         }
 823 }
 824
 825 static void dvi_patch_skew_dvp_low(void)
 826 {
 827         switch (viaparinfo->chip_info->gfx_chip_name) {
 828         case UNICHROME_K8M890:
 829                 {
 830                         viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
 831                         break;
 832                 }
 833
 834         case UNICHROME_P4M900:
 835                 {
 836                         viafb_write_reg_mask(CR99, VIACR, 0x08,
 837                                        BIT0 + BIT1 + BIT2 + BIT3);
 838                         break;
 839                 }
 840
 841         case UNICHROME_P4M890:
 842                 {
 843                         viafb_write_reg_mask(CR99, VIACR, 0x0F,
 844                                        BIT0 + BIT1 + BIT2 + BIT3);
 845                         break;
 846                 }
 847
 848         default:
 849                 {
 850                         break;
 851                 }
 852         }
 853 }
 854
 855 static void set_dvi_output_path(int set_iga, int output_interface)
 856 {
 857         switch (output_interface) {
 858         case INTERFACE_DVP0:
 859                 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);
 860
 861                 if (set_iga == IGA1) {
 862                         viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
 863                         viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 +
 864                                 BIT5 + BIT7);
 865                 } else {
 866                         viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
 867                         viafb_write_reg_mask(CR6C, VIACR, 0xA1, BIT0 +
 868                                 BIT5 + BIT7);
 869                 }
 870
 871                 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT7 + BIT6);
 872
 873                 dvi_patch_skew_dvp0();
 874                 break;
 875
 876         case INTERFACE_DVP1:
 877                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
 878                         if (set_iga == IGA1)
 879                                 viafb_write_reg_mask(CR93, VIACR, 0x21,
 880                                                BIT0 + BIT5 + BIT7);
 881                         else
 882                                 viafb_write_reg_mask(CR93, VIACR, 0xA1,
 883                                                BIT0 + BIT5 + BIT7);
 884                 } else {
 885                         if (set_iga == IGA1)
 886                                 viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
 887                         else
 888                                 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
 889                 }
 890
 891                 viafb_write_reg_mask(SR1E, VIASR, 0x30, BIT4 + BIT5);
 892                 dvi_patch_skew_dvp1();
 893                 break;
 894         case INTERFACE_DFP_HIGH:
 895                 if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266) {
 896                         if (set_iga == IGA1) {
 897                                 viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
 898                                 viafb_write_reg_mask(CR97, VIACR, 0x03,
 899                                                BIT0 + BIT1 + BIT4);
 900                         } else {
 901                                 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
 902                                 viafb_write_reg_mask(CR97, VIACR, 0x13,
 903                                                BIT0 + BIT1 + BIT4);
 904                         }
 905                 }
 906                 viafb_write_reg_mask(SR2A, VIASR, 0x0C, BIT2 + BIT3);
 907                 break;
 908
 909         case INTERFACE_DFP_LOW:
 910                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
 911                         break;
 912
 913                 if (set_iga == IGA1) {
 914                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
 915                         viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
 916                 } else {
 917                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
 918                         viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
 919                 }
 920
 921                 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
 922                 dvi_patch_skew_dvp_low();
 923                 break;
 924
 925         case INTERFACE_TMDS:
 926                 if (set_iga == IGA1)
 927                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
 928                 else
 929                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
 930                 break;
 931         }
 932
 933         if (set_iga == IGA2) {
 934                 enable_second_display_channel();
 935                 /* Disable LCD Scaling */
 936                 viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);
 937         }
 938 }
 939
 940 static void set_lcd_output_path(int set_iga, int output_interface)
 941 {
 942         DEBUG_MSG(KERN_INFO
 943                   "set_lcd_output_path, iga:%d,out_interface:%d\n",
 944                   set_iga, output_interface);
 945         switch (set_iga) {
 946         case IGA1:
 947                 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
 948                 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
 949
 950                 disable_second_display_channel();
 951                 break;
 952
 953         case IGA2:
 954                 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
 955                 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
 956
 957                 enable_second_display_channel();
 958                 break;
 959         }
 960
 961         switch (output_interface) {
 962         case INTERFACE_DVP0:
 963                 if (set_iga == IGA1) {
 964                         viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
 965                 } else {
 966                         viafb_write_reg(CR91, VIACR, 0x00);
 967                         viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
 968                 }
 969                 break;
 970
 971         case INTERFACE_DVP1:
 972                 if (set_iga == IGA1)
 973                         viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
 974                 else {
 975                         viafb_write_reg(CR91, VIACR, 0x00);
 976                         viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
 977                 }
 978                 break;
 979
 980         case INTERFACE_DFP_HIGH:
 981                 if (set_iga == IGA1)
 982                         viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
 983                 else {
 984                         viafb_write_reg(CR91, VIACR, 0x00);
 985                         viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
 986                         viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
 987                 }
 988                 break;
 989
 990         case INTERFACE_DFP_LOW:
 991                 if (set_iga == IGA1)
 992                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
 993                 else {
 994                         viafb_write_reg(CR91, VIACR, 0x00);
 995                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
 996                         viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
 997                 }
 998
 999                 break;
1000
1001         case INTERFACE_DFP:
1002                 if ((UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name)
1003                     || (UNICHROME_P4M890 ==
1004                     viaparinfo->chip_info->gfx_chip_name))
1005                         viafb_write_reg_mask(CR97, VIACR, 0x84,
1006                                        BIT7 + BIT2 + BIT1 + BIT0);
1007                 if (set_iga == IGA1) {
1008                         viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
1009                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
1010                 } else {
1011                         viafb_write_reg(CR91, VIACR, 0x00);
1012                         viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
1013                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
1014                 }
1015                 break;
1016
1017         case INTERFACE_LVDS0:
1018         case INTERFACE_LVDS0LVDS1:
1019                 if (set_iga == IGA1)
1020                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
1021                 else
1022                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
1023
1024                 break;
1025
1026         case INTERFACE_LVDS1:
1027                 if (set_iga == IGA1)
1028                         viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
1029                 else
1030                         viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
1031                 break;
1032         }
1033 }
1034
1035 static void load_fix_bit_crtc_reg(void)
1036 {
1037         /* always set to 1 */
1038         viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
1039         /* line compare should set all bits = 1 (extend modes) */
1040         viafb_write_reg(CR18, VIACR, 0xff);
1041         /* line compare should set all bits = 1 (extend modes) */
1042         viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4);
1043         /* line compare should set all bits = 1 (extend modes) */
1044         viafb_write_reg_mask(CR09, VIACR, 0x40, BIT6);
1045         /* line compare should set all bits = 1 (extend modes) */
1046         viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
1047         /* line compare should set all bits = 1 (extend modes) */
1048         viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
1049         /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */
1050         /* extend mode always set to e3h */
1051         viafb_write_reg(CR17, VIACR, 0xe3);
1052         /* extend mode always set to 0h */
1053         viafb_write_reg(CR08, VIACR, 0x00);
1054         /* extend mode always set to 0h */
1055         viafb_write_reg(CR14, VIACR, 0x00);
1056
1057         /* If K8M800, enable Prefetch Mode. */
1058         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
1059                 || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890))
1060                 viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);
1061         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
1062             && (viaparinfo->chip_info->gfx_chip_revision == CLE266_REVISION_AX))
1063                 viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);
1064
1065 }
1066
1067 void viafb_load_reg(int timing_value, int viafb_load_reg_num,
1068         struct io_register *reg,
1069               int io_type)
1070 {
1071         int reg_mask;
1072         int bit_num = 0;
1073         int data;
1074         int i, j;
1075         int shift_next_reg;
1076         int start_index, end_index, cr_index;
1077         u16 get_bit;
1078
1079         for (i = 0; i < viafb_load_reg_num; i++) {
1080                 reg_mask = 0;
1081                 data = 0;
1082                 start_index = reg[i].start_bit;
1083                 end_index = reg[i].end_bit;
1084                 cr_index = reg[i].io_addr;
1085
1086                 shift_next_reg = bit_num;
1087                 for (j = start_index; j <= end_index; j++) {
1088                         /*if (bit_num==8) timing_value = timing_value >>8; */
1089                         reg_mask = reg_mask | (BIT0 << j);
1090                         get_bit = (timing_value & (BIT0 << bit_num));
1091                         data =
1092                             data | ((get_bit >> shift_next_reg) << start_index);
1093                         bit_num++;
1094                 }
1095                 if (io_type == VIACR)
1096                         viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);
1097                 else
1098                         viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);
1099         }
1100
1101 }
1102
1103 /* Write Registers */
1104 void viafb_write_regx(struct io_reg RegTable[], int ItemNum)
1105 {
1106         int i;
1107         unsigned char RegTemp;
1108
1109         /*DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum ); */
1110
1111         for (i = 0; i < ItemNum; i++) {
1112                 outb(RegTable[i].index, RegTable[i].port);
1113                 RegTemp = inb(RegTable[i].port + 1);
1114                 RegTemp = (RegTemp & (~RegTable[i].mask)) | RegTable[i].value;
1115                 outb(RegTemp, RegTable[i].port + 1);
1116         }
1117 }
1118
1119 void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga)
1120 {
1121         int reg_value;
1122         int viafb_load_reg_num;
1123         struct io_register *reg = NULL;
1124
1125         switch (set_iga) {
1126         case IGA1:
1127                 reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1128                 viafb_load_reg_num = fetch_count_reg.
1129                         iga1_fetch_count_reg.reg_num;
1130                 reg = fetch_count_reg.iga1_fetch_count_reg.reg;
1131                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1132                 break;
1133         case IGA2:
1134                 reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1135                 viafb_load_reg_num = fetch_count_reg.
1136                         iga2_fetch_count_reg.reg_num;
1137                 reg = fetch_count_reg.iga2_fetch_count_reg.reg;
1138                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1139                 break;
1140         }
1141
1142 }
1143
1144 void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1145 {
1146         int reg_value;
1147         int viafb_load_reg_num;
1148         struct io_register *reg = NULL;
1149         int iga1_fifo_max_depth = 0, iga1_fifo_threshold =
1150             0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0;
1151         int iga2_fifo_max_depth = 0, iga2_fifo_threshold =
1152             0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0;
1153
1154         if (set_iga == IGA1) {
1155                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1156                         iga1_fifo_max_depth = K800_IGA1_FIFO_MAX_DEPTH;
1157                         iga1_fifo_threshold = K800_IGA1_FIFO_THRESHOLD;
1158                         iga1_fifo_high_threshold =
1159                             K800_IGA1_FIFO_HIGH_THRESHOLD;
1160                         /* If resolution > 1280x1024, expire length = 64, else
1161                            expire length = 128 */
1162                         if ((hor_active > 1280) && (ver_active > 1024))
1163                                 iga1_display_queue_expire_num = 16;
1164                         else
1165                                 iga1_display_queue_expire_num =
1166                                     K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1167
1168                 }
1169
1170                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1171                         iga1_fifo_max_depth = P880_IGA1_FIFO_MAX_DEPTH;
1172                         iga1_fifo_threshold = P880_IGA1_FIFO_THRESHOLD;
1173                         iga1_fifo_high_threshold =
1174                             P880_IGA1_FIFO_HIGH_THRESHOLD;
1175                         iga1_display_queue_expire_num =
1176                             P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1177
1178                         /* If resolution > 1280x1024, expire length = 64, else
1179                            expire length = 128 */
1180                         if ((hor_active > 1280) && (ver_active > 1024))
1181                                 iga1_display_queue_expire_num = 16;
1182                         else
1183                                 iga1_display_queue_expire_num =
1184                                     P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1185                 }
1186
1187                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1188                         iga1_fifo_max_depth = CN700_IGA1_FIFO_MAX_DEPTH;
1189                         iga1_fifo_threshold = CN700_IGA1_FIFO_THRESHOLD;
1190                         iga1_fifo_high_threshold =
1191                             CN700_IGA1_FIFO_HIGH_THRESHOLD;
1192
1193                         /* If resolution > 1280x1024, expire length = 64,
1194                            else expire length = 128 */
1195                         if ((hor_active > 1280) && (ver_active > 1024))
1196                                 iga1_display_queue_expire_num = 16;
1197                         else
1198                                 iga1_display_queue_expire_num =
1199                                     CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1200                 }
1201
1202                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1203                         iga1_fifo_max_depth = CX700_IGA1_FIFO_MAX_DEPTH;
1204                         iga1_fifo_threshold = CX700_IGA1_FIFO_THRESHOLD;
1205                         iga1_fifo_high_threshold =
1206                             CX700_IGA1_FIFO_HIGH_THRESHOLD;
1207                         iga1_display_queue_expire_num =
1208                             CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1209                 }
1210
1211                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1212                         iga1_fifo_max_depth = K8M890_IGA1_FIFO_MAX_DEPTH;
1213                         iga1_fifo_threshold = K8M890_IGA1_FIFO_THRESHOLD;
1214                         iga1_fifo_high_threshold =
1215                             K8M890_IGA1_FIFO_HIGH_THRESHOLD;
1216                         iga1_display_queue_expire_num =
1217                             K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1218                 }
1219
1220                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1221                         iga1_fifo_max_depth = P4M890_IGA1_FIFO_MAX_DEPTH;
1222                         iga1_fifo_threshold = P4M890_IGA1_FIFO_THRESHOLD;
1223                         iga1_fifo_high_threshold =
1224                             P4M890_IGA1_FIFO_HIGH_THRESHOLD;
1225                         iga1_display_queue_expire_num =
1226                             P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1227                 }
1228
1229                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1230                         iga1_fifo_max_depth = P4M900_IGA1_FIFO_MAX_DEPTH;
1231                         iga1_fifo_threshold = P4M900_IGA1_FIFO_THRESHOLD;
1232                         iga1_fifo_high_threshold =
1233                             P4M900_IGA1_FIFO_HIGH_THRESHOLD;
1234                         iga1_display_queue_expire_num =
1235                             P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1236                 }
1237
1238                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1239                         iga1_fifo_max_depth = VX800_IGA1_FIFO_MAX_DEPTH;
1240                         iga1_fifo_threshold = VX800_IGA1_FIFO_THRESHOLD;
1241                         iga1_fifo_high_threshold =
1242                             VX800_IGA1_FIFO_HIGH_THRESHOLD;
1243                         iga1_display_queue_expire_num =
1244                             VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1245                 }
1246
1247                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1248                         iga1_fifo_max_depth = VX855_IGA1_FIFO_MAX_DEPTH;
1249                         iga1_fifo_threshold = VX855_IGA1_FIFO_THRESHOLD;
1250                         iga1_fifo_high_threshold =
1251                             VX855_IGA1_FIFO_HIGH_THRESHOLD;
1252                         iga1_display_queue_expire_num =
1253                             VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1254                 }
1255
1256                 /* Set Display FIFO Depath Select */
1257                 reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
1258                 viafb_load_reg_num =
1259                     display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num;
1260                 reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg;
1261                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1262
1263                 /* Set Display FIFO Threshold Select */
1264                 reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold);
1265                 viafb_load_reg_num =
1266                     fifo_threshold_select_reg.
1267                     iga1_fifo_threshold_select_reg.reg_num;
1268                 reg =
1269                     fifo_threshold_select_reg.
1270                     iga1_fifo_threshold_select_reg.reg;
1271                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1272
1273                 /* Set FIFO High Threshold Select */
1274                 reg_value =
1275                     IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold);
1276                 viafb_load_reg_num =
1277                     fifo_high_threshold_select_reg.
1278                     iga1_fifo_high_threshold_select_reg.reg_num;
1279                 reg =
1280                     fifo_high_threshold_select_reg.
1281                     iga1_fifo_high_threshold_select_reg.reg;
1282                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1283
1284                 /* Set Display Queue Expire Num */
1285                 reg_value =
1286                     IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1287                     (iga1_display_queue_expire_num);
1288                 viafb_load_reg_num =
1289                     display_queue_expire_num_reg.
1290                     iga1_display_queue_expire_num_reg.reg_num;
1291                 reg =
1292                     display_queue_expire_num_reg.
1293                     iga1_display_queue_expire_num_reg.reg;
1294                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1295
1296         } else {
1297                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1298                         iga2_fifo_max_depth = K800_IGA2_FIFO_MAX_DEPTH;
1299                         iga2_fifo_threshold = K800_IGA2_FIFO_THRESHOLD;
1300                         iga2_fifo_high_threshold =
1301                             K800_IGA2_FIFO_HIGH_THRESHOLD;
1302
1303                         /* If resolution > 1280x1024, expire length = 64,
1304                            else  expire length = 128 */
1305                         if ((hor_active > 1280) && (ver_active > 1024))
1306                                 iga2_display_queue_expire_num = 16;
1307                         else
1308                                 iga2_display_queue_expire_num =
1309                                     K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1310                 }
1311
1312                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1313                         iga2_fifo_max_depth = P880_IGA2_FIFO_MAX_DEPTH;
1314                         iga2_fifo_threshold = P880_IGA2_FIFO_THRESHOLD;
1315                         iga2_fifo_high_threshold =
1316                             P880_IGA2_FIFO_HIGH_THRESHOLD;
1317
1318                         /* If resolution > 1280x1024, expire length = 64,
1319                            else  expire length = 128 */
1320                         if ((hor_active > 1280) && (ver_active > 1024))
1321                                 iga2_display_queue_expire_num = 16;
1322                         else
1323                                 iga2_display_queue_expire_num =
1324                                     P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1325                 }
1326
1327                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1328                         iga2_fifo_max_depth = CN700_IGA2_FIFO_MAX_DEPTH;
1329                         iga2_fifo_threshold = CN700_IGA2_FIFO_THRESHOLD;
1330                         iga2_fifo_high_threshold =
1331                             CN700_IGA2_FIFO_HIGH_THRESHOLD;
1332
1333                         /* If resolution > 1280x1024, expire length = 64,
1334                            else expire length = 128 */
1335                         if ((hor_active > 1280) && (ver_active > 1024))
1336                                 iga2_display_queue_expire_num = 16;
1337                         else
1338                                 iga2_display_queue_expire_num =
1339                                     CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1340                 }
1341
1342                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1343                         iga2_fifo_max_depth = CX700_IGA2_FIFO_MAX_DEPTH;
1344                         iga2_fifo_threshold = CX700_IGA2_FIFO_THRESHOLD;
1345                         iga2_fifo_high_threshold =
1346                             CX700_IGA2_FIFO_HIGH_THRESHOLD;
1347                         iga2_display_queue_expire_num =
1348                             CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1349                 }
1350
1351                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1352                         iga2_fifo_max_depth = K8M890_IGA2_FIFO_MAX_DEPTH;
1353                         iga2_fifo_threshold = K8M890_IGA2_FIFO_THRESHOLD;
1354                         iga2_fifo_high_threshold =
1355                             K8M890_IGA2_FIFO_HIGH_THRESHOLD;
1356                         iga2_display_queue_expire_num =
1357                             K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1358                 }
1359
1360                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1361                         iga2_fifo_max_depth = P4M890_IGA2_FIFO_MAX_DEPTH;
1362                         iga2_fifo_threshold = P4M890_IGA2_FIFO_THRESHOLD;
1363                         iga2_fifo_high_threshold =
1364                             P4M890_IGA2_FIFO_HIGH_THRESHOLD;
1365                         iga2_display_queue_expire_num =
1366                             P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1367                 }
1368
1369                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1370                         iga2_fifo_max_depth = P4M900_IGA2_FIFO_MAX_DEPTH;
1371                         iga2_fifo_threshold = P4M900_IGA2_FIFO_THRESHOLD;
1372                         iga2_fifo_high_threshold =
1373                             P4M900_IGA2_FIFO_HIGH_THRESHOLD;
1374                         iga2_display_queue_expire_num =
1375                             P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1376                 }
1377
1378                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1379                         iga2_fifo_max_depth = VX800_IGA2_FIFO_MAX_DEPTH;
1380                         iga2_fifo_threshold = VX800_IGA2_FIFO_THRESHOLD;
1381                         iga2_fifo_high_threshold =
1382                             VX800_IGA2_FIFO_HIGH_THRESHOLD;
1383                         iga2_display_queue_expire_num =
1384                             VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1385                 }
1386
1387                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1388                         iga2_fifo_max_depth = VX855_IGA2_FIFO_MAX_DEPTH;
1389                         iga2_fifo_threshold = VX855_IGA2_FIFO_THRESHOLD;
1390                         iga2_fifo_high_threshold =
1391                             VX855_IGA2_FIFO_HIGH_THRESHOLD;
1392                         iga2_display_queue_expire_num =
1393                             VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1394                 }
1395
1396                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1397                         /* Set Display FIFO Depath Select */
1398                         reg_value =
1399                             IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth)
1400                             - 1;
1401                         /* Patch LCD in IGA2 case */
1402                         viafb_load_reg_num =
1403                             display_fifo_depth_reg.
1404                             iga2_fifo_depth_select_reg.reg_num;
1405                         reg =
1406                             display_fifo_depth_reg.
1407                             iga2_fifo_depth_select_reg.reg;
1408                         viafb_load_reg(reg_value,
1409                                 viafb_load_reg_num, reg, VIACR);
1410                 } else {
1411
1412                         /* Set Display FIFO Depath Select */
1413                         reg_value =
1414                             IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth);
1415                         viafb_load_reg_num =
1416                             display_fifo_depth_reg.
1417                             iga2_fifo_depth_select_reg.reg_num;
1418                         reg =
1419                             display_fifo_depth_reg.
1420                             iga2_fifo_depth_select_reg.reg;
1421                         viafb_load_reg(reg_value,
1422                                 viafb_load_reg_num, reg, VIACR);
1423                 }
1424
1425                 /* Set Display FIFO Threshold Select */
1426                 reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold);
1427                 viafb_load_reg_num =
1428                     fifo_threshold_select_reg.
1429                     iga2_fifo_threshold_select_reg.reg_num;
1430                 reg =
1431                     fifo_threshold_select_reg.
1432                     iga2_fifo_threshold_select_reg.reg;
1433                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1434
1435                 /* Set FIFO High Threshold Select */
1436                 reg_value =
1437                     IGA2_FIFO_HIGH_THRESHOLD_FORMULA(iga2_fifo_high_threshold);
1438                 viafb_load_reg_num =
1439                     fifo_high_threshold_select_reg.
1440                     iga2_fifo_high_threshold_select_reg.reg_num;
1441                 reg =
1442                     fifo_high_threshold_select_reg.
1443                     iga2_fifo_high_threshold_select_reg.reg;
1444                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1445
1446                 /* Set Display Queue Expire Num */
1447                 reg_value =
1448                     IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1449                     (iga2_display_queue_expire_num);
1450                 viafb_load_reg_num =
1451                     display_queue_expire_num_reg.
1452                     iga2_display_queue_expire_num_reg.reg_num;
1453                 reg =
1454                     display_queue_expire_num_reg.
1455                     iga2_display_queue_expire_num_reg.reg;
1456                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1457
1458         }
1459
1460 }
1461
1462 u32 viafb_get_clk_value(int clk)
1463 {
1464         int i;
1465
1466         for (i = 0; i < NUM_TOTAL_PLL_TABLE; i++) {
1467                 if (clk == pll_value[i].clk) {
1468                         switch (viaparinfo->chip_info->gfx_chip_name) {
1469                         case UNICHROME_CLE266:
1470                         case UNICHROME_K400:
1471                                 return pll_value[i].cle266_pll;
1472
1473                         case UNICHROME_K800:
1474                         case UNICHROME_PM800:
1475                         case UNICHROME_CN700:
1476                                 return pll_value[i].k800_pll;
1477
1478                         case UNICHROME_CX700:
1479                         case UNICHROME_K8M890:
1480                         case UNICHROME_P4M890:
1481                         case UNICHROME_P4M900:
1482                         case UNICHROME_VX800:
1483                                 return pll_value[i].cx700_pll;
1484                         case UNICHROME_VX855:
1485                                 return pll_value[i].vx855_pll;
1486                         }
1487                 }
1488         }
1489
1490         DEBUG_MSG(KERN_INFO "Can't find match PLL value\n\n");
1491         return 0;
1492 }
1493
1494 /* Set VCLK*/
1495 void viafb_set_vclock(u32 CLK, int set_iga)
1496 {
1497         unsigned char RegTemp;
1498
1499         /* H.W. Reset : ON */
1500         viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1501
1502         if (set_iga == IGA1) {
1503                 /* Change D,N FOR VCLK */
1504                 switch (viaparinfo->chip_info->gfx_chip_name) {
1505                 case UNICHROME_CLE266:
1506                 case UNICHROME_K400:
1507                         viafb_write_reg(SR46, VIASR, CLK / 0x100);
1508                         viafb_write_reg(SR47, VIASR, CLK % 0x100);
1509                         break;
1510
1511                 case UNICHROME_K800:
1512                 case UNICHROME_PM800:
1513                 case UNICHROME_CN700:
1514                 case UNICHROME_CX700:
1515                 case UNICHROME_K8M890:
1516                 case UNICHROME_P4M890:
1517                 case UNICHROME_P4M900:
1518                 case UNICHROME_VX800:
1519                 case UNICHROME_VX855:
1520                         viafb_write_reg(SR44, VIASR, CLK / 0x10000);
1521                         DEBUG_MSG(KERN_INFO "\nSR44=%x", CLK / 0x10000);
1522                         viafb_write_reg(SR45, VIASR, (CLK & 0xFFFF) / 0x100);
1523                         DEBUG_MSG(KERN_INFO "\nSR45=%x",
1524                                   (CLK & 0xFFFF) / 0x100);
1525                         viafb_write_reg(SR46, VIASR, CLK % 0x100);
1526                         DEBUG_MSG(KERN_INFO "\nSR46=%x", CLK % 0x100);
1527                         break;
1528                 }
1529         }
1530
1531         if (set_iga == IGA2) {
1532                 /* Change D,N FOR LCK */
1533                 switch (viaparinfo->chip_info->gfx_chip_name) {
1534                 case UNICHROME_CLE266:
1535                 case UNICHROME_K400:
1536                         viafb_write_reg(SR44, VIASR, CLK / 0x100);
1537                         viafb_write_reg(SR45, VIASR, CLK % 0x100);
1538                         break;
1539
1540                 case UNICHROME_K800:
1541                 case UNICHROME_PM800:
1542                 case UNICHROME_CN700:
1543                 case UNICHROME_CX700:
1544                 case UNICHROME_K8M890:
1545                 case UNICHROME_P4M890:
1546                 case UNICHROME_P4M900:
1547                 case UNICHROME_VX800:
1548                 case UNICHROME_VX855:
1549                         viafb_write_reg(SR4A, VIASR, CLK / 0x10000);
1550                         viafb_write_reg(SR4B, VIASR, (CLK & 0xFFFF) / 0x100);
1551                         viafb_write_reg(SR4C, VIASR, CLK % 0x100);
1552                         break;
1553                 }
1554         }
1555
1556         /* H.W. Reset : OFF */
1557         viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1558
1559         /* Reset PLL */
1560         if (set_iga == IGA1) {
1561                 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
1562                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
1563         }
1564
1565         if (set_iga == IGA2) {
1566                 viafb_write_reg_mask(SR40, VIASR, 0x01, BIT0);
1567                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT0);
1568         }
1569
1570         /* Fire! */
1571         RegTemp = inb(VIARMisc);
1572         outb(RegTemp | (BIT2 + BIT3), VIAWMisc);
1573 }
1574
1575 void viafb_load_crtc_timing(struct display_timing device_timing,
1576         int set_iga)
1577 {
1578         int i;
1579         int viafb_load_reg_num = 0;
1580         int reg_value = 0;
1581         struct io_register *reg = NULL;
1582
1583         viafb_unlock_crt();
1584
1585         for (i = 0; i < 12; i++) {
1586                 if (set_iga == IGA1) {
1587                         switch (i) {
1588                         case H_TOTAL_INDEX:
1589                                 reg_value =
1590                                     IGA1_HOR_TOTAL_FORMULA(device_timing.
1591                                                            hor_total);
1592                                 viafb_load_reg_num =
1593                                         iga1_crtc_reg.hor_total.reg_num;
1594                                 reg = iga1_crtc_reg.hor_total.reg;
1595                                 break;
1596                         case H_ADDR_INDEX:
1597                                 reg_value =
1598                                     IGA1_HOR_ADDR_FORMULA(device_timing.
1599                                                           hor_addr);
1600                                 viafb_load_reg_num =
1601                                         iga1_crtc_reg.hor_addr.reg_num;
1602                                 reg = iga1_crtc_reg.hor_addr.reg;
1603                                 break;
1604                         case H_BLANK_START_INDEX:
1605                                 reg_value =
1606                                     IGA1_HOR_BLANK_START_FORMULA
1607                                     (device_timing.hor_blank_start);
1608                                 viafb_load_reg_num =
1609                                     iga1_crtc_reg.hor_blank_start.reg_num;
1610                                 reg = iga1_crtc_reg.hor_blank_start.reg;
1611                                 break;
1612                         case H_BLANK_END_INDEX:
1613                                 reg_value =
1614                                     IGA1_HOR_BLANK_END_FORMULA
1615                                     (device_timing.hor_blank_start,
1616                                      device_timing.hor_blank_end);
1617                                 viafb_load_reg_num =
1618                                     iga1_crtc_reg.hor_blank_end.reg_num;
1619                                 reg = iga1_crtc_reg.hor_blank_end.reg;
1620                                 break;
1621                         case H_SYNC_START_INDEX:
1622                                 reg_value =
1623                                     IGA1_HOR_SYNC_START_FORMULA
1624                                     (device_timing.hor_sync_start);
1625                                 viafb_load_reg_num =
1626                                     iga1_crtc_reg.hor_sync_start.reg_num;
1627                                 reg = iga1_crtc_reg.hor_sync_start.reg;
1628                                 break;
1629                         case H_SYNC_END_INDEX:
1630                                 reg_value =
1631                                     IGA1_HOR_SYNC_END_FORMULA
1632                                     (device_timing.hor_sync_start,
1633                                      device_timing.hor_sync_end);
1634                                 viafb_load_reg_num =
1635                                     iga1_crtc_reg.hor_sync_end.reg_num;
1636                                 reg = iga1_crtc_reg.hor_sync_end.reg;
1637                                 break;
1638                         case V_TOTAL_INDEX:
1639                                 reg_value =
1640                                     IGA1_VER_TOTAL_FORMULA(device_timing.
1641                                                            ver_total);
1642                                 viafb_load_reg_num =
1643                                         iga1_crtc_reg.ver_total.reg_num;
1644                                 reg = iga1_crtc_reg.ver_total.reg;
1645                                 break;
1646                         case V_ADDR_INDEX:
1647                                 reg_value =
1648                                     IGA1_VER_ADDR_FORMULA(device_timing.
1649                                                           ver_addr);
1650                                 viafb_load_reg_num =
1651                                         iga1_crtc_reg.ver_addr.reg_num;
1652                                 reg = iga1_crtc_reg.ver_addr.reg;
1653                                 break;
1654                         case V_BLANK_START_INDEX:
1655                                 reg_value =
1656                                     IGA1_VER_BLANK_START_FORMULA
1657                                     (device_timing.ver_blank_start);
1658                                 viafb_load_reg_num =
1659                                     iga1_crtc_reg.ver_blank_start.reg_num;
1660                                 reg = iga1_crtc_reg.ver_blank_start.reg;
1661                                 break;
1662                         case V_BLANK_END_INDEX:
1663                                 reg_value =
1664                                     IGA1_VER_BLANK_END_FORMULA
1665                                     (device_timing.ver_blank_start,
1666                                      device_timing.ver_blank_end);
1667                                 viafb_load_reg_num =
1668                                     iga1_crtc_reg.ver_blank_end.reg_num;
1669                                 reg = iga1_crtc_reg.ver_blank_end.reg;
1670                                 break;
1671                         case V_SYNC_START_INDEX:
1672                                 reg_value =
1673                                     IGA1_VER_SYNC_START_FORMULA
1674                                     (device_timing.ver_sync_start);
1675                                 viafb_load_reg_num =
1676                                     iga1_crtc_reg.ver_sync_start.reg_num;
1677                                 reg = iga1_crtc_reg.ver_sync_start.reg;
1678                                 break;
1679                         case V_SYNC_END_INDEX:
1680                                 reg_value =
1681                                     IGA1_VER_SYNC_END_FORMULA
1682                                     (device_timing.ver_sync_start,
1683                                      device_timing.ver_sync_end);
1684                                 viafb_load_reg_num =
1685                                     iga1_crtc_reg.ver_sync_end.reg_num;
1686                                 reg = iga1_crtc_reg.ver_sync_end.reg;
1687                                 break;
1688
1689                         }
1690                 }
1691
1692                 if (set_iga == IGA2) {
1693                         switch (i) {
1694                         case H_TOTAL_INDEX:
1695                                 reg_value =
1696                                     IGA2_HOR_TOTAL_FORMULA(device_timing.
1697                                                            hor_total);
1698                                 viafb_load_reg_num =
1699                                         iga2_crtc_reg.hor_total.reg_num;
1700                                 reg = iga2_crtc_reg.hor_total.reg;
1701                                 break;
1702                         case H_ADDR_INDEX:
1703                                 reg_value =
1704                                     IGA2_HOR_ADDR_FORMULA(device_timing.
1705                                                           hor_addr);
1706                                 viafb_load_reg_num =
1707                                         iga2_crtc_reg.hor_addr.reg_num;
1708                                 reg = iga2_crtc_reg.hor_addr.reg;
1709                                 break;
1710                         case H_BLANK_START_INDEX:
1711                                 reg_value =
1712                                     IGA2_HOR_BLANK_START_FORMULA
1713                                     (device_timing.hor_blank_start);
1714                                 viafb_load_reg_num =
1715                                     iga2_crtc_reg.hor_blank_start.reg_num;
1716                                 reg = iga2_crtc_reg.hor_blank_start.reg;
1717                                 break;
1718                         case H_BLANK_END_INDEX:
1719                                 reg_value =
1720                                     IGA2_HOR_BLANK_END_FORMULA
1721                                     (device_timing.hor_blank_start,
1722                                      device_timing.hor_blank_end);
1723                                 viafb_load_reg_num =
1724                                     iga2_crtc_reg.hor_blank_end.reg_num;
1725                                 reg = iga2_crtc_reg.hor_blank_end.reg;
1726                                 break;
1727                         case H_SYNC_START_INDEX:
1728                                 reg_value =
1729                                     IGA2_HOR_SYNC_START_FORMULA
1730                                     (device_timing.hor_sync_start);
1731                                 if (UNICHROME_CN700 <=
1732                                         viaparinfo->chip_info->gfx_chip_name)
1733                                         viafb_load_reg_num =
1734                                             iga2_crtc_reg.hor_sync_start.
1735                                             reg_num;
1736                                 else
1737                                         viafb_load_reg_num = 3;
1738                                 reg = iga2_crtc_reg.hor_sync_start.reg;
1739                                 break;
1740                         case H_SYNC_END_INDEX:
1741                                 reg_value =
1742                                     IGA2_HOR_SYNC_END_FORMULA
1743                                     (device_timing.hor_sync_start,
1744                                      device_timing.hor_sync_end);
1745                                 viafb_load_reg_num =
1746                                     iga2_crtc_reg.hor_sync_end.reg_num;
1747                                 reg = iga2_crtc_reg.hor_sync_end.reg;
1748                                 break;
1749                         case V_TOTAL_INDEX:
1750                                 reg_value =
1751                                     IGA2_VER_TOTAL_FORMULA(device_timing.
1752                                                            ver_total);
1753                                 viafb_load_reg_num =
1754                                         iga2_crtc_reg.ver_total.reg_num;
1755                                 reg = iga2_crtc_reg.ver_total.reg;
1756                                 break;
1757                         case V_ADDR_INDEX:
1758                                 reg_value =
1759                                     IGA2_VER_ADDR_FORMULA(device_timing.
1760                                                           ver_addr);
1761                                 viafb_load_reg_num =
1762                                         iga2_crtc_reg.ver_addr.reg_num;
1763                                 reg = iga2_crtc_reg.ver_addr.reg;
1764                                 break;
1765                         case V_BLANK_START_INDEX:
1766                                 reg_value =
1767                                     IGA2_VER_BLANK_START_FORMULA
1768                                     (device_timing.ver_blank_start);
1769                                 viafb_load_reg_num =
1770                                     iga2_crtc_reg.ver_blank_start.reg_num;
1771                                 reg = iga2_crtc_reg.ver_blank_start.reg;
1772                                 break;
1773                         case V_BLANK_END_INDEX:
1774                                 reg_value =
1775                                     IGA2_VER_BLANK_END_FORMULA
1776                                     (device_timing.ver_blank_start,
1777                                      device_timing.ver_blank_end);
1778                                 viafb_load_reg_num =
1779                                     iga2_crtc_reg.ver_blank_end.reg_num;
1780                                 reg = iga2_crtc_reg.ver_blank_end.reg;
1781                                 break;
1782                         case V_SYNC_START_INDEX:
1783                                 reg_value =
1784                                     IGA2_VER_SYNC_START_FORMULA
1785                                     (device_timing.ver_sync_start);
1786                                 viafb_load_reg_num =
1787                                     iga2_crtc_reg.ver_sync_start.reg_num;
1788                                 reg = iga2_crtc_reg.ver_sync_start.reg;
1789                                 break;
1790                         case V_SYNC_END_INDEX:
1791                                 reg_value =
1792                                     IGA2_VER_SYNC_END_FORMULA
1793                                     (device_timing.ver_sync_start,
1794                                      device_timing.ver_sync_end);
1795                                 viafb_load_reg_num =
1796                                     iga2_crtc_reg.ver_sync_end.reg_num;
1797                                 reg = iga2_crtc_reg.ver_sync_end.reg;
1798                                 break;
1799
1800                         }
1801                 }
1802                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1803         }
1804
1805         viafb_lock_crt();
1806 }
1807
1808 void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1809         struct VideoModeTable *video_mode, int bpp_byte, int set_iga)
1810 {
1811         struct display_timing crt_reg;
1812         int i;
1813         int index = 0;
1814         int h_addr, v_addr;
1815         u32 pll_D_N;
1816
1817         for (i = 0; i < video_mode->mode_array; i++) {
1818                 index = i;
1819
1820                 if (crt_table[i].refresh_rate == viaparinfo->
1821                         crt_setting_info->refresh_rate)
1822                         break;
1823         }
1824
1825         crt_reg = crt_table[index].crtc;
1826
1827         /* Mode 640x480 has border, but LCD/DFP didn't have border. */
1828         /* So we would delete border. */
1829         if ((viafb_LCD_ON | viafb_DVI_ON)
1830             && video_mode->crtc[0].crtc.hor_addr == 640
1831             && video_mode->crtc[0].crtc.ver_addr == 480
1832             && viaparinfo->crt_setting_info->refresh_rate == 60) {
1833                 /* The border is 8 pixels. */
1834                 crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8;
1835
1836                 /* Blanking time should add left and right borders. */
1837                 crt_reg.hor_blank_end = crt_reg.hor_blank_end + 16;
1838         }
1839
1840         h_addr = crt_reg.hor_addr;
1841         v_addr = crt_reg.ver_addr;
1842
1843         /* update polarity for CRT timing */
1844         if (crt_table[index].h_sync_polarity == NEGATIVE) {
1845                 if (crt_table[index].v_sync_polarity == NEGATIVE)
1846                         outb((inb(VIARMisc) & (~(BIT6 + BIT7))) |
1847                              (BIT6 + BIT7), VIAWMisc);
1848                 else
1849                         outb((inb(VIARMisc) & (~(BIT6 + BIT7))) | (BIT6),
1850                              VIAWMisc);
1851         } else {
1852                 if (crt_table[index].v_sync_polarity == NEGATIVE)
1853                         outb((inb(VIARMisc) & (~(BIT6 + BIT7))) | (BIT7),
1854                              VIAWMisc);
1855                 else
1856                         outb((inb(VIARMisc) & (~(BIT6 + BIT7))), VIAWMisc);
1857         }
1858
1859         if (set_iga == IGA1) {
1860                 viafb_unlock_crt();
1861                 viafb_write_reg(CR09, VIACR, 0x00);     /*initial CR09=0 */
1862                 viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6);
1863                 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1864         }
1865
1866         switch (set_iga) {
1867         case IGA1:
1868                 viafb_load_crtc_timing(crt_reg, IGA1);
1869                 break;
1870         case IGA2:
1871                 viafb_load_crtc_timing(crt_reg, IGA2);
1872                 break;
1873         }
1874
1875         load_fix_bit_crtc_reg();
1876         viafb_lock_crt();
1877         viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1878         viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga);
1879
1880         /* load FIFO */
1881         if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
1882             && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
1883                 viafb_load_FIFO_reg(set_iga, h_addr, v_addr);
1884
1885         pll_D_N = viafb_get_clk_value(crt_table[index].clk);
1886         DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);
1887         viafb_set_vclock(pll_D_N, set_iga);
1888
1889 }
1890
1891 void viafb_init_chip_info(int chip_type)
1892 {
1893         init_gfx_chip_info(chip_type);
1894         init_tmds_chip_info();
1895         init_lvds_chip_info();
1896
1897         viaparinfo->crt_setting_info->iga_path = IGA1;
1898         viaparinfo->crt_setting_info->refresh_rate = viafb_refresh;
1899
1900         /*Set IGA path for each device */
1901         viafb_set_iga_path();
1902
1903         viaparinfo->lvds_setting_info->display_method = viafb_lcd_dsp_method;
1904         viaparinfo->lvds_setting_info->get_lcd_size_method =
1905                 GET_LCD_SIZE_BY_USER_SETTING;
1906         viaparinfo->lvds_setting_info->lcd_mode = viafb_lcd_mode;
1907         viaparinfo->lvds_setting_info2->display_method =
1908                 viaparinfo->lvds_setting_info->display_method;
1909         viaparinfo->lvds_setting_info2->lcd_mode =
1910                 viaparinfo->lvds_setting_info->lcd_mode;
1911 }
1912
1913 void viafb_update_device_setting(int hres, int vres,
1914         int bpp, int vmode_refresh, int flag)
1915 {
1916         if (flag == 0) {
1917                 viaparinfo->crt_setting_info->h_active = hres;
1918                 viaparinfo->crt_setting_info->v_active = vres;
1919                 viaparinfo->crt_setting_info->bpp = bpp;
1920                 viaparinfo->crt_setting_info->refresh_rate =
1921                         vmode_refresh;
1922
1923                 viaparinfo->tmds_setting_info->h_active = hres;
1924                 viaparinfo->tmds_setting_info->v_active = vres;
1925
1926                 viaparinfo->lvds_setting_info->h_active = hres;
1927                 viaparinfo->lvds_setting_info->v_active = vres;
1928                 viaparinfo->lvds_setting_info->bpp = bpp;
1929                 viaparinfo->lvds_setting_info->refresh_rate =
1930                         vmode_refresh;
1931                 viaparinfo->lvds_setting_info2->h_active = hres;
1932                 viaparinfo->lvds_setting_info2->v_active = vres;
1933                 viaparinfo->lvds_setting_info2->bpp = bpp;
1934                 viaparinfo->lvds_setting_info2->refresh_rate =
1935                         vmode_refresh;
1936         } else {
1937
1938                 if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
1939                         viaparinfo->tmds_setting_info->h_active = hres;
1940                         viaparinfo->tmds_setting_info->v_active = vres;
1941                 }
1942
1943                 if (viaparinfo->lvds_setting_info->iga_path == IGA2) {
1944                         viaparinfo->lvds_setting_info->h_active = hres;
1945                         viaparinfo->lvds_setting_info->v_active = vres;
1946                         viaparinfo->lvds_setting_info->bpp = bpp;
1947                         viaparinfo->lvds_setting_info->refresh_rate =
1948                                 vmode_refresh;
1949                 }
1950                 if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) {
1951                         viaparinfo->lvds_setting_info2->h_active = hres;
1952                         viaparinfo->lvds_setting_info2->v_active = vres;
1953                         viaparinfo->lvds_setting_info2->bpp = bpp;
1954                         viaparinfo->lvds_setting_info2->refresh_rate =
1955                                 vmode_refresh;
1956                 }
1957         }
1958 }
1959
1960 static void init_gfx_chip_info(int chip_type)
1961 {
1962         u8 tmp;
1963
1964         viaparinfo->chip_info->gfx_chip_name = chip_type;
1965
1966         /* Check revision of CLE266 Chip */
1967         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
1968                 /* CR4F only define in CLE266.CX chip */
1969                 tmp = viafb_read_reg(VIACR, CR4F);
1970                 viafb_write_reg(CR4F, VIACR, 0x55);
1971                 if (viafb_read_reg(VIACR, CR4F) != 0x55)
1972                         viaparinfo->chip_info->gfx_chip_revision =
1973                         CLE266_REVISION_AX;
1974                 else
1975                         viaparinfo->chip_info->gfx_chip_revision =
1976                         CLE266_REVISION_CX;
1977                 /* restore orignal CR4F value */
1978                 viafb_write_reg(CR4F, VIACR, tmp);
1979         }
1980
1981         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1982                 tmp = viafb_read_reg(VIASR, SR43);
1983                 DEBUG_MSG(KERN_INFO "SR43:%X\n", tmp);
1984                 if (tmp & 0x02) {
1985                         viaparinfo->chip_info->gfx_chip_revision =
1986                                 CX700_REVISION_700M2;
1987                 } else if (tmp & 0x40) {
1988                         viaparinfo->chip_info->gfx_chip_revision =
1989                                 CX700_REVISION_700M;
1990                 } else {
1991                         viaparinfo->chip_info->gfx_chip_revision =
1992                                 CX700_REVISION_700;
1993                 }
1994         }
1995
1996         /* Determine which 2D engine we have */
1997         switch (viaparinfo->chip_info->gfx_chip_name) {
1998         case UNICHROME_VX800:
1999         case UNICHROME_VX855:
2000                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_M1;
2001                 break;
2002         case UNICHROME_K8M890:
2003         case UNICHROME_P4M900:
2004                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H5;
2005                 break;
2006         default:
2007                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H2;
2008                 break;
2009         }
2010 }
2011
2012 static void init_tmds_chip_info(void)
2013 {
2014         viafb_tmds_trasmitter_identify();
2015
2016         if (INTERFACE_NONE == viaparinfo->chip_info->tmds_chip_info.
2017                 output_interface) {
2018                 switch (viaparinfo->chip_info->gfx_chip_name) {
2019                 case UNICHROME_CX700:
2020                         {
2021                                 /* we should check support by hardware layout.*/
2022                                 if ((viafb_display_hardware_layout ==
2023                                      HW_LAYOUT_DVI_ONLY)
2024                                     || (viafb_display_hardware_layout ==
2025                                         HW_LAYOUT_LCD_DVI)) {
2026                                         viaparinfo->chip_info->tmds_chip_info.
2027                                             output_interface = INTERFACE_TMDS;
2028                                 } else {
2029                                         viaparinfo->chip_info->tmds_chip_info.
2030                                                 output_interface =
2031                                                 INTERFACE_NONE;
2032                                 }
2033                                 break;
2034                         }
2035                 case UNICHROME_K8M890:
2036                 case UNICHROME_P4M900:
2037                 case UNICHROME_P4M890:
2038                         /* TMDS on PCIE, we set DFPLOW as default. */
2039                         viaparinfo->chip_info->tmds_chip_info.output_interface =
2040                             INTERFACE_DFP_LOW;
2041                         break;
2042                 default:
2043                         {
2044                                 /* set DVP1 default for DVI */
2045                                 viaparinfo->chip_info->tmds_chip_info
2046                                 .output_interface = INTERFACE_DVP1;
2047                         }
2048                 }
2049         }
2050
2051         DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n",
2052                   viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
2053         viafb_init_dvi_size(&viaparinfo->shared->chip_info.tmds_chip_info,
2054                 &viaparinfo->shared->tmds_setting_info);
2055 }
2056
2057 static void init_lvds_chip_info(void)
2058 {
2059         if (viafb_lcd_panel_id > LCD_PANEL_ID_MAXIMUM)
2060                 viaparinfo->lvds_setting_info->get_lcd_size_method =
2061                     GET_LCD_SIZE_BY_VGA_BIOS;
2062         else
2063                 viaparinfo->lvds_setting_info->get_lcd_size_method =
2064                     GET_LCD_SIZE_BY_USER_SETTING;
2065
2066         viafb_lvds_trasmitter_identify();
2067         viafb_init_lcd_size();
2068         viafb_init_lvds_output_interface(&viaparinfo->chip_info->lvds_chip_info,
2069                                    viaparinfo->lvds_setting_info);
2070         if (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) {
2071                 viafb_init_lvds_output_interface(&viaparinfo->chip_info->
2072                         lvds_chip_info2, viaparinfo->lvds_setting_info2);
2073         }
2074         /*If CX700,two singel LCD, we need to reassign
2075            LCD interface to different LVDS port */
2076         if ((UNICHROME_CX700 == viaparinfo->chip_info->gfx_chip_name)
2077             && (HW_LAYOUT_LCD1_LCD2 == viafb_display_hardware_layout)) {
2078                 if ((INTEGRATED_LVDS == viaparinfo->chip_info->lvds_chip_info.
2079                         lvds_chip_name) && (INTEGRATED_LVDS ==
2080                         viaparinfo->chip_info->
2081                         lvds_chip_info2.lvds_chip_name)) {
2082                         viaparinfo->chip_info->lvds_chip_info.output_interface =
2083                                 INTERFACE_LVDS0;
2084                         viaparinfo->chip_info->lvds_chip_info2.
2085                                 output_interface =
2086                             INTERFACE_LVDS1;
2087                 }
2088         }
2089
2090         DEBUG_MSG(KERN_INFO "LVDS Chip = %d\n",
2091                   viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
2092         DEBUG_MSG(KERN_INFO "LVDS1 output_interface = %d\n",
2093                   viaparinfo->chip_info->lvds_chip_info.output_interface);
2094         DEBUG_MSG(KERN_INFO "LVDS2 output_interface = %d\n",
2095                   viaparinfo->chip_info->lvds_chip_info.output_interface);
2096 }
2097
2098 void viafb_init_dac(int set_iga)
2099 {
2100         int i;
2101         u8 tmp;
2102
2103         if (set_iga == IGA1) {
2104                 /* access Primary Display's LUT */
2105                 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2106                 /* turn off LCK */
2107                 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);
2108                 for (i = 0; i < 256; i++) {
2109                         write_dac_reg(i, palLUT_table[i].red,
2110                                       palLUT_table[i].green,
2111                                       palLUT_table[i].blue);
2112                 }
2113                 /* turn on LCK */
2114                 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);
2115         } else {
2116                 tmp = viafb_read_reg(VIACR, CR6A);
2117                 /* access Secondary Display's LUT */
2118                 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);
2119                 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
2120                 for (i = 0; i < 256; i++) {
2121                         write_dac_reg(i, palLUT_table[i].red,
2122                                       palLUT_table[i].green,
2123                                       palLUT_table[i].blue);
2124                 }
2125                 /* set IGA1 DAC for default */
2126                 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2127                 viafb_write_reg(CR6A, VIACR, tmp);
2128         }
2129 }
2130
2131 static void device_screen_off(void)
2132 {
2133         /* turn off CRT screen (IGA1) */
2134         viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);
2135 }
2136
2137 static void device_screen_on(void)
2138 {
2139         /* turn on CRT screen (IGA1) */
2140         viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);
2141 }
2142
2143 static void set_display_channel(void)
2144 {
2145         /*If viafb_LCD2_ON, on cx700, internal lvds's information
2146         is keeped on lvds_setting_info2 */
2147         if (viafb_LCD2_ON &&
2148                 viaparinfo->lvds_setting_info2->device_lcd_dualedge) {
2149                 /* For dual channel LCD: */
2150                 /* Set to Dual LVDS channel. */
2151                 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2152         } else if (viafb_LCD_ON && viafb_DVI_ON) {
2153                 /* For LCD+DFP: */
2154                 /* Set to LVDS1 + TMDS channel. */
2155                 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);
2156         } else if (viafb_DVI_ON) {
2157                 /* Set to single TMDS channel. */
2158                 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);
2159         } else if (viafb_LCD_ON) {
2160                 if (viaparinfo->lvds_setting_info->device_lcd_dualedge) {
2161                         /* For dual channel LCD: */
2162                         /* Set to Dual LVDS channel. */
2163                         viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2164                 } else {
2165                         /* Set to LVDS0 + LVDS1 channel. */
2166                         viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);
2167                 }
2168         }
2169 }
2170
2171 int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2172         struct VideoModeTable *vmode_tbl1, int video_bpp1)
2173 {
2174         int i, j;
2175         int port;
2176         u8 value, index, mask;
2177         struct crt_mode_table *crt_timing;
2178         struct crt_mode_table *crt_timing1 = NULL;
2179
2180         device_screen_off();
2181         crt_timing = vmode_tbl->crtc;
2182
2183         if (viafb_SAMM_ON == 1) {
2184                 crt_timing1 = vmode_tbl1->crtc;
2185         }
2186
2187         inb(VIAStatus);
2188         outb(0x00, VIAAR);
2189
2190         /* Write Common Setting for Video Mode */
2191         switch (viaparinfo->chip_info->gfx_chip_name) {
2192         case UNICHROME_CLE266:
2193                 viafb_write_regx(CLE266_ModeXregs, NUM_TOTAL_CLE266_ModeXregs);
2194                 break;
2195
2196         case UNICHROME_K400:
2197                 viafb_write_regx(KM400_ModeXregs, NUM_TOTAL_KM400_ModeXregs);
2198                 break;
2199
2200         case UNICHROME_K800:
2201         case UNICHROME_PM800:
2202                 viafb_write_regx(CN400_ModeXregs, NUM_TOTAL_CN400_ModeXregs);
2203                 break;
2204
2205         case UNICHROME_CN700:
2206         case UNICHROME_K8M890:
2207         case UNICHROME_P4M890:
2208         case UNICHROME_P4M900:
2209                 viafb_write_regx(CN700_ModeXregs, NUM_TOTAL_CN700_ModeXregs);
2210                 break;
2211
2212         case UNICHROME_CX700:
2213         case UNICHROME_VX800:
2214                 viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs);
2215                 break;
2216
2217         case UNICHROME_VX855:
2218                 viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs);
2219                 break;
2220         }
2221
2222         device_off();
2223
2224         /* Fill VPIT Parameters */
2225         /* Write Misc Register */
2226         outb(VPIT.Misc, VIAWMisc);
2227
2228         /* Write Sequencer */
2229         for (i = 1; i <= StdSR; i++) {
2230                 outb(i, VIASR);
2231                 outb(VPIT.SR[i - 1], VIASR + 1);
2232         }
2233
2234         viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2);
2235         viafb_set_iga_path();
2236
2237         /* Write CRTC */
2238         viafb_fill_crtc_timing(crt_timing, vmode_tbl, video_bpp / 8, IGA1);
2239
2240         /* Write Graphic Controller */
2241         for (i = 0; i < StdGR; i++) {
2242                 outb(i, VIAGR);
2243                 outb(VPIT.GR[i], VIAGR + 1);
2244         }
2245
2246         /* Write Attribute Controller */
2247         for (i = 0; i < StdAR; i++) {
2248                 inb(VIAStatus);
2249                 outb(i, VIAAR);
2250                 outb(VPIT.AR[i], VIAAR);
2251         }
2252
2253         inb(VIAStatus);
2254         outb(0x20, VIAAR);
2255
2256         /* Update Patch Register */
2257
2258         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266
2259             || viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400)
2260             && vmode_tbl->crtc[0].crtc.hor_addr == 1024
2261             && vmode_tbl->crtc[0].crtc.ver_addr == 768) {
2262                 for (j = 0; j < res_patch_table[0].table_length; j++) {
2263                         index = res_patch_table[0].io_reg_table[j].index;
2264                         port = res_patch_table[0].io_reg_table[j].port;
2265                         value = res_patch_table[0].io_reg_table[j].value;
2266                         mask = res_patch_table[0].io_reg_table[j].mask;
2267                         viafb_write_reg_mask(index, port, value, mask);
2268                 }
2269         }
2270
2271         via_set_primary_pitch(viafbinfo->fix.line_length);
2272         via_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length
2273                 : viafbinfo->fix.line_length);
2274         via_set_primary_color_depth(viaparinfo->depth);
2275         via_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth
2276                 : viaparinfo->depth);
2277         /* Update Refresh Rate Setting */
2278
2279         /* Clear On Screen */
2280
2281         /* CRT set mode */
2282         if (viafb_CRT_ON) {
2283                 if (viafb_SAMM_ON && (viaparinfo->crt_setting_info->iga_path ==
2284                         IGA2)) {
2285                         viafb_fill_crtc_timing(crt_timing1, vmode_tbl1,
2286                                 video_bpp1 / 8,
2287                                 viaparinfo->crt_setting_info->iga_path);
2288                 } else {
2289                         viafb_fill_crtc_timing(crt_timing, vmode_tbl,
2290                                 video_bpp / 8,
2291                                 viaparinfo->crt_setting_info->iga_path);
2292                 }
2293
2294                 set_crt_output_path(viaparinfo->crt_setting_info->iga_path);
2295
2296                 /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode
2297                 to 8 alignment (1368),there is several pixels (2 pixels)
2298                 on right side of screen. */
2299                 if (vmode_tbl->crtc[0].crtc.hor_addr % 8) {
2300                         viafb_unlock_crt();
2301                         viafb_write_reg(CR02, VIACR,
2302                                 viafb_read_reg(VIACR, CR02) - 1);
2303                         viafb_lock_crt();
2304                 }
2305         }
2306
2307         if (viafb_DVI_ON) {
2308                 if (viafb_SAMM_ON &&
2309                         (viaparinfo->tmds_setting_info->iga_path == IGA2)) {
2310                         viafb_dvi_set_mode(viafb_get_mode
2311                                      (viaparinfo->tmds_setting_info->h_active,
2312                                       viaparinfo->tmds_setting_info->
2313                                       v_active),
2314                                      video_bpp1, viaparinfo->
2315                                      tmds_setting_info->iga_path);
2316                 } else {
2317                         viafb_dvi_set_mode(viafb_get_mode
2318                                      (viaparinfo->tmds_setting_info->h_active,
2319                                       viaparinfo->
2320                                       tmds_setting_info->v_active),
2321                                      video_bpp, viaparinfo->
2322                                      tmds_setting_info->iga_path);
2323                 }
2324         }
2325
2326         if (viafb_LCD_ON) {
2327                 if (viafb_SAMM_ON &&
2328                         (viaparinfo->lvds_setting_info->iga_path == IGA2)) {
2329                         viaparinfo->lvds_setting_info->bpp = video_bpp1;
2330                         viafb_lcd_set_mode(crt_timing1, viaparinfo->
2331                                 lvds_setting_info,
2332                                      &viaparinfo->chip_info->lvds_chip_info);
2333                 } else {
2334                         /* IGA1 doesn't have LCD scaling, so set it center. */
2335                         if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
2336                                 viaparinfo->lvds_setting_info->display_method =
2337                                     LCD_CENTERING;
2338                         }
2339                         viaparinfo->lvds_setting_info->bpp = video_bpp;
2340                         viafb_lcd_set_mode(crt_timing, viaparinfo->
2341                                 lvds_setting_info,
2342                                      &viaparinfo->chip_info->lvds_chip_info);
2343                 }
2344         }
2345         if (viafb_LCD2_ON) {
2346                 if (viafb_SAMM_ON &&
2347                         (viaparinfo->lvds_setting_info2->iga_path == IGA2)) {
2348                         viaparinfo->lvds_setting_info2->bpp = video_bpp1;
2349                         viafb_lcd_set_mode(crt_timing1, viaparinfo->
2350                                 lvds_setting_info2,
2351                                      &viaparinfo->chip_info->lvds_chip_info2);
2352                 } else {
2353                         /* IGA1 doesn't have LCD scaling, so set it center. */
2354                         if (viaparinfo->lvds_setting_info2->iga_path == IGA1) {
2355                                 viaparinfo->lvds_setting_info2->display_method =
2356                                     LCD_CENTERING;
2357                         }
2358                         viaparinfo->lvds_setting_info2->bpp = video_bpp;
2359                         viafb_lcd_set_mode(crt_timing, viaparinfo->
2360                                 lvds_setting_info2,
2361                                      &viaparinfo->chip_info->lvds_chip_info2);
2362                 }
2363         }
2364
2365         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
2366             && (viafb_LCD_ON || viafb_DVI_ON))
2367                 set_display_channel();
2368
2369         /* If set mode normally, save resolution information for hot-plug . */
2370         if (!viafb_hotplug) {
2371                 viafb_hotplug_Xres = vmode_tbl->crtc[0].crtc.hor_addr;
2372                 viafb_hotplug_Yres = vmode_tbl->crtc[0].crtc.ver_addr;
2373                 viafb_hotplug_bpp = video_bpp;
2374                 viafb_hotplug_refresh = viafb_refresh;
2375
2376                 if (viafb_DVI_ON)
2377                         viafb_DeviceStatus = DVI_Device;
2378                 else
2379                         viafb_DeviceStatus = CRT_Device;
2380         }
2381         device_on();
2382
2383         if (viafb_SAMM_ON == 1)
2384                 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
2385
2386         device_screen_on();
2387         return 1;
2388 }
2389
2390 int viafb_get_pixclock(int hres, int vres, int vmode_refresh)
2391 {
2392         int i;
2393
2394         for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2395                 if ((hres == res_map_refresh_tbl[i].hres)
2396                     && (vres == res_map_refresh_tbl[i].vres)
2397                     && (vmode_refresh == res_map_refresh_tbl[i].vmode_refresh))
2398                         return res_map_refresh_tbl[i].pixclock;
2399         }
2400         return RES_640X480_60HZ_PIXCLOCK;
2401
2402 }
2403
2404 int viafb_get_refresh(int hres, int vres, u32 long_refresh)
2405 {
2406 #define REFRESH_TOLERANCE 3
2407         int i, nearest = -1, diff = REFRESH_TOLERANCE;
2408         for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2409                 if ((hres == res_map_refresh_tbl[i].hres)
2410                     && (vres == res_map_refresh_tbl[i].vres)
2411                     && (diff > (abs(long_refresh -
2412                     res_map_refresh_tbl[i].vmode_refresh)))) {
2413                         diff = abs(long_refresh - res_map_refresh_tbl[i].
2414                                 vmode_refresh);
2415                         nearest = i;
2416                 }
2417         }
2418 #undef REFRESH_TOLERANCE
2419         if (nearest > 0)
2420                 return res_map_refresh_tbl[nearest].vmode_refresh;
2421         return 60;
2422 }
2423
2424 static void device_off(void)
2425 {
2426         viafb_crt_disable();
2427         viafb_dvi_disable();
2428         viafb_lcd_disable();
2429 }
2430
2431 static void device_on(void)
2432 {
2433         if (viafb_CRT_ON == 1)
2434                 viafb_crt_enable();
2435         if (viafb_DVI_ON == 1)
2436                 viafb_dvi_enable();
2437         if (viafb_LCD_ON == 1)
2438                 viafb_lcd_enable();
2439 }
2440
2441 void viafb_crt_disable(void)
2442 {
2443         viafb_write_reg_mask(CR36, VIACR, BIT5 + BIT4, BIT5 + BIT4);
2444 }
2445
2446 void viafb_crt_enable(void)
2447 {
2448         viafb_write_reg_mask(CR36, VIACR, 0x0, BIT5 + BIT4);
2449 }
2450
2451 static void enable_second_display_channel(void)
2452 {
2453         /* to enable second display channel. */
2454         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2455         viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);
2456         viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2457 }
2458
2459 static void disable_second_display_channel(void)
2460 {
2461         /* to disable second display channel. */
2462         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2463         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7);
2464         viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2465 }
2466
2467
2468 void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
2469                                         *p_gfx_dpa_setting)
2470 {
2471         switch (output_interface) {
2472         case INTERFACE_DVP0:
2473                 {
2474                         /* DVP0 Clock Polarity and Adjust: */
2475                         viafb_write_reg_mask(CR96, VIACR,
2476                                        p_gfx_dpa_setting->DVP0, 0x0F);
2477
2478                         /* DVP0 Clock and Data Pads Driving: */
2479                         viafb_write_reg_mask(SR1E, VIASR,
2480                                        p_gfx_dpa_setting->DVP0ClockDri_S, BIT2);
2481                         viafb_write_reg_mask(SR2A, VIASR,
2482                                        p_gfx_dpa_setting->DVP0ClockDri_S1,
2483                                        BIT4);
2484                         viafb_write_reg_mask(SR1B, VIASR,
2485                                        p_gfx_dpa_setting->DVP0DataDri_S, BIT1);
2486                         viafb_write_reg_mask(SR2A, VIASR,
2487                                        p_gfx_dpa_setting->DVP0DataDri_S1, BIT5);
2488                         break;
2489                 }
2490
2491         case INTERFACE_DVP1:
2492                 {
2493                         /* DVP1 Clock Polarity and Adjust: */
2494                         viafb_write_reg_mask(CR9B, VIACR,
2495                                        p_gfx_dpa_setting->DVP1, 0x0F);
2496
2497                         /* DVP1 Clock and Data Pads Driving: */
2498                         viafb_write_reg_mask(SR65, VIASR,
2499                                        p_gfx_dpa_setting->DVP1Driving, 0x0F);
2500                         break;
2501                 }
2502
2503         case INTERFACE_DFP_HIGH:
2504                 {
2505                         viafb_write_reg_mask(CR97, VIACR,
2506                                        p_gfx_dpa_setting->DFPHigh, 0x0F);
2507                         break;
2508                 }
2509
2510         case INTERFACE_DFP_LOW:
2511                 {
2512                         viafb_write_reg_mask(CR99, VIACR,
2513                                        p_gfx_dpa_setting->DFPLow, 0x0F);
2514                         break;
2515                 }
2516
2517         case INTERFACE_DFP:
2518                 {
2519                         viafb_write_reg_mask(CR97, VIACR,
2520                                        p_gfx_dpa_setting->DFPHigh, 0x0F);
2521                         viafb_write_reg_mask(CR99, VIACR,
2522                                        p_gfx_dpa_setting->DFPLow, 0x0F);
2523                         break;
2524                 }
2525         }
2526 }
2527
2528 /*According var's xres, yres fill var's other timing information*/
2529 void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
2530         struct VideoModeTable *vmode_tbl)
2531 {
2532         struct crt_mode_table *crt_timing = NULL;
2533         struct display_timing crt_reg;
2534         int i = 0, index = 0;
2535         crt_timing = vmode_tbl->crtc;
2536         for (i = 0; i < vmode_tbl->mode_array; i++) {
2537                 index = i;
2538                 if (crt_timing[i].refresh_rate == refresh)
2539                         break;
2540         }
2541
2542         crt_reg = crt_timing[index].crtc;
2543         var->pixclock = viafb_get_pixclock(var->xres, var->yres, refresh);
2544         var->left_margin =
2545             crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end);
2546         var->right_margin = crt_reg.hor_sync_start - crt_reg.hor_addr;
2547         var->hsync_len = crt_reg.hor_sync_end;
2548         var->upper_margin =
2549             crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end);
2550         var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr;
2551         var->vsync_len = crt_reg.ver_sync_end;
2552 }