drivers/video/via/hw.c

   1 /*
   2  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
   3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
   4
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public
   7  * License as published by the Free Software Foundation;
   8  * either version 2, or (at your option) any later version.
   9
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
  12  * the implied warranty of MERCHANTABILITY or FITNESS FOR
  13  * A PARTICULAR PURPOSE.See the GNU General Public License
  14  * for more details.
  15
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc.,
  19  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20  */
  21
  22 #include <linux/via-core.h>
  23 #include "global.h"
  24
  25 static struct pll_map pll_value[] = {
  26         {25175000,
  27                 {99, 7, 3},
  28                 {85, 3, 4},     /* ignoring bit difference: 0x00008000 */
  29                 {141, 5, 4},
  30                 {141, 5, 4} },
  31         {29581000,
  32                 {33, 4, 2},
  33                 {66, 2, 4},     /* ignoring bit difference: 0x00808000 */
  34                 {166, 5, 4},    /* ignoring bit difference: 0x00008000 */
  35                 {165, 5, 4} },
  36         {26880000,
  37                 {15, 4, 1},
  38                 {30, 2, 3},     /* ignoring bit difference: 0x00808000 */
  39                 {150, 5, 4},
  40                 {150, 5, 4} },
  41         {31500000,
  42                 {53, 3, 3},     /* ignoring bit difference: 0x00008000 */
  43                 {141, 4, 4},    /* ignoring bit difference: 0x00008000 */
  44                 {176, 5, 4},
  45                 {176, 5, 4} },
  46         {31728000,
  47                 {31, 7, 1},
  48                 {177, 5, 4},    /* ignoring bit difference: 0x00008000 */
  49                 {177, 5, 4},
  50                 {142, 4, 4} },
  51         {32688000,
  52                 {73, 4, 3},
  53                 {146, 4, 4},    /* ignoring bit difference: 0x00008000 */
  54                 {183, 5, 4},
  55                 {146, 4, 4} },
  56         {36000000,
  57                 {101, 5, 3},    /* ignoring bit difference: 0x00008000 */
  58                 {161, 4, 4},    /* ignoring bit difference: 0x00008000 */
  59                 {202, 5, 4},
  60                 {161, 4, 4} },
  61         {40000000,
  62                 {89, 4, 3},
  63                 {89, 4, 3},     /* ignoring bit difference: 0x00008000 */
  64                 {112, 5, 3},
  65                 {112, 5, 3} },
  66         {41291000,
  67                 {23, 4, 1},
  68                 {69, 3, 3},     /* ignoring bit difference: 0x00008000 */
  69                 {115, 5, 3},
  70                 {115, 5, 3} },
  71         {43163000,
  72                 {121, 5, 3},
  73                 {121, 5, 3},    /* ignoring bit difference: 0x00008000 */
  74                 {121, 5, 3},
  75                 {121, 5, 3} },
  76         {45250000,
  77                 {127, 5, 3},
  78                 {127, 5, 3},    /* ignoring bit difference: 0x00808000 */
  79                 {127, 5, 3},
  80                 {127, 5, 3} },
  81         {46000000,
  82                 {90, 7, 2},
  83                 {103, 4, 3},    /* ignoring bit difference: 0x00008000 */
  84                 {129, 5, 3},
  85                 {103, 4, 3} },
  86         {46996000,
  87                 {105, 4, 3},    /* ignoring bit difference: 0x00008000 */
  88                 {131, 5, 3},    /* ignoring bit difference: 0x00808000 */
  89                 {131, 5, 3},    /* ignoring bit difference: 0x00808000 */
  90                 {105, 4, 3} },
  91         {48000000,
  92                 {67, 20, 0},
  93                 {134, 5, 3},    /* ignoring bit difference: 0x00808000 */
  94                 {134, 5, 3},
  95                 {134, 5, 3} },
  96         {48875000,
  97                 {99, 29, 0},
  98                 {82, 3, 3},     /* ignoring bit difference: 0x00808000 */
  99                 {82, 3, 3},     /* ignoring bit difference: 0x00808000 */
 100                 {137, 5, 3} },
 101         {49500000,
 102                 {83, 6, 2},
 103                 {83, 3, 3},     /* ignoring bit difference: 0x00008000 */
 104                 {138, 5, 3},
 105                 {83, 3, 3} },
 106         {52406000,
 107                 {117, 4, 3},
 108                 {117, 4, 3},    /* ignoring bit difference: 0x00008000 */
 109                 {117, 4, 3},
 110                 {88, 3, 3} },
 111         {52977000,
 112                 {37, 5, 1},
 113                 {148, 5, 3},    /* ignoring bit difference: 0x00808000 */
 114                 {148, 5, 3},
 115                 {148, 5, 3} },
 116         {56250000,
 117                 {55, 7, 1},     /* ignoring bit difference: 0x00008000 */
 118                 {126, 4, 3},    /* ignoring bit difference: 0x00008000 */
 119                 {157, 5, 3},
 120                 {157, 5, 3} },
 121         {57275000,
 122                 {0, 0, 0},
 123                 {2, 2, 0},
 124                 {2, 2, 0},
 125                 {157, 5, 3} },  /* ignoring bit difference: 0x00808000 */
 126         {60466000,
 127                 {76, 9, 1},
 128                 {169, 5, 3},    /* ignoring bit difference: 0x00808000 */
 129                 {169, 5, 3},    /* FIXED: old = {72, 2, 3} */
 130                 {169, 5, 3} },
 131         {61500000,
 132                 {86, 20, 0},
 133                 {172, 5, 3},    /* ignoring bit difference: 0x00808000 */
 134                 {172, 5, 3},
 135                 {172, 5, 3} },
 136         {65000000,
 137                 {109, 6, 2},    /* ignoring bit difference: 0x00008000 */
 138                 {109, 3, 3},    /* ignoring bit difference: 0x00008000 */
 139                 {109, 3, 3},
 140                 {109, 3, 3} },
 141         {65178000,
 142                 {91, 5, 2},
 143                 {182, 5, 3},    /* ignoring bit difference: 0x00808000 */
 144                 {109, 3, 3},
 145                 {182, 5, 3} },
 146         {66750000,
 147                 {75, 4, 2},
 148                 {150, 4, 3},    /* ignoring bit difference: 0x00808000 */
 149                 {150, 4, 3},
 150                 {112, 3, 3} },
 151         {68179000,
 152                 {19, 4, 0},
 153                 {114, 3, 3},    /* ignoring bit difference: 0x00008000 */
 154                 {190, 5, 3},
 155                 {191, 5, 3} },
 156         {69924000,
 157                 {83, 17, 0},
 158                 {195, 5, 3},    /* ignoring bit difference: 0x00808000 */
 159                 {195, 5, 3},
 160                 {195, 5, 3} },
 161         {70159000,
 162                 {98, 20, 0},
 163                 {196, 5, 3},    /* ignoring bit difference: 0x00808000 */
 164                 {196, 5, 3},
 165                 {195, 5, 3} },
 166         {72000000,
 167                 {121, 24, 0},
 168                 {161, 4, 3},    /* ignoring bit difference: 0x00808000 */
 169                 {161, 4, 3},
 170                 {161, 4, 3} },
 171         {78750000,
 172                 {33, 3, 1},
 173                 {66, 3, 2},     /* ignoring bit difference: 0x00008000 */
 174                 {110, 5, 2},
 175                 {110, 5, 2} },
 176         {80136000,
 177                 {28, 5, 0},
 178                 {68, 3, 2},     /* ignoring bit difference: 0x00008000 */
 179                 {112, 5, 2},
 180                 {112, 5, 2} },
 181         {83375000,
 182                 {93, 2, 3},
 183                 {93, 4, 2},     /* ignoring bit difference: 0x00800000 */
 184                 {93, 4, 2},     /* ignoring bit difference: 0x00800000 */
 185                 {117, 5, 2} },
 186         {83950000,
 187                 {41, 7, 0},
 188                 {117, 5, 2},    /* ignoring bit difference: 0x00008000 */
 189                 {117, 5, 2},
 190                 {117, 5, 2} },
 191         {84750000,
 192                 {118, 5, 2},
 193                 {118, 5, 2},    /* ignoring bit difference: 0x00808000 */
 194                 {118, 5, 2},
 195                 {118, 5, 2} },
 196         {85860000,
 197                 {84, 7, 1},
 198                 {120, 5, 2},    /* ignoring bit difference: 0x00808000 */
 199                 {120, 5, 2},
 200                 {118, 5, 2} },
 201         {88750000,
 202                 {31, 5, 0},
 203                 {124, 5, 2},    /* ignoring bit difference: 0x00808000 */
 204                 {174, 7, 2},    /* ignoring bit difference: 0x00808000 */
 205                 {124, 5, 2} },
 206         {94500000,
 207                 {33, 5, 0},
 208                 {132, 5, 2},    /* ignoring bit difference: 0x00008000 */
 209                 {132, 5, 2},
 210                 {132, 5, 2} },
 211         {97750000,
 212                 {82, 6, 1},
 213                 {137, 5, 2},    /* ignoring bit difference: 0x00808000 */
 214                 {137, 5, 2},
 215                 {137, 5, 2} },
 216         {101000000,
 217                 {127, 9, 1},
 218                 {141, 5, 2},    /* ignoring bit difference: 0x00808000 */
 219                 {141, 5, 2},
 220                 {141, 5, 2} },
 221         {106500000,
 222                 {119, 4, 2},
 223                 {119, 4, 2},    /* ignoring bit difference: 0x00808000 */
 224                 {119, 4, 2},
 225                 {149, 5, 2} },
 226         {108000000,
 227                 {121, 4, 2},
 228                 {121, 4, 2},    /* ignoring bit difference: 0x00808000 */
 229                 {151, 5, 2},
 230                 {151, 5, 2} },
 231         {113309000,
 232                 {95, 12, 0},
 233                 {95, 3, 2},     /* ignoring bit difference: 0x00808000 */
 234                 {95, 3, 2},
 235                 {159, 5, 2} },
 236         {118840000,
 237                 {83, 5, 1},
 238                 {166, 5, 2},    /* ignoring bit difference: 0x00808000 */
 239                 {166, 5, 2},
 240                 {166, 5, 2} },
 241         {119000000,
 242                 {108, 13, 0},
 243                 {133, 4, 2},    /* ignoring bit difference: 0x00808000 */
 244                 {133, 4, 2},
 245                 {167, 5, 2} },
 246         {121750000,
 247                 {85, 5, 1},
 248                 {170, 5, 2},    /* ignoring bit difference: 0x00808000 */
 249                 {68, 2, 2},
 250                 {0, 0, 0} },
 251         {125104000,
 252                 {53, 6, 0},     /* ignoring bit difference: 0x00008000 */
 253                 {106, 3, 2},    /* ignoring bit difference: 0x00008000 */
 254                 {175, 5, 2},
 255                 {0, 0, 0} },
 256         {135000000,
 257                 {94, 5, 1},
 258                 {28, 3, 0},     /* ignoring bit difference: 0x00804000 */
 259                 {151, 4, 2},
 260                 {189, 5, 2} },
 261         {136700000,
 262                 {115, 12, 0},
 263                 {191, 5, 2},    /* ignoring bit difference: 0x00808000 */
 264                 {191, 5, 2},
 265                 {191, 5, 2} },
 266         {138400000,
 267                 {87, 9, 0},
 268                 {116, 3, 2},    /* ignoring bit difference: 0x00808000 */
 269                 {116, 3, 2},
 270                 {194, 5, 2} },
 271         {146760000,
 272                 {103, 5, 1},
 273                 {206, 5, 2},    /* ignoring bit difference: 0x00808000 */
 274                 {206, 5, 2},
 275                 {206, 5, 2} },
 276         {153920000,
 277                 {86, 8, 0},
 278                 {86, 4, 1},     /* ignoring bit difference: 0x00808000 */
 279                 {86, 4, 1},
 280                 {86, 4, 1} },   /* FIXED: old = {84, 2, 1} */
 281         {156000000,
 282                 {109, 5, 1},
 283                 {109, 5, 1},    /* ignoring bit difference: 0x00808000 */
 284                 {109, 5, 1},
 285                 {108, 5, 1} },
 286         {157500000,
 287                 {55, 5, 0},     /* ignoring bit difference: 0x00008000 */
 288                 {22, 2, 0},     /* ignoring bit difference: 0x00802000 */
 289                 {110, 5, 1},
 290                 {110, 5, 1} },
 291         {162000000,
 292                 {113, 5, 1},
 293                 {113, 5, 1},    /* ignoring bit difference: 0x00808000 */
 294                 {113, 5, 1},
 295                 {113, 5, 1} },
 296         {187000000,
 297                 {118, 9, 0},
 298                 {131, 5, 1},    /* ignoring bit difference: 0x00808000 */
 299                 {131, 5, 1},
 300                 {131, 5, 1} },
 301         {193295000,
 302                 {108, 8, 0},
 303                 {81, 3, 1},     /* ignoring bit difference: 0x00808000 */
 304                 {135, 5, 1},
 305                 {135, 5, 1} },
 306         {202500000,
 307                 {99, 7, 0},
 308                 {85, 3, 1},     /* ignoring bit difference: 0x00808000 */
 309                 {142, 5, 1},
 310                 {142, 5, 1} },
 311         {204000000,
 312                 {100, 7, 0},
 313                 {143, 5, 1},    /* ignoring bit difference: 0x00808000 */
 314                 {143, 5, 1},
 315                 {143, 5, 1} },
 316         {218500000,
 317                 {92, 6, 0},
 318                 {153, 5, 1},    /* ignoring bit difference: 0x00808000 */
 319                 {153, 5, 1},
 320                 {153, 5, 1} },
 321         {234000000,
 322                 {98, 6, 0},
 323                 {98, 3, 1},     /* ignoring bit difference: 0x00008000 */
 324                 {98, 3, 1},
 325                 {164, 5, 1} },
 326         {267250000,
 327                 {112, 6, 0},
 328                 {112, 3, 1},    /* ignoring bit difference: 0x00808000 */
 329                 {187, 5, 1},
 330                 {187, 5, 1} },
 331         {297500000,
 332                 {102, 5, 0},    /* ignoring bit difference: 0x00008000 */
 333                 {166, 4, 1},    /* ignoring bit difference: 0x00008000 */
 334                 {208, 5, 1},
 335                 {208, 5, 1} },
 336         {74481000,
 337                 {26, 5, 0},
 338                 {125, 3, 3},    /* ignoring bit difference: 0x00808000 */
 339                 {208, 5, 3},
 340                 {209, 5, 3} },
 341         {172798000,
 342                 {121, 5, 1},
 343                 {121, 5, 1},    /* ignoring bit difference: 0x00808000 */
 344                 {121, 5, 1},
 345                 {121, 5, 1} },
 346         {122614000,
 347                 {60, 7, 0},
 348                 {137, 4, 2},    /* ignoring bit difference: 0x00808000 */
 349                 {137, 4, 2},
 350                 {172, 5, 2} },
 351         {74270000,
 352                 {83, 8, 1},
 353                 {208, 5, 3},
 354                 {208, 5, 3},
 355                 {0, 0, 0} },
 356         {148500000,
 357                 {83, 8, 0},
 358                 {208, 5, 2},
 359                 {166, 4, 2},
 360                 {208, 5, 2} }
 361 };
 362
 363 static struct fifo_depth_select display_fifo_depth_reg = {
 364         /* IGA1 FIFO Depth_Select */
 365         {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } },
 366         /* IGA2 FIFO Depth_Select */
 367         {IGA2_FIFO_DEPTH_SELECT_REG_NUM,
 368          {{CR68, 4, 7}, {CR94, 7, 7}, {CR95, 7, 7} } }
 369 };
 370
 371 static struct fifo_threshold_select fifo_threshold_select_reg = {
 372         /* IGA1 FIFO Threshold Select */
 373         {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } },
 374         /* IGA2 FIFO Threshold Select */
 375         {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68, 0, 3}, {CR95, 4, 6} } }
 376 };
 377
 378 static struct fifo_high_threshold_select fifo_high_threshold_select_reg = {
 379         /* IGA1 FIFO High Threshold Select */
 380         {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18, 0, 5}, {SR18, 7, 7} } },
 381         /* IGA2 FIFO High Threshold Select */
 382         {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92, 0, 3}, {CR95, 0, 2} } }
 383 };
 384
 385 static struct display_queue_expire_num display_queue_expire_num_reg = {
 386         /* IGA1 Display Queue Expire Num */
 387         {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22, 0, 4} } },
 388         /* IGA2 Display Queue Expire Num */
 389         {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94, 0, 6} } }
 390 };
 391
 392 /* Definition Fetch Count Registers*/
 393 static struct fetch_count fetch_count_reg = {
 394         /* IGA1 Fetch Count Register */
 395         {IGA1_FETCH_COUNT_REG_NUM, {{SR1C, 0, 7}, {SR1D, 0, 1} } },
 396         /* IGA2 Fetch Count Register */
 397         {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } }
 398 };
 399
 400 static struct iga1_crtc_timing iga1_crtc_reg = {
 401         /* IGA1 Horizontal Total */
 402         {IGA1_HOR_TOTAL_REG_NUM, {{CR00, 0, 7}, {CR36, 3, 3} } },
 403         /* IGA1 Horizontal Addressable Video */
 404         {IGA1_HOR_ADDR_REG_NUM, {{CR01, 0, 7} } },
 405         /* IGA1 Horizontal Blank Start */
 406         {IGA1_HOR_BLANK_START_REG_NUM, {{CR02, 0, 7} } },
 407         /* IGA1 Horizontal Blank End */
 408         {IGA1_HOR_BLANK_END_REG_NUM,
 409          {{CR03, 0, 4}, {CR05, 7, 7}, {CR33, 5, 5} } },
 410         /* IGA1 Horizontal Sync Start */
 411         {IGA1_HOR_SYNC_START_REG_NUM, {{CR04, 0, 7}, {CR33, 4, 4} } },
 412         /* IGA1 Horizontal Sync End */
 413         {IGA1_HOR_SYNC_END_REG_NUM, {{CR05, 0, 4} } },
 414         /* IGA1 Vertical Total */
 415         {IGA1_VER_TOTAL_REG_NUM,
 416          {{CR06, 0, 7}, {CR07, 0, 0}, {CR07, 5, 5}, {CR35, 0, 0} } },
 417         /* IGA1 Vertical Addressable Video */
 418         {IGA1_VER_ADDR_REG_NUM,
 419          {{CR12, 0, 7}, {CR07, 1, 1}, {CR07, 6, 6}, {CR35, 2, 2} } },
 420         /* IGA1 Vertical Blank Start */
 421         {IGA1_VER_BLANK_START_REG_NUM,
 422          {{CR15, 0, 7}, {CR07, 3, 3}, {CR09, 5, 5}, {CR35, 3, 3} } },
 423         /* IGA1 Vertical Blank End */
 424         {IGA1_VER_BLANK_END_REG_NUM, {{CR16, 0, 7} } },
 425         /* IGA1 Vertical Sync Start */
 426         {IGA1_VER_SYNC_START_REG_NUM,
 427          {{CR10, 0, 7}, {CR07, 2, 2}, {CR07, 7, 7}, {CR35, 1, 1} } },
 428         /* IGA1 Vertical Sync End */
 429         {IGA1_VER_SYNC_END_REG_NUM, {{CR11, 0, 3} } }
 430 };
 431
 432 static struct iga2_crtc_timing iga2_crtc_reg = {
 433         /* IGA2 Horizontal Total */
 434         {IGA2_HOR_TOTAL_REG_NUM, {{CR50, 0, 7}, {CR55, 0, 3} } },
 435         /* IGA2 Horizontal Addressable Video */
 436         {IGA2_HOR_ADDR_REG_NUM, {{CR51, 0, 7}, {CR55, 4, 6} } },
 437         /* IGA2 Horizontal Blank Start */
 438         {IGA2_HOR_BLANK_START_REG_NUM, {{CR52, 0, 7}, {CR54, 0, 2} } },
 439         /* IGA2 Horizontal Blank End */
 440         {IGA2_HOR_BLANK_END_REG_NUM,
 441          {{CR53, 0, 7}, {CR54, 3, 5}, {CR5D, 6, 6} } },
 442         /* IGA2 Horizontal Sync Start */
 443         {IGA2_HOR_SYNC_START_REG_NUM,
 444          {{CR56, 0, 7}, {CR54, 6, 7}, {CR5C, 7, 7}, {CR5D, 7, 7} } },
 445         /* IGA2 Horizontal Sync End */
 446         {IGA2_HOR_SYNC_END_REG_NUM, {{CR57, 0, 7}, {CR5C, 6, 6} } },
 447         /* IGA2 Vertical Total */
 448         {IGA2_VER_TOTAL_REG_NUM, {{CR58, 0, 7}, {CR5D, 0, 2} } },
 449         /* IGA2 Vertical Addressable Video */
 450         {IGA2_VER_ADDR_REG_NUM, {{CR59, 0, 7}, {CR5D, 3, 5} } },
 451         /* IGA2 Vertical Blank Start */
 452         {IGA2_VER_BLANK_START_REG_NUM, {{CR5A, 0, 7}, {CR5C, 0, 2} } },
 453         /* IGA2 Vertical Blank End */
 454         {IGA2_VER_BLANK_END_REG_NUM, {{CR5B, 0, 7}, {CR5C, 3, 5} } },
 455         /* IGA2 Vertical Sync Start */
 456         {IGA2_VER_SYNC_START_REG_NUM, {{CR5E, 0, 7}, {CR5F, 5, 7} } },
 457         /* IGA2 Vertical Sync End */
 458         {IGA2_VER_SYNC_END_REG_NUM, {{CR5F, 0, 4} } }
 459 };
 460
 461 static struct rgbLUT palLUT_table[] = {
 462         /* {R,G,B} */
 463         /* Index 0x00~0x03 */
 464         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00,
 465                                                                      0x2A,
 466                                                                      0x2A},
 467         /* Index 0x04~0x07 */
 468         {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A,
 469                                                                      0x2A,
 470                                                                      0x2A},
 471         /* Index 0x08~0x0B */
 472         {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15,
 473                                                                      0x3F,
 474                                                                      0x3F},
 475         /* Index 0x0C~0x0F */
 476         {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F,
 477                                                                      0x3F,
 478                                                                      0x3F},
 479         /* Index 0x10~0x13 */
 480         {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B,
 481                                                                      0x0B,
 482                                                                      0x0B},
 483         /* Index 0x14~0x17 */
 484         {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18,
 485                                                                      0x18,
 486                                                                      0x18},
 487         /* Index 0x18~0x1B */
 488         {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28,
 489                                                                      0x28,
 490                                                                      0x28},
 491         /* Index 0x1C~0x1F */
 492         {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F,
 493                                                                      0x3F,
 494                                                                      0x3F},
 495         /* Index 0x20~0x23 */
 496         {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F,
 497                                                                      0x00,
 498                                                                      0x3F},
 499         /* Index 0x24~0x27 */
 500         {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F,
 501                                                                      0x00,
 502                                                                      0x10},
 503         /* Index 0x28~0x2B */
 504         {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F,
 505                                                                      0x2F,
 506                                                                      0x00},
 507         /* Index 0x2C~0x2F */
 508         {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10,
 509                                                                      0x3F,
 510                                                                      0x00},
 511         /* Index 0x30~0x33 */
 512         {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00,
 513                                                                      0x3F,
 514                                                                      0x2F},
 515         /* Index 0x34~0x37 */
 516         {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00,
 517                                                                      0x10,
 518                                                                      0x3F},
 519         /* Index 0x38~0x3B */
 520         {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37,
 521                                                                      0x1F,
 522                                                                      0x3F},
 523         /* Index 0x3C~0x3F */
 524         {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F,
 525                                                                      0x1F,
 526                                                                      0x27},
 527         /* Index 0x40~0x43 */
 528         {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F,
 529                                                                      0x3F,
 530                                                                      0x1F},
 531         /* Index 0x44~0x47 */
 532         {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27,
 533                                                                      0x3F,
 534                                                                      0x1F},
 535         /* Index 0x48~0x4B */
 536         {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F,
 537                                                                      0x3F,
 538                                                                      0x37},
 539         /* Index 0x4C~0x4F */
 540         {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F,
 541                                                                      0x27,
 542                                                                      0x3F},
 543         /* Index 0x50~0x53 */
 544         {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A,
 545                                                                      0x2D,
 546                                                                      0x3F},
 547         /* Index 0x54~0x57 */
 548         {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F,
 549                                                                      0x2D,
 550                                                                      0x31},
 551         /* Index 0x58~0x5B */
 552         {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F,
 553                                                                      0x3A,
 554                                                                      0x2D},
 555         /* Index 0x5C~0x5F */
 556         {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31,
 557                                                                      0x3F,
 558                                                                      0x2D},
 559         /* Index 0x60~0x63 */
 560         {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D,
 561                                                                      0x3F,
 562                                                                      0x3A},
 563         /* Index 0x64~0x67 */
 564         {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D,
 565                                                                      0x31,
 566                                                                      0x3F},
 567         /* Index 0x68~0x6B */
 568         {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15,
 569                                                                      0x00,
 570                                                                      0x1C},
 571         /* Index 0x6C~0x6F */
 572         {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C,
 573                                                                      0x00,
 574                                                                      0x07},
 575         /* Index 0x70~0x73 */
 576         {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C,
 577                                                                      0x15,
 578                                                                      0x00},
 579         /* Index 0x74~0x77 */
 580         {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07,
 581                                                                      0x1C,
 582                                                                      0x00},
 583         /* Index 0x78~0x7B */
 584         {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00,
 585                                                                      0x1C,
 586                                                                      0x15},
 587         /* Index 0x7C~0x7F */
 588         {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00,
 589                                                                      0x07,
 590                                                                      0x1C},
 591         /* Index 0x80~0x83 */
 592         {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18,
 593                                                                      0x0E,
 594                                                                      0x1C},
 595         /* Index 0x84~0x87 */
 596         {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C,
 597                                                                      0x0E,
 598                                                                      0x11},
 599         /* Index 0x88~0x8B */
 600         {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C,
 601                                                                      0x18,
 602                                                                      0x0E},
 603         /* Index 0x8C~0x8F */
 604         {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11,
 605                                                                      0x1C,
 606                                                                      0x0E},
 607         /* Index 0x90~0x93 */
 608         {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E,
 609                                                                      0x1C,
 610                                                                      0x18},
 611         /* Index 0x94~0x97 */
 612         {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E,
 613                                                                      0x11,
 614                                                                      0x1C},
 615         /* Index 0x98~0x9B */
 616         {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A,
 617                                                                      0x14,
 618                                                                      0x1C},
 619         /* Index 0x9C~0x9F */
 620         {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C,
 621                                                                      0x14,
 622                                                                      0x16},
 623         /* Index 0xA0~0xA3 */
 624         {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C,
 625                                                                      0x1A,
 626                                                                      0x14},
 627         /* Index 0xA4~0xA7 */
 628         {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16,
 629                                                                      0x1C,
 630                                                                      0x14},
 631         /* Index 0xA8~0xAB */
 632         {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14,
 633                                                                      0x1C,
 634                                                                      0x1A},
 635         /* Index 0xAC~0xAF */
 636         {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14,
 637                                                                      0x16,
 638                                                                      0x1C},
 639         /* Index 0xB0~0xB3 */
 640         {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C,
 641                                                                      0x00,
 642                                                                      0x10},
 643         /* Index 0xB4~0xB7 */
 644         {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10,
 645                                                                      0x00,
 646                                                                      0x04},
 647         /* Index 0xB8~0xBB */
 648         {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10,
 649                                                                      0x0C,
 650                                                                      0x00},
 651         /* Index 0xBC~0xBF */
 652         {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04,
 653                                                                      0x10,
 654                                                                      0x00},
 655         /* Index 0xC0~0xC3 */
 656         {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00,
 657                                                                      0x10,
 658                                                                      0x0C},
 659         /* Index 0xC4~0xC7 */
 660         {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00,
 661                                                                      0x04,
 662                                                                      0x10},
 663         /* Index 0xC8~0xCB */
 664         {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E,
 665                                                                      0x08,
 666                                                                      0x10},
 667         /* Index 0xCC~0xCF */
 668         {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10,
 669                                                                      0x08,
 670                                                                      0x0A},
 671         /* Index 0xD0~0xD3 */
 672         {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10,
 673                                                                      0x0E,
 674                                                                      0x08},
 675         /* Index 0xD4~0xD7 */
 676         {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A,
 677                                                                      0x10,
 678                                                                      0x08},
 679         /* Index 0xD8~0xDB */
 680         {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08,
 681                                                                      0x10,
 682                                                                      0x0E},
 683         /* Index 0xDC~0xDF */
 684         {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08,
 685                                                                      0x0A,
 686                                                                      0x10},
 687         /* Index 0xE0~0xE3 */
 688         {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F,
 689                                                                      0x0B,
 690                                                                      0x10},
 691         /* Index 0xE4~0xE7 */
 692         {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10,
 693                                                                      0x0B,
 694                                                                      0x0C},
 695         /* Index 0xE8~0xEB */
 696         {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10,
 697                                                                      0x0F,
 698                                                                      0x0B},
 699         /* Index 0xEC~0xEF */
 700         {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C,
 701                                                                      0x10,
 702                                                                      0x0B},
 703         /* Index 0xF0~0xF3 */
 704         {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B,
 705                                                                      0x10,
 706                                                                      0x0F},
 707         /* Index 0xF4~0xF7 */
 708         {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B,
 709                                                                      0x0C,
 710                                                                      0x10},
 711         /* Index 0xF8~0xFB */
 712         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
 713                                                                      0x00,
 714                                                                      0x00},
 715         /* Index 0xFC~0xFF */
 716         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
 717                                                                      0x00,
 718                                                                      0x00}
 719 };
 720
 721 static void set_crt_output_path(int set_iga);
 722 static void dvi_patch_skew_dvp0(void);
 723 static void dvi_patch_skew_dvp_low(void);
 724 static void set_dvi_output_path(int set_iga, int output_interface);
 725 static void set_lcd_output_path(int set_iga, int output_interface);
 726 static void load_fix_bit_crtc_reg(void);
 727 static void init_gfx_chip_info(int chip_type);
 728 static void init_tmds_chip_info(void);
 729 static void init_lvds_chip_info(void);
 730 static void device_screen_off(void);
 731 static void device_screen_on(void);
 732 static void set_display_channel(void);
 733 static void device_off(void);
 734 static void device_on(void);
 735 static void enable_second_display_channel(void);
 736 static void disable_second_display_channel(void);
 737
 738 void viafb_lock_crt(void)
 739 {
 740         viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);
 741 }
 742
 743 void viafb_unlock_crt(void)
 744 {
 745         viafb_write_reg_mask(CR11, VIACR, 0, BIT7);
 746         viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
 747 }
 748
 749 void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
 750 {
 751         outb(index, LUT_INDEX_WRITE);
 752         outb(r, LUT_DATA);
 753         outb(g, LUT_DATA);
 754         outb(b, LUT_DATA);
 755 }
 756
 757 /*Set IGA path for each device*/
 758 void viafb_set_iga_path(void)
 759 {
 760
 761         if (viafb_SAMM_ON == 1) {
 762                 if (viafb_CRT_ON) {
 763                         if (viafb_primary_dev == CRT_Device)
 764                                 viaparinfo->crt_setting_info->iga_path = IGA1;
 765                         else
 766                                 viaparinfo->crt_setting_info->iga_path = IGA2;
 767                 }
 768
 769                 if (viafb_DVI_ON) {
 770                         if (viafb_primary_dev == DVI_Device)
 771                                 viaparinfo->tmds_setting_info->iga_path = IGA1;
 772                         else
 773                                 viaparinfo->tmds_setting_info->iga_path = IGA2;
 774                 }
 775
 776                 if (viafb_LCD_ON) {
 777                         if (viafb_primary_dev == LCD_Device) {
 778                                 if (viafb_dual_fb &&
 779                                         (viaparinfo->chip_info->gfx_chip_name ==
 780                                         UNICHROME_CLE266)) {
 781                                         viaparinfo->
 782                                         lvds_setting_info->iga_path = IGA2;
 783                                         viaparinfo->
 784                                         crt_setting_info->iga_path = IGA1;
 785                                         viaparinfo->
 786                                         tmds_setting_info->iga_path = IGA1;
 787                                 } else
 788                                         viaparinfo->
 789                                         lvds_setting_info->iga_path = IGA1;
 790                         } else {
 791                                 viaparinfo->lvds_setting_info->iga_path = IGA2;
 792                         }
 793                 }
 794                 if (viafb_LCD2_ON) {
 795                         if (LCD2_Device == viafb_primary_dev)
 796                                 viaparinfo->lvds_setting_info2->iga_path = IGA1;
 797                         else
 798                                 viaparinfo->lvds_setting_info2->iga_path = IGA2;
 799                 }
 800         } else {
 801                 viafb_SAMM_ON = 0;
 802
 803                 if (viafb_CRT_ON && viafb_LCD_ON) {
 804                         viaparinfo->crt_setting_info->iga_path = IGA1;
 805                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 806                 } else if (viafb_CRT_ON && viafb_DVI_ON) {
 807                         viaparinfo->crt_setting_info->iga_path = IGA1;
 808                         viaparinfo->tmds_setting_info->iga_path = IGA2;
 809                 } else if (viafb_LCD_ON && viafb_DVI_ON) {
 810                         viaparinfo->tmds_setting_info->iga_path = IGA1;
 811                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 812                 } else if (viafb_LCD_ON && viafb_LCD2_ON) {
 813                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 814                         viaparinfo->lvds_setting_info2->iga_path = IGA2;
 815                 } else if (viafb_CRT_ON) {
 816                         viaparinfo->crt_setting_info->iga_path = IGA1;
 817                 } else if (viafb_LCD_ON) {
 818                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 819                 } else if (viafb_DVI_ON) {
 820                         viaparinfo->tmds_setting_info->iga_path = IGA1;
 821                 }
 822         }
 823 }
 824
 825 static void set_color_register(u8 index, u8 red, u8 green, u8 blue)
 826 {
 827         outb(0xFF, 0x3C6); /* bit mask of palette */
 828         outb(index, 0x3C8);
 829         outb(red, 0x3C9);
 830         outb(green, 0x3C9);
 831         outb(blue, 0x3C9);
 832 }
 833
 834 void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue)
 835 {
 836         viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01);
 837         set_color_register(index, red, green, blue);
 838 }
 839
 840 void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue)
 841 {
 842         viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01);
 843         set_color_register(index, red, green, blue);
 844 }
 845
 846 void viafb_set_output_path(int device, int set_iga, int output_interface)
 847 {
 848         switch (device) {
 849         case DEVICE_CRT:
 850                 set_crt_output_path(set_iga);
 851                 break;
 852         case DEVICE_DVI:
 853                 set_dvi_output_path(set_iga, output_interface);
 854                 break;
 855         case DEVICE_LCD:
 856                 set_lcd_output_path(set_iga, output_interface);
 857                 break;
 858         }
 859 }
 860
 861 static void set_crt_output_path(int set_iga)
 862 {
 863         viafb_write_reg_mask(CR36, VIACR, 0x00, BIT4 + BIT5);
 864
 865         switch (set_iga) {
 866         case IGA1:
 867                 viafb_write_reg_mask(SR16, VIASR, 0x00, BIT6);
 868                 break;
 869         case IGA2:
 870                 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
 871                 viafb_write_reg_mask(SR16, VIASR, 0x40, BIT6);
 872                 break;
 873         }
 874 }
 875
 876 static void dvi_patch_skew_dvp0(void)
 877 {
 878         /* Reset data driving first: */
 879         viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);
 880         viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);
 881
 882         switch (viaparinfo->chip_info->gfx_chip_name) {
 883         case UNICHROME_P4M890:
 884                 {
 885                         if ((viaparinfo->tmds_setting_info->h_active == 1600) &&
 886                                 (viaparinfo->tmds_setting_info->v_active ==
 887                                 1200))
 888                                 viafb_write_reg_mask(CR96, VIACR, 0x03,
 889                                                BIT0 + BIT1 + BIT2);
 890                         else
 891                                 viafb_write_reg_mask(CR96, VIACR, 0x07,
 892                                                BIT0 + BIT1 + BIT2);
 893                         break;
 894                 }
 895
 896         case UNICHROME_P4M900:
 897                 {
 898                         viafb_write_reg_mask(CR96, VIACR, 0x07,
 899                                        BIT0 + BIT1 + BIT2 + BIT3);
 900                         viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);
 901                         viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);
 902                         break;
 903                 }
 904
 905         default:
 906                 {
 907                         break;
 908                 }
 909         }
 910 }
 911
 912 static void dvi_patch_skew_dvp_low(void)
 913 {
 914         switch (viaparinfo->chip_info->gfx_chip_name) {
 915         case UNICHROME_K8M890:
 916                 {
 917                         viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
 918                         break;
 919                 }
 920
 921         case UNICHROME_P4M900:
 922                 {
 923                         viafb_write_reg_mask(CR99, VIACR, 0x08,
 924                                        BIT0 + BIT1 + BIT2 + BIT3);
 925                         break;
 926                 }
 927
 928         case UNICHROME_P4M890:
 929                 {
 930                         viafb_write_reg_mask(CR99, VIACR, 0x0F,
 931                                        BIT0 + BIT1 + BIT2 + BIT3);
 932                         break;
 933                 }
 934
 935         default:
 936                 {
 937                         break;
 938                 }
 939         }
 940 }
 941
 942 static void set_dvi_output_path(int set_iga, int output_interface)
 943 {
 944         switch (output_interface) {
 945         case INTERFACE_DVP0:
 946                 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);
 947
 948                 if (set_iga == IGA1) {
 949                         viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
 950                         viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 +
 951                                 BIT5 + BIT7);
 952                 } else {
 953                         viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
 954                         viafb_write_reg_mask(CR6C, VIACR, 0xA1, BIT0 +
 955                                 BIT5 + BIT7);
 956                 }
 957
 958                 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT7 + BIT6);
 959
 960                 dvi_patch_skew_dvp0();
 961                 break;
 962
 963         case INTERFACE_DVP1:
 964                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
 965                         if (set_iga == IGA1)
 966                                 viafb_write_reg_mask(CR93, VIACR, 0x21,
 967                                                BIT0 + BIT5 + BIT7);
 968                         else
 969                                 viafb_write_reg_mask(CR93, VIACR, 0xA1,
 970                                                BIT0 + BIT5 + BIT7);
 971                 } else {
 972                         if (set_iga == IGA1)
 973                                 viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
 974                         else
 975                                 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
 976                 }
 977
 978                 viafb_write_reg_mask(SR1E, VIASR, 0x30, BIT4 + BIT5);
 979                 break;
 980         case INTERFACE_DFP_HIGH:
 981                 if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266) {
 982                         if (set_iga == IGA1) {
 983                                 viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
 984                                 viafb_write_reg_mask(CR97, VIACR, 0x03,
 985                                                BIT0 + BIT1 + BIT4);
 986                         } else {
 987                                 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
 988                                 viafb_write_reg_mask(CR97, VIACR, 0x13,
 989                                                BIT0 + BIT1 + BIT4);
 990                         }
 991                 }
 992                 viafb_write_reg_mask(SR2A, VIASR, 0x0C, BIT2 + BIT3);
 993                 break;
 994
 995         case INTERFACE_DFP_LOW:
 996                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
 997                         break;
 998
 999                 if (set_iga == IGA1) {
1000                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
1001                         viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
1002                 } else {
1003                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
1004                         viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
1005                 }
1006
1007                 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
1008                 dvi_patch_skew_dvp_low();
1009                 break;
1010
1011         case INTERFACE_TMDS:
1012                 if (set_iga == IGA1)
1013                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
1014                 else
1015                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
1016                 break;
1017         }
1018
1019         if (set_iga == IGA2) {
1020                 enable_second_display_channel();
1021                 /* Disable LCD Scaling */
1022                 viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);
1023         }
1024 }
1025
1026 static void set_lcd_output_path(int set_iga, int output_interface)
1027 {
1028         DEBUG_MSG(KERN_INFO
1029                   "set_lcd_output_path, iga:%d,out_interface:%d\n",
1030                   set_iga, output_interface);
1031         switch (set_iga) {
1032         case IGA1:
1033                 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
1034                 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
1035
1036                 disable_second_display_channel();
1037                 break;
1038
1039         case IGA2:
1040                 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
1041                 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
1042
1043                 enable_second_display_channel();
1044                 break;
1045         }
1046
1047         switch (output_interface) {
1048         case INTERFACE_DVP0:
1049                 if (set_iga == IGA1) {
1050                         viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
1051                 } else {
1052                         viafb_write_reg(CR91, VIACR, 0x00);
1053                         viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
1054                 }
1055                 break;
1056
1057         case INTERFACE_DVP1:
1058                 if (set_iga == IGA1)
1059                         viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
1060                 else {
1061                         viafb_write_reg(CR91, VIACR, 0x00);
1062                         viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
1063                 }
1064                 break;
1065
1066         case INTERFACE_DFP_HIGH:
1067                 if (set_iga == IGA1)
1068                         viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
1069                 else {
1070                         viafb_write_reg(CR91, VIACR, 0x00);
1071                         viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
1072                         viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
1073                 }
1074                 break;
1075
1076         case INTERFACE_DFP_LOW:
1077                 if (set_iga == IGA1)
1078                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
1079                 else {
1080                         viafb_write_reg(CR91, VIACR, 0x00);
1081                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
1082                         viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
1083                 }
1084
1085                 break;
1086
1087         case INTERFACE_DFP:
1088                 if ((UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name)
1089                     || (UNICHROME_P4M890 ==
1090                     viaparinfo->chip_info->gfx_chip_name))
1091                         viafb_write_reg_mask(CR97, VIACR, 0x84,
1092                                        BIT7 + BIT2 + BIT1 + BIT0);
1093                 if (set_iga == IGA1) {
1094                         viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
1095                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
1096                 } else {
1097                         viafb_write_reg(CR91, VIACR, 0x00);
1098                         viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
1099                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
1100                 }
1101                 break;
1102
1103         case INTERFACE_LVDS0:
1104         case INTERFACE_LVDS0LVDS1:
1105                 if (set_iga == IGA1)
1106                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
1107                 else
1108                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
1109
1110                 break;
1111
1112         case INTERFACE_LVDS1:
1113                 if (set_iga == IGA1)
1114                         viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
1115                 else
1116                         viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
1117                 break;
1118         }
1119 }
1120
1121 static void load_fix_bit_crtc_reg(void)
1122 {
1123         /* always set to 1 */
1124         viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
1125         /* line compare should set all bits = 1 (extend modes) */
1126         viafb_write_reg(CR18, VIACR, 0xff);
1127         /* line compare should set all bits = 1 (extend modes) */
1128         viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4);
1129         /* line compare should set all bits = 1 (extend modes) */
1130         viafb_write_reg_mask(CR09, VIACR, 0x40, BIT6);
1131         /* line compare should set all bits = 1 (extend modes) */
1132         viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
1133         /* line compare should set all bits = 1 (extend modes) */
1134         viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
1135         /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */
1136         /* extend mode always set to e3h */
1137         viafb_write_reg(CR17, VIACR, 0xe3);
1138         /* extend mode always set to 0h */
1139         viafb_write_reg(CR08, VIACR, 0x00);
1140         /* extend mode always set to 0h */
1141         viafb_write_reg(CR14, VIACR, 0x00);
1142
1143         /* If K8M800, enable Prefetch Mode. */
1144         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
1145                 || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890))
1146                 viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);
1147         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
1148             && (viaparinfo->chip_info->gfx_chip_revision == CLE266_REVISION_AX))
1149                 viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);
1150
1151 }
1152
1153 void viafb_load_reg(int timing_value, int viafb_load_reg_num,
1154         struct io_register *reg,
1155               int io_type)
1156 {
1157         int reg_mask;
1158         int bit_num = 0;
1159         int data;
1160         int i, j;
1161         int shift_next_reg;
1162         int start_index, end_index, cr_index;
1163         u16 get_bit;
1164
1165         for (i = 0; i < viafb_load_reg_num; i++) {
1166                 reg_mask = 0;
1167                 data = 0;
1168                 start_index = reg[i].start_bit;
1169                 end_index = reg[i].end_bit;
1170                 cr_index = reg[i].io_addr;
1171
1172                 shift_next_reg = bit_num;
1173                 for (j = start_index; j <= end_index; j++) {
1174                         /*if (bit_num==8) timing_value = timing_value >>8; */
1175                         reg_mask = reg_mask | (BIT0 << j);
1176                         get_bit = (timing_value & (BIT0 << bit_num));
1177                         data =
1178                             data | ((get_bit >> shift_next_reg) << start_index);
1179                         bit_num++;
1180                 }
1181                 if (io_type == VIACR)
1182                         viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);
1183                 else
1184                         viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);
1185         }
1186
1187 }
1188
1189 /* Write Registers */
1190 void viafb_write_regx(struct io_reg RegTable[], int ItemNum)
1191 {
1192         int i;
1193
1194         /*DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum ); */
1195
1196         for (i = 0; i < ItemNum; i++)
1197                 via_write_reg_mask(RegTable[i].port, RegTable[i].index,
1198                         RegTable[i].value, RegTable[i].mask);
1199 }
1200
1201 void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga)
1202 {
1203         int reg_value;
1204         int viafb_load_reg_num;
1205         struct io_register *reg = NULL;
1206
1207         switch (set_iga) {
1208         case IGA1:
1209                 reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1210                 viafb_load_reg_num = fetch_count_reg.
1211                         iga1_fetch_count_reg.reg_num;
1212                 reg = fetch_count_reg.iga1_fetch_count_reg.reg;
1213                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1214                 break;
1215         case IGA2:
1216                 reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1217                 viafb_load_reg_num = fetch_count_reg.
1218                         iga2_fetch_count_reg.reg_num;
1219                 reg = fetch_count_reg.iga2_fetch_count_reg.reg;
1220                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1221                 break;
1222         }
1223
1224 }
1225
1226 void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1227 {
1228         int reg_value;
1229         int viafb_load_reg_num;
1230         struct io_register *reg = NULL;
1231         int iga1_fifo_max_depth = 0, iga1_fifo_threshold =
1232             0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0;
1233         int iga2_fifo_max_depth = 0, iga2_fifo_threshold =
1234             0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0;
1235
1236         if (set_iga == IGA1) {
1237                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1238                         iga1_fifo_max_depth = K800_IGA1_FIFO_MAX_DEPTH;
1239                         iga1_fifo_threshold = K800_IGA1_FIFO_THRESHOLD;
1240                         iga1_fifo_high_threshold =
1241                             K800_IGA1_FIFO_HIGH_THRESHOLD;
1242                         /* If resolution > 1280x1024, expire length = 64, else
1243                            expire length = 128 */
1244                         if ((hor_active > 1280) && (ver_active > 1024))
1245                                 iga1_display_queue_expire_num = 16;
1246                         else
1247                                 iga1_display_queue_expire_num =
1248                                     K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1249
1250                 }
1251
1252                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1253                         iga1_fifo_max_depth = P880_IGA1_FIFO_MAX_DEPTH;
1254                         iga1_fifo_threshold = P880_IGA1_FIFO_THRESHOLD;
1255                         iga1_fifo_high_threshold =
1256                             P880_IGA1_FIFO_HIGH_THRESHOLD;
1257                         iga1_display_queue_expire_num =
1258                             P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1259
1260                         /* If resolution > 1280x1024, expire length = 64, else
1261                            expire length = 128 */
1262                         if ((hor_active > 1280) && (ver_active > 1024))
1263                                 iga1_display_queue_expire_num = 16;
1264                         else
1265                                 iga1_display_queue_expire_num =
1266                                     P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1267                 }
1268
1269                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1270                         iga1_fifo_max_depth = CN700_IGA1_FIFO_MAX_DEPTH;
1271                         iga1_fifo_threshold = CN700_IGA1_FIFO_THRESHOLD;
1272                         iga1_fifo_high_threshold =
1273                             CN700_IGA1_FIFO_HIGH_THRESHOLD;
1274
1275                         /* If resolution > 1280x1024, expire length = 64,
1276                            else expire length = 128 */
1277                         if ((hor_active > 1280) && (ver_active > 1024))
1278                                 iga1_display_queue_expire_num = 16;
1279                         else
1280                                 iga1_display_queue_expire_num =
1281                                     CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1282                 }
1283
1284                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1285                         iga1_fifo_max_depth = CX700_IGA1_FIFO_MAX_DEPTH;
1286                         iga1_fifo_threshold = CX700_IGA1_FIFO_THRESHOLD;
1287                         iga1_fifo_high_threshold =
1288                             CX700_IGA1_FIFO_HIGH_THRESHOLD;
1289                         iga1_display_queue_expire_num =
1290                             CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1291                 }
1292
1293                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1294                         iga1_fifo_max_depth = K8M890_IGA1_FIFO_MAX_DEPTH;
1295                         iga1_fifo_threshold = K8M890_IGA1_FIFO_THRESHOLD;
1296                         iga1_fifo_high_threshold =
1297                             K8M890_IGA1_FIFO_HIGH_THRESHOLD;
1298                         iga1_display_queue_expire_num =
1299                             K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1300                 }
1301
1302                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1303                         iga1_fifo_max_depth = P4M890_IGA1_FIFO_MAX_DEPTH;
1304                         iga1_fifo_threshold = P4M890_IGA1_FIFO_THRESHOLD;
1305                         iga1_fifo_high_threshold =
1306                             P4M890_IGA1_FIFO_HIGH_THRESHOLD;
1307                         iga1_display_queue_expire_num =
1308                             P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1309                 }
1310
1311                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1312                         iga1_fifo_max_depth = P4M900_IGA1_FIFO_MAX_DEPTH;
1313                         iga1_fifo_threshold = P4M900_IGA1_FIFO_THRESHOLD;
1314                         iga1_fifo_high_threshold =
1315                             P4M900_IGA1_FIFO_HIGH_THRESHOLD;
1316                         iga1_display_queue_expire_num =
1317                             P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1318                 }
1319
1320                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1321                         iga1_fifo_max_depth = VX800_IGA1_FIFO_MAX_DEPTH;
1322                         iga1_fifo_threshold = VX800_IGA1_FIFO_THRESHOLD;
1323                         iga1_fifo_high_threshold =
1324                             VX800_IGA1_FIFO_HIGH_THRESHOLD;
1325                         iga1_display_queue_expire_num =
1326                             VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1327                 }
1328
1329                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1330                         iga1_fifo_max_depth = VX855_IGA1_FIFO_MAX_DEPTH;
1331                         iga1_fifo_threshold = VX855_IGA1_FIFO_THRESHOLD;
1332                         iga1_fifo_high_threshold =
1333                             VX855_IGA1_FIFO_HIGH_THRESHOLD;
1334                         iga1_display_queue_expire_num =
1335                             VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1336                 }
1337
1338                 /* Set Display FIFO Depath Select */
1339                 reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
1340                 viafb_load_reg_num =
1341                     display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num;
1342                 reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg;
1343                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1344
1345                 /* Set Display FIFO Threshold Select */
1346                 reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold);
1347                 viafb_load_reg_num =
1348                     fifo_threshold_select_reg.
1349                     iga1_fifo_threshold_select_reg.reg_num;
1350                 reg =
1351                     fifo_threshold_select_reg.
1352                     iga1_fifo_threshold_select_reg.reg;
1353                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1354
1355                 /* Set FIFO High Threshold Select */
1356                 reg_value =
1357                     IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold);
1358                 viafb_load_reg_num =
1359                     fifo_high_threshold_select_reg.
1360                     iga1_fifo_high_threshold_select_reg.reg_num;
1361                 reg =
1362                     fifo_high_threshold_select_reg.
1363                     iga1_fifo_high_threshold_select_reg.reg;
1364                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1365
1366                 /* Set Display Queue Expire Num */
1367                 reg_value =
1368                     IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1369                     (iga1_display_queue_expire_num);
1370                 viafb_load_reg_num =
1371                     display_queue_expire_num_reg.
1372                     iga1_display_queue_expire_num_reg.reg_num;
1373                 reg =
1374                     display_queue_expire_num_reg.
1375                     iga1_display_queue_expire_num_reg.reg;
1376                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1377
1378         } else {
1379                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1380                         iga2_fifo_max_depth = K800_IGA2_FIFO_MAX_DEPTH;
1381                         iga2_fifo_threshold = K800_IGA2_FIFO_THRESHOLD;
1382                         iga2_fifo_high_threshold =
1383                             K800_IGA2_FIFO_HIGH_THRESHOLD;
1384
1385                         /* If resolution > 1280x1024, expire length = 64,
1386                            else  expire length = 128 */
1387                         if ((hor_active > 1280) && (ver_active > 1024))
1388                                 iga2_display_queue_expire_num = 16;
1389                         else
1390                                 iga2_display_queue_expire_num =
1391                                     K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1392                 }
1393
1394                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1395                         iga2_fifo_max_depth = P880_IGA2_FIFO_MAX_DEPTH;
1396                         iga2_fifo_threshold = P880_IGA2_FIFO_THRESHOLD;
1397                         iga2_fifo_high_threshold =
1398                             P880_IGA2_FIFO_HIGH_THRESHOLD;
1399
1400                         /* If resolution > 1280x1024, expire length = 64,
1401                            else  expire length = 128 */
1402                         if ((hor_active > 1280) && (ver_active > 1024))
1403                                 iga2_display_queue_expire_num = 16;
1404                         else
1405                                 iga2_display_queue_expire_num =
1406                                     P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1407                 }
1408
1409                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1410                         iga2_fifo_max_depth = CN700_IGA2_FIFO_MAX_DEPTH;
1411                         iga2_fifo_threshold = CN700_IGA2_FIFO_THRESHOLD;
1412                         iga2_fifo_high_threshold =
1413                             CN700_IGA2_FIFO_HIGH_THRESHOLD;
1414
1415                         /* If resolution > 1280x1024, expire length = 64,
1416                            else expire length = 128 */
1417                         if ((hor_active > 1280) && (ver_active > 1024))
1418                                 iga2_display_queue_expire_num = 16;
1419                         else
1420                                 iga2_display_queue_expire_num =
1421                                     CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1422                 }
1423
1424                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1425                         iga2_fifo_max_depth = CX700_IGA2_FIFO_MAX_DEPTH;
1426                         iga2_fifo_threshold = CX700_IGA2_FIFO_THRESHOLD;
1427                         iga2_fifo_high_threshold =
1428                             CX700_IGA2_FIFO_HIGH_THRESHOLD;
1429                         iga2_display_queue_expire_num =
1430                             CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1431                 }
1432
1433                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1434                         iga2_fifo_max_depth = K8M890_IGA2_FIFO_MAX_DEPTH;
1435                         iga2_fifo_threshold = K8M890_IGA2_FIFO_THRESHOLD;
1436                         iga2_fifo_high_threshold =
1437                             K8M890_IGA2_FIFO_HIGH_THRESHOLD;
1438                         iga2_display_queue_expire_num =
1439                             K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1440                 }
1441
1442                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1443                         iga2_fifo_max_depth = P4M890_IGA2_FIFO_MAX_DEPTH;
1444                         iga2_fifo_threshold = P4M890_IGA2_FIFO_THRESHOLD;
1445                         iga2_fifo_high_threshold =
1446                             P4M890_IGA2_FIFO_HIGH_THRESHOLD;
1447                         iga2_display_queue_expire_num =
1448                             P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1449                 }
1450
1451                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1452                         iga2_fifo_max_depth = P4M900_IGA2_FIFO_MAX_DEPTH;
1453                         iga2_fifo_threshold = P4M900_IGA2_FIFO_THRESHOLD;
1454                         iga2_fifo_high_threshold =
1455                             P4M900_IGA2_FIFO_HIGH_THRESHOLD;
1456                         iga2_display_queue_expire_num =
1457                             P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1458                 }
1459
1460                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1461                         iga2_fifo_max_depth = VX800_IGA2_FIFO_MAX_DEPTH;
1462                         iga2_fifo_threshold = VX800_IGA2_FIFO_THRESHOLD;
1463                         iga2_fifo_high_threshold =
1464                             VX800_IGA2_FIFO_HIGH_THRESHOLD;
1465                         iga2_display_queue_expire_num =
1466                             VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1467                 }
1468
1469                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1470                         iga2_fifo_max_depth = VX855_IGA2_FIFO_MAX_DEPTH;
1471                         iga2_fifo_threshold = VX855_IGA2_FIFO_THRESHOLD;
1472                         iga2_fifo_high_threshold =
1473                             VX855_IGA2_FIFO_HIGH_THRESHOLD;
1474                         iga2_display_queue_expire_num =
1475                             VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1476                 }
1477
1478                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1479                         /* Set Display FIFO Depath Select */
1480                         reg_value =
1481                             IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth)
1482                             - 1;
1483                         /* Patch LCD in IGA2 case */
1484                         viafb_load_reg_num =
1485                             display_fifo_depth_reg.
1486                             iga2_fifo_depth_select_reg.reg_num;
1487                         reg =
1488                             display_fifo_depth_reg.
1489                             iga2_fifo_depth_select_reg.reg;
1490                         viafb_load_reg(reg_value,
1491                                 viafb_load_reg_num, reg, VIACR);
1492                 } else {
1493
1494                         /* Set Display FIFO Depath Select */
1495                         reg_value =
1496                             IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth);
1497                         viafb_load_reg_num =
1498                             display_fifo_depth_reg.
1499                             iga2_fifo_depth_select_reg.reg_num;
1500                         reg =
1501                             display_fifo_depth_reg.
1502                             iga2_fifo_depth_select_reg.reg;
1503                         viafb_load_reg(reg_value,
1504                                 viafb_load_reg_num, reg, VIACR);
1505                 }
1506
1507                 /* Set Display FIFO Threshold Select */
1508                 reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold);
1509                 viafb_load_reg_num =
1510                     fifo_threshold_select_reg.
1511                     iga2_fifo_threshold_select_reg.reg_num;
1512                 reg =
1513                     fifo_threshold_select_reg.
1514                     iga2_fifo_threshold_select_reg.reg;
1515                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1516
1517                 /* Set FIFO High Threshold Select */
1518                 reg_value =
1519                     IGA2_FIFO_HIGH_THRESHOLD_FORMULA(iga2_fifo_high_threshold);
1520                 viafb_load_reg_num =
1521                     fifo_high_threshold_select_reg.
1522                     iga2_fifo_high_threshold_select_reg.reg_num;
1523                 reg =
1524                     fifo_high_threshold_select_reg.
1525                     iga2_fifo_high_threshold_select_reg.reg;
1526                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1527
1528                 /* Set Display Queue Expire Num */
1529                 reg_value =
1530                     IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1531                     (iga2_display_queue_expire_num);
1532                 viafb_load_reg_num =
1533                     display_queue_expire_num_reg.
1534                     iga2_display_queue_expire_num_reg.reg_num;
1535                 reg =
1536                     display_queue_expire_num_reg.
1537                     iga2_display_queue_expire_num_reg.reg;
1538                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1539
1540         }
1541
1542 }
1543
1544 static u32 cle266_encode_pll(struct pll_config pll)
1545 {
1546         return (pll.multiplier << 8)
1547                 | (pll.rshift << 6)
1548                 | pll.divisor;
1549 }
1550
1551 static u32 k800_encode_pll(struct pll_config pll)
1552 {
1553         return ((pll.divisor - 2) << 16)
1554                 | (pll.rshift << 10)
1555                 | (pll.multiplier - 2);
1556 }
1557
1558 static u32 vx855_encode_pll(struct pll_config pll)
1559 {
1560         return (pll.divisor << 16)
1561                 | (pll.rshift << 10)
1562                 | pll.multiplier;
1563 }
1564
1565 u32 viafb_get_clk_value(int clk)
1566 {
1567         u32 value = 0;
1568         int i = 0;
1569
1570         while (i < NUM_TOTAL_PLL_TABLE && clk != pll_value[i].clk)
1571                 i++;
1572
1573         if (i == NUM_TOTAL_PLL_TABLE) {
1574                 printk(KERN_WARNING "viafb_get_clk_value: PLL lookup failed!");
1575         } else {
1576                 switch (viaparinfo->chip_info->gfx_chip_name) {
1577                 case UNICHROME_CLE266:
1578                 case UNICHROME_K400:
1579                         value = cle266_encode_pll(pll_value[i].cle266_pll);
1580                         break;
1581
1582                 case UNICHROME_K800:
1583                 case UNICHROME_PM800:
1584                 case UNICHROME_CN700:
1585                         value = k800_encode_pll(pll_value[i].k800_pll);
1586                         break;
1587
1588                 case UNICHROME_CX700:
1589                 case UNICHROME_CN750:
1590                 case UNICHROME_K8M890:
1591                 case UNICHROME_P4M890:
1592                 case UNICHROME_P4M900:
1593                 case UNICHROME_VX800:
1594                         value = k800_encode_pll(pll_value[i].cx700_pll);
1595                         break;
1596
1597                 case UNICHROME_VX855:
1598                         value = vx855_encode_pll(pll_value[i].vx855_pll);
1599                         break;
1600                 }
1601         }
1602
1603         return value;
1604 }
1605
1606 /* Set VCLK*/
1607 void viafb_set_vclock(u32 clk, int set_iga)
1608 {
1609         /* H.W. Reset : ON */
1610         viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1611
1612         if (set_iga == IGA1) {
1613                 /* Change D,N FOR VCLK */
1614                 switch (viaparinfo->chip_info->gfx_chip_name) {
1615                 case UNICHROME_CLE266:
1616                 case UNICHROME_K400:
1617                         via_write_reg(VIASR, SR46, (clk & 0x00FF));
1618                         via_write_reg(VIASR, SR47, (clk & 0xFF00) >> 8);
1619                         break;
1620
1621                 case UNICHROME_K800:
1622                 case UNICHROME_PM800:
1623                 case UNICHROME_CN700:
1624                 case UNICHROME_CX700:
1625                 case UNICHROME_CN750:
1626                 case UNICHROME_K8M890:
1627                 case UNICHROME_P4M890:
1628                 case UNICHROME_P4M900:
1629                 case UNICHROME_VX800:
1630                 case UNICHROME_VX855:
1631                         via_write_reg(VIASR, SR44, (clk & 0x0000FF));
1632                         via_write_reg(VIASR, SR45, (clk & 0x00FF00) >> 8);
1633                         via_write_reg(VIASR, SR46, (clk & 0xFF0000) >> 16);
1634                         break;
1635                 }
1636         }
1637
1638         if (set_iga == IGA2) {
1639                 /* Change D,N FOR LCK */
1640                 switch (viaparinfo->chip_info->gfx_chip_name) {
1641                 case UNICHROME_CLE266:
1642                 case UNICHROME_K400:
1643                         via_write_reg(VIASR, SR44, (clk & 0x00FF));
1644                         via_write_reg(VIASR, SR45, (clk & 0xFF00) >> 8);
1645                         break;
1646
1647                 case UNICHROME_K800:
1648                 case UNICHROME_PM800:
1649                 case UNICHROME_CN700:
1650                 case UNICHROME_CX700:
1651                 case UNICHROME_CN750:
1652                 case UNICHROME_K8M890:
1653                 case UNICHROME_P4M890:
1654                 case UNICHROME_P4M900:
1655                 case UNICHROME_VX800:
1656                 case UNICHROME_VX855:
1657                         via_write_reg(VIASR, SR4A, (clk & 0x0000FF));
1658                         via_write_reg(VIASR, SR4B, (clk & 0x00FF00) >> 8);
1659                         via_write_reg(VIASR, SR4C, (clk & 0xFF0000) >> 16);
1660                         break;
1661                 }
1662         }
1663
1664         /* H.W. Reset : OFF */
1665         viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1666
1667         /* Reset PLL */
1668         if (set_iga == IGA1) {
1669                 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
1670                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
1671         }
1672
1673         if (set_iga == IGA2) {
1674                 viafb_write_reg_mask(SR40, VIASR, 0x04, BIT2);
1675                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT2);
1676         }
1677
1678         /* Fire! */
1679         via_write_misc_reg_mask(0x0C, 0x0C); /* select external clock */
1680 }
1681
1682 void viafb_load_crtc_timing(struct display_timing device_timing,
1683         int set_iga)
1684 {
1685         int i;
1686         int viafb_load_reg_num = 0;
1687         int reg_value = 0;
1688         struct io_register *reg = NULL;
1689
1690         viafb_unlock_crt();
1691
1692         for (i = 0; i < 12; i++) {
1693                 if (set_iga == IGA1) {
1694                         switch (i) {
1695                         case H_TOTAL_INDEX:
1696                                 reg_value =
1697                                     IGA1_HOR_TOTAL_FORMULA(device_timing.
1698                                                            hor_total);
1699                                 viafb_load_reg_num =
1700                                         iga1_crtc_reg.hor_total.reg_num;
1701                                 reg = iga1_crtc_reg.hor_total.reg;
1702                                 break;
1703                         case H_ADDR_INDEX:
1704                                 reg_value =
1705                                     IGA1_HOR_ADDR_FORMULA(device_timing.
1706                                                           hor_addr);
1707                                 viafb_load_reg_num =
1708                                         iga1_crtc_reg.hor_addr.reg_num;
1709                                 reg = iga1_crtc_reg.hor_addr.reg;
1710                                 break;
1711                         case H_BLANK_START_INDEX:
1712                                 reg_value =
1713                                     IGA1_HOR_BLANK_START_FORMULA
1714                                     (device_timing.hor_blank_start);
1715                                 viafb_load_reg_num =
1716                                     iga1_crtc_reg.hor_blank_start.reg_num;
1717                                 reg = iga1_crtc_reg.hor_blank_start.reg;
1718                                 break;
1719                         case H_BLANK_END_INDEX:
1720                                 reg_value =
1721                                     IGA1_HOR_BLANK_END_FORMULA
1722                                     (device_timing.hor_blank_start,
1723                                      device_timing.hor_blank_end);
1724                                 viafb_load_reg_num =
1725                                     iga1_crtc_reg.hor_blank_end.reg_num;
1726                                 reg = iga1_crtc_reg.hor_blank_end.reg;
1727                                 break;
1728                         case H_SYNC_START_INDEX:
1729                                 reg_value =
1730                                     IGA1_HOR_SYNC_START_FORMULA
1731                                     (device_timing.hor_sync_start);
1732                                 viafb_load_reg_num =
1733                                     iga1_crtc_reg.hor_sync_start.reg_num;
1734                                 reg = iga1_crtc_reg.hor_sync_start.reg;
1735                                 break;
1736                         case H_SYNC_END_INDEX:
1737                                 reg_value =
1738                                     IGA1_HOR_SYNC_END_FORMULA
1739                                     (device_timing.hor_sync_start,
1740                                      device_timing.hor_sync_end);
1741                                 viafb_load_reg_num =
1742                                     iga1_crtc_reg.hor_sync_end.reg_num;
1743                                 reg = iga1_crtc_reg.hor_sync_end.reg;
1744                                 break;
1745                         case V_TOTAL_INDEX:
1746                                 reg_value =
1747                                     IGA1_VER_TOTAL_FORMULA(device_timing.
1748                                                            ver_total);
1749                                 viafb_load_reg_num =
1750                                         iga1_crtc_reg.ver_total.reg_num;
1751                                 reg = iga1_crtc_reg.ver_total.reg;
1752                                 break;
1753                         case V_ADDR_INDEX:
1754                                 reg_value =
1755                                     IGA1_VER_ADDR_FORMULA(device_timing.
1756                                                           ver_addr);
1757                                 viafb_load_reg_num =
1758                                         iga1_crtc_reg.ver_addr.reg_num;
1759                                 reg = iga1_crtc_reg.ver_addr.reg;
1760                                 break;
1761                         case V_BLANK_START_INDEX:
1762                                 reg_value =
1763                                     IGA1_VER_BLANK_START_FORMULA
1764                                     (device_timing.ver_blank_start);
1765                                 viafb_load_reg_num =
1766                                     iga1_crtc_reg.ver_blank_start.reg_num;
1767                                 reg = iga1_crtc_reg.ver_blank_start.reg;
1768                                 break;
1769                         case V_BLANK_END_INDEX:
1770                                 reg_value =
1771                                     IGA1_VER_BLANK_END_FORMULA
1772                                     (device_timing.ver_blank_start,
1773                                      device_timing.ver_blank_end);
1774                                 viafb_load_reg_num =
1775                                     iga1_crtc_reg.ver_blank_end.reg_num;
1776                                 reg = iga1_crtc_reg.ver_blank_end.reg;
1777                                 break;
1778                         case V_SYNC_START_INDEX:
1779                                 reg_value =
1780                                     IGA1_VER_SYNC_START_FORMULA
1781                                     (device_timing.ver_sync_start);
1782                                 viafb_load_reg_num =
1783                                     iga1_crtc_reg.ver_sync_start.reg_num;
1784                                 reg = iga1_crtc_reg.ver_sync_start.reg;
1785                                 break;
1786                         case V_SYNC_END_INDEX:
1787                                 reg_value =
1788                                     IGA1_VER_SYNC_END_FORMULA
1789                                     (device_timing.ver_sync_start,
1790                                      device_timing.ver_sync_end);
1791                                 viafb_load_reg_num =
1792                                     iga1_crtc_reg.ver_sync_end.reg_num;
1793                                 reg = iga1_crtc_reg.ver_sync_end.reg;
1794                                 break;
1795
1796                         }
1797                 }
1798
1799                 if (set_iga == IGA2) {
1800                         switch (i) {
1801                         case H_TOTAL_INDEX:
1802                                 reg_value =
1803                                     IGA2_HOR_TOTAL_FORMULA(device_timing.
1804                                                            hor_total);
1805                                 viafb_load_reg_num =
1806                                         iga2_crtc_reg.hor_total.reg_num;
1807                                 reg = iga2_crtc_reg.hor_total.reg;
1808                                 break;
1809                         case H_ADDR_INDEX:
1810                                 reg_value =
1811                                     IGA2_HOR_ADDR_FORMULA(device_timing.
1812                                                           hor_addr);
1813                                 viafb_load_reg_num =
1814                                         iga2_crtc_reg.hor_addr.reg_num;
1815                                 reg = iga2_crtc_reg.hor_addr.reg;
1816                                 break;
1817                         case H_BLANK_START_INDEX:
1818                                 reg_value =
1819                                     IGA2_HOR_BLANK_START_FORMULA
1820                                     (device_timing.hor_blank_start);
1821                                 viafb_load_reg_num =
1822                                     iga2_crtc_reg.hor_blank_start.reg_num;
1823                                 reg = iga2_crtc_reg.hor_blank_start.reg;
1824                                 break;
1825                         case H_BLANK_END_INDEX:
1826                                 reg_value =
1827                                     IGA2_HOR_BLANK_END_FORMULA
1828                                     (device_timing.hor_blank_start,
1829                                      device_timing.hor_blank_end);
1830                                 viafb_load_reg_num =
1831                                     iga2_crtc_reg.hor_blank_end.reg_num;
1832                                 reg = iga2_crtc_reg.hor_blank_end.reg;
1833                                 break;
1834                         case H_SYNC_START_INDEX:
1835                                 reg_value =
1836                                     IGA2_HOR_SYNC_START_FORMULA
1837                                     (device_timing.hor_sync_start);
1838                                 if (UNICHROME_CN700 <=
1839                                         viaparinfo->chip_info->gfx_chip_name)
1840                                         viafb_load_reg_num =
1841                                             iga2_crtc_reg.hor_sync_start.
1842                                             reg_num;
1843                                 else
1844                                         viafb_load_reg_num = 3;
1845                                 reg = iga2_crtc_reg.hor_sync_start.reg;
1846                                 break;
1847                         case H_SYNC_END_INDEX:
1848                                 reg_value =
1849                                     IGA2_HOR_SYNC_END_FORMULA
1850                                     (device_timing.hor_sync_start,
1851                                      device_timing.hor_sync_end);
1852                                 viafb_load_reg_num =
1853                                     iga2_crtc_reg.hor_sync_end.reg_num;
1854                                 reg = iga2_crtc_reg.hor_sync_end.reg;
1855                                 break;
1856                         case V_TOTAL_INDEX:
1857                                 reg_value =
1858                                     IGA2_VER_TOTAL_FORMULA(device_timing.
1859                                                            ver_total);
1860                                 viafb_load_reg_num =
1861                                         iga2_crtc_reg.ver_total.reg_num;
1862                                 reg = iga2_crtc_reg.ver_total.reg;
1863                                 break;
1864                         case V_ADDR_INDEX:
1865                                 reg_value =
1866                                     IGA2_VER_ADDR_FORMULA(device_timing.
1867                                                           ver_addr);
1868                                 viafb_load_reg_num =
1869                                         iga2_crtc_reg.ver_addr.reg_num;
1870                                 reg = iga2_crtc_reg.ver_addr.reg;
1871                                 break;
1872                         case V_BLANK_START_INDEX:
1873                                 reg_value =
1874                                     IGA2_VER_BLANK_START_FORMULA
1875                                     (device_timing.ver_blank_start);
1876                                 viafb_load_reg_num =
1877                                     iga2_crtc_reg.ver_blank_start.reg_num;
1878                                 reg = iga2_crtc_reg.ver_blank_start.reg;
1879                                 break;
1880                         case V_BLANK_END_INDEX:
1881                                 reg_value =
1882                                     IGA2_VER_BLANK_END_FORMULA
1883                                     (device_timing.ver_blank_start,
1884                                      device_timing.ver_blank_end);
1885                                 viafb_load_reg_num =
1886                                     iga2_crtc_reg.ver_blank_end.reg_num;
1887                                 reg = iga2_crtc_reg.ver_blank_end.reg;
1888                                 break;
1889                         case V_SYNC_START_INDEX:
1890                                 reg_value =
1891                                     IGA2_VER_SYNC_START_FORMULA
1892                                     (device_timing.ver_sync_start);
1893                                 viafb_load_reg_num =
1894                                     iga2_crtc_reg.ver_sync_start.reg_num;
1895                                 reg = iga2_crtc_reg.ver_sync_start.reg;
1896                                 break;
1897                         case V_SYNC_END_INDEX:
1898                                 reg_value =
1899                                     IGA2_VER_SYNC_END_FORMULA
1900                                     (device_timing.ver_sync_start,
1901                                      device_timing.ver_sync_end);
1902                                 viafb_load_reg_num =
1903                                     iga2_crtc_reg.ver_sync_end.reg_num;
1904                                 reg = iga2_crtc_reg.ver_sync_end.reg;
1905                                 break;
1906
1907                         }
1908                 }
1909                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1910         }
1911
1912         viafb_lock_crt();
1913 }
1914
1915 void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1916         struct VideoModeTable *video_mode, int bpp_byte, int set_iga)
1917 {
1918         struct display_timing crt_reg;
1919         int i;
1920         int index = 0;
1921         int h_addr, v_addr;
1922         u32 pll_D_N;
1923         u8 polarity = 0;
1924
1925         for (i = 0; i < video_mode->mode_array; i++) {
1926                 index = i;
1927
1928                 if (crt_table[i].refresh_rate == viaparinfo->
1929                         crt_setting_info->refresh_rate)
1930                         break;
1931         }
1932
1933         crt_reg = crt_table[index].crtc;
1934
1935         /* Mode 640x480 has border, but LCD/DFP didn't have border. */
1936         /* So we would delete border. */
1937         if ((viafb_LCD_ON | viafb_DVI_ON)
1938             && video_mode->crtc[0].crtc.hor_addr == 640
1939             && video_mode->crtc[0].crtc.ver_addr == 480
1940             && viaparinfo->crt_setting_info->refresh_rate == 60) {
1941                 /* The border is 8 pixels. */
1942                 crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8;
1943
1944                 /* Blanking time should add left and right borders. */
1945                 crt_reg.hor_blank_end = crt_reg.hor_blank_end + 16;
1946         }
1947
1948         h_addr = crt_reg.hor_addr;
1949         v_addr = crt_reg.ver_addr;
1950
1951         /* update polarity for CRT timing */
1952         if (crt_table[index].h_sync_polarity == NEGATIVE)
1953                 polarity |= BIT6;
1954         if (crt_table[index].v_sync_polarity == NEGATIVE)
1955                 polarity |= BIT7;
1956         via_write_misc_reg_mask(polarity, BIT6 | BIT7);
1957
1958         if (set_iga == IGA1) {
1959                 viafb_unlock_crt();
1960                 viafb_write_reg(CR09, VIACR, 0x00);     /*initial CR09=0 */
1961                 viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6);
1962                 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1963         }
1964
1965         switch (set_iga) {
1966         case IGA1:
1967                 viafb_load_crtc_timing(crt_reg, IGA1);
1968                 break;
1969         case IGA2:
1970                 viafb_load_crtc_timing(crt_reg, IGA2);
1971                 break;
1972         }
1973
1974         load_fix_bit_crtc_reg();
1975         viafb_lock_crt();
1976         viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1977         viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga);
1978
1979         /* load FIFO */
1980         if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
1981             && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
1982                 viafb_load_FIFO_reg(set_iga, h_addr, v_addr);
1983
1984         pll_D_N = viafb_get_clk_value(crt_table[index].clk);
1985         DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);
1986         viafb_set_vclock(pll_D_N, set_iga);
1987
1988 }
1989
1990 void viafb_init_chip_info(int chip_type)
1991 {
1992         init_gfx_chip_info(chip_type);
1993         init_tmds_chip_info();
1994         init_lvds_chip_info();
1995
1996         viaparinfo->crt_setting_info->iga_path = IGA1;
1997         viaparinfo->crt_setting_info->refresh_rate = viafb_refresh;
1998
1999         /*Set IGA path for each device */
2000         viafb_set_iga_path();
2001
2002         viaparinfo->lvds_setting_info->display_method = viafb_lcd_dsp_method;
2003         viaparinfo->lvds_setting_info->lcd_mode = viafb_lcd_mode;
2004         viaparinfo->lvds_setting_info2->display_method =
2005                 viaparinfo->lvds_setting_info->display_method;
2006         viaparinfo->lvds_setting_info2->lcd_mode =
2007                 viaparinfo->lvds_setting_info->lcd_mode;
2008 }
2009
2010 void viafb_update_device_setting(int hres, int vres,
2011         int bpp, int vmode_refresh, int flag)
2012 {
2013         if (flag == 0) {
2014                 viaparinfo->crt_setting_info->h_active = hres;
2015                 viaparinfo->crt_setting_info->v_active = vres;
2016                 viaparinfo->crt_setting_info->bpp = bpp;
2017                 viaparinfo->crt_setting_info->refresh_rate =
2018                         vmode_refresh;
2019
2020                 viaparinfo->tmds_setting_info->h_active = hres;
2021                 viaparinfo->tmds_setting_info->v_active = vres;
2022
2023                 viaparinfo->lvds_setting_info->h_active = hres;
2024                 viaparinfo->lvds_setting_info->v_active = vres;
2025                 viaparinfo->lvds_setting_info->bpp = bpp;
2026                 viaparinfo->lvds_setting_info->refresh_rate =
2027                         vmode_refresh;
2028                 viaparinfo->lvds_setting_info2->h_active = hres;
2029                 viaparinfo->lvds_setting_info2->v_active = vres;
2030                 viaparinfo->lvds_setting_info2->bpp = bpp;
2031                 viaparinfo->lvds_setting_info2->refresh_rate =
2032                         vmode_refresh;
2033         } else {
2034
2035                 if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
2036                         viaparinfo->tmds_setting_info->h_active = hres;
2037                         viaparinfo->tmds_setting_info->v_active = vres;
2038                 }
2039
2040                 if (viaparinfo->lvds_setting_info->iga_path == IGA2) {
2041                         viaparinfo->lvds_setting_info->h_active = hres;
2042                         viaparinfo->lvds_setting_info->v_active = vres;
2043                         viaparinfo->lvds_setting_info->bpp = bpp;
2044                         viaparinfo->lvds_setting_info->refresh_rate =
2045                                 vmode_refresh;
2046                 }
2047                 if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) {
2048                         viaparinfo->lvds_setting_info2->h_active = hres;
2049                         viaparinfo->lvds_setting_info2->v_active = vres;
2050                         viaparinfo->lvds_setting_info2->bpp = bpp;
2051                         viaparinfo->lvds_setting_info2->refresh_rate =
2052                                 vmode_refresh;
2053                 }
2054         }
2055 }
2056
2057 static void init_gfx_chip_info(int chip_type)
2058 {
2059         u8 tmp;
2060
2061         viaparinfo->chip_info->gfx_chip_name = chip_type;
2062
2063         /* Check revision of CLE266 Chip */
2064         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
2065                 /* CR4F only define in CLE266.CX chip */
2066                 tmp = viafb_read_reg(VIACR, CR4F);
2067                 viafb_write_reg(CR4F, VIACR, 0x55);
2068                 if (viafb_read_reg(VIACR, CR4F) != 0x55)
2069                         viaparinfo->chip_info->gfx_chip_revision =
2070                         CLE266_REVISION_AX;
2071                 else
2072                         viaparinfo->chip_info->gfx_chip_revision =
2073                         CLE266_REVISION_CX;
2074                 /* restore orignal CR4F value */
2075                 viafb_write_reg(CR4F, VIACR, tmp);
2076         }
2077
2078         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
2079                 tmp = viafb_read_reg(VIASR, SR43);
2080                 DEBUG_MSG(KERN_INFO "SR43:%X\n", tmp);
2081                 if (tmp & 0x02) {
2082                         viaparinfo->chip_info->gfx_chip_revision =
2083                                 CX700_REVISION_700M2;
2084                 } else if (tmp & 0x40) {
2085                         viaparinfo->chip_info->gfx_chip_revision =
2086                                 CX700_REVISION_700M;
2087                 } else {
2088                         viaparinfo->chip_info->gfx_chip_revision =
2089                                 CX700_REVISION_700;
2090                 }
2091         }
2092
2093         /* Determine which 2D engine we have */
2094         switch (viaparinfo->chip_info->gfx_chip_name) {
2095         case UNICHROME_VX800:
2096         case UNICHROME_VX855:
2097                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_M1;
2098                 break;
2099         case UNICHROME_K8M890:
2100         case UNICHROME_P4M900:
2101                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H5;
2102                 break;
2103         default:
2104                 viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H2;
2105                 break;
2106         }
2107 }
2108
2109 static void init_tmds_chip_info(void)
2110 {
2111         viafb_tmds_trasmitter_identify();
2112
2113         if (INTERFACE_NONE == viaparinfo->chip_info->tmds_chip_info.
2114                 output_interface) {
2115                 switch (viaparinfo->chip_info->gfx_chip_name) {
2116                 case UNICHROME_CX700:
2117                         {
2118                                 /* we should check support by hardware layout.*/
2119                                 if ((viafb_display_hardware_layout ==
2120                                      HW_LAYOUT_DVI_ONLY)
2121                                     || (viafb_display_hardware_layout ==
2122                                         HW_LAYOUT_LCD_DVI)) {
2123                                         viaparinfo->chip_info->tmds_chip_info.
2124                                             output_interface = INTERFACE_TMDS;
2125                                 } else {
2126                                         viaparinfo->chip_info->tmds_chip_info.
2127                                                 output_interface =
2128                                                 INTERFACE_NONE;
2129                                 }
2130                                 break;
2131                         }
2132                 case UNICHROME_K8M890:
2133                 case UNICHROME_P4M900:
2134                 case UNICHROME_P4M890:
2135                         /* TMDS on PCIE, we set DFPLOW as default. */
2136                         viaparinfo->chip_info->tmds_chip_info.output_interface =
2137                             INTERFACE_DFP_LOW;
2138                         break;
2139                 default:
2140                         {
2141                                 /* set DVP1 default for DVI */
2142                                 viaparinfo->chip_info->tmds_chip_info
2143                                 .output_interface = INTERFACE_DVP1;
2144                         }
2145                 }
2146         }
2147
2148         DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n",
2149                   viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
2150         viafb_init_dvi_size(&viaparinfo->shared->chip_info.tmds_chip_info,
2151                 &viaparinfo->shared->tmds_setting_info);
2152 }
2153
2154 static void init_lvds_chip_info(void)
2155 {
2156         viafb_lvds_trasmitter_identify();
2157         viafb_init_lcd_size();
2158         viafb_init_lvds_output_interface(&viaparinfo->chip_info->lvds_chip_info,
2159                                    viaparinfo->lvds_setting_info);
2160         if (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) {
2161                 viafb_init_lvds_output_interface(&viaparinfo->chip_info->
2162                         lvds_chip_info2, viaparinfo->lvds_setting_info2);
2163         }
2164         /*If CX700,two singel LCD, we need to reassign
2165            LCD interface to different LVDS port */
2166         if ((UNICHROME_CX700 == viaparinfo->chip_info->gfx_chip_name)
2167             && (HW_LAYOUT_LCD1_LCD2 == viafb_display_hardware_layout)) {
2168                 if ((INTEGRATED_LVDS == viaparinfo->chip_info->lvds_chip_info.
2169                         lvds_chip_name) && (INTEGRATED_LVDS ==
2170                         viaparinfo->chip_info->
2171                         lvds_chip_info2.lvds_chip_name)) {
2172                         viaparinfo->chip_info->lvds_chip_info.output_interface =
2173                                 INTERFACE_LVDS0;
2174                         viaparinfo->chip_info->lvds_chip_info2.
2175                                 output_interface =
2176                             INTERFACE_LVDS1;
2177                 }
2178         }
2179
2180         DEBUG_MSG(KERN_INFO "LVDS Chip = %d\n",
2181                   viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
2182         DEBUG_MSG(KERN_INFO "LVDS1 output_interface = %d\n",
2183                   viaparinfo->chip_info->lvds_chip_info.output_interface);
2184         DEBUG_MSG(KERN_INFO "LVDS2 output_interface = %d\n",
2185                   viaparinfo->chip_info->lvds_chip_info.output_interface);
2186 }
2187
2188 void viafb_init_dac(int set_iga)
2189 {
2190         int i;
2191         u8 tmp;
2192
2193         if (set_iga == IGA1) {
2194                 /* access Primary Display's LUT */
2195                 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2196                 /* turn off LCK */
2197                 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);
2198                 for (i = 0; i < 256; i++) {
2199                         write_dac_reg(i, palLUT_table[i].red,
2200                                       palLUT_table[i].green,
2201                                       palLUT_table[i].blue);
2202                 }
2203                 /* turn on LCK */
2204                 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);
2205         } else {
2206                 tmp = viafb_read_reg(VIACR, CR6A);
2207                 /* access Secondary Display's LUT */
2208                 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);
2209                 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
2210                 for (i = 0; i < 256; i++) {
2211                         write_dac_reg(i, palLUT_table[i].red,
2212                                       palLUT_table[i].green,
2213                                       palLUT_table[i].blue);
2214                 }
2215                 /* set IGA1 DAC for default */
2216                 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2217                 viafb_write_reg(CR6A, VIACR, tmp);
2218         }
2219 }
2220
2221 static void device_screen_off(void)
2222 {
2223         /* turn off CRT screen (IGA1) */
2224         viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);
2225 }
2226
2227 static void device_screen_on(void)
2228 {
2229         /* turn on CRT screen (IGA1) */
2230         viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);
2231 }
2232
2233 static void set_display_channel(void)
2234 {
2235         /*If viafb_LCD2_ON, on cx700, internal lvds's information
2236         is keeped on lvds_setting_info2 */
2237         if (viafb_LCD2_ON &&
2238                 viaparinfo->lvds_setting_info2->device_lcd_dualedge) {
2239                 /* For dual channel LCD: */
2240                 /* Set to Dual LVDS channel. */
2241                 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2242         } else if (viafb_LCD_ON && viafb_DVI_ON) {
2243                 /* For LCD+DFP: */
2244                 /* Set to LVDS1 + TMDS channel. */
2245                 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);
2246         } else if (viafb_DVI_ON) {
2247                 /* Set to single TMDS channel. */
2248                 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);
2249         } else if (viafb_LCD_ON) {
2250                 if (viaparinfo->lvds_setting_info->device_lcd_dualedge) {
2251                         /* For dual channel LCD: */
2252                         /* Set to Dual LVDS channel. */
2253                         viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2254                 } else {
2255                         /* Set to LVDS0 + LVDS1 channel. */
2256                         viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);
2257                 }
2258         }
2259 }
2260
2261 int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2262         struct VideoModeTable *vmode_tbl1, int video_bpp1)
2263 {
2264         int i, j;
2265         int port;
2266         u8 value, index, mask;
2267         struct crt_mode_table *crt_timing;
2268         struct crt_mode_table *crt_timing1 = NULL;
2269
2270         device_screen_off();
2271         crt_timing = vmode_tbl->crtc;
2272
2273         if (viafb_SAMM_ON == 1) {
2274                 crt_timing1 = vmode_tbl1->crtc;
2275         }
2276
2277         inb(VIAStatus);
2278         outb(0x00, VIAAR);
2279
2280         /* Write Common Setting for Video Mode */
2281         switch (viaparinfo->chip_info->gfx_chip_name) {
2282         case UNICHROME_CLE266:
2283                 viafb_write_regx(CLE266_ModeXregs, NUM_TOTAL_CLE266_ModeXregs);
2284                 break;
2285
2286         case UNICHROME_K400:
2287                 viafb_write_regx(KM400_ModeXregs, NUM_TOTAL_KM400_ModeXregs);
2288                 break;
2289
2290         case UNICHROME_K800:
2291         case UNICHROME_PM800:
2292                 viafb_write_regx(CN400_ModeXregs, NUM_TOTAL_CN400_ModeXregs);
2293                 break;
2294
2295         case UNICHROME_CN700:
2296         case UNICHROME_K8M890:
2297         case UNICHROME_P4M890:
2298         case UNICHROME_P4M900:
2299                 viafb_write_regx(CN700_ModeXregs, NUM_TOTAL_CN700_ModeXregs);
2300                 break;
2301
2302         case UNICHROME_CX700:
2303         case UNICHROME_VX800:
2304                 viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs);
2305                 break;
2306
2307         case UNICHROME_VX855:
2308                 viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs);
2309                 break;
2310         }
2311
2312         device_off();
2313
2314         /* Fill VPIT Parameters */
2315         /* Write Misc Register */
2316         outb(VPIT.Misc, VIA_MISC_REG_WRITE);
2317
2318         /* Write Sequencer */
2319         for (i = 1; i <= StdSR; i++)
2320                 via_write_reg(VIASR, i, VPIT.SR[i - 1]);
2321
2322         viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2);
2323         viafb_set_iga_path();
2324
2325         /* Write CRTC */
2326         viafb_fill_crtc_timing(crt_timing, vmode_tbl, video_bpp / 8, IGA1);
2327
2328         /* Write Graphic Controller */
2329         for (i = 0; i < StdGR; i++)
2330                 via_write_reg(VIAGR, i, VPIT.GR[i]);
2331
2332         /* Write Attribute Controller */
2333         for (i = 0; i < StdAR; i++) {
2334                 inb(VIAStatus);
2335                 outb(i, VIAAR);
2336                 outb(VPIT.AR[i], VIAAR);
2337         }
2338
2339         inb(VIAStatus);
2340         outb(0x20, VIAAR);
2341
2342         /* Update Patch Register */
2343
2344         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266
2345             || viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400)
2346             && vmode_tbl->crtc[0].crtc.hor_addr == 1024
2347             && vmode_tbl->crtc[0].crtc.ver_addr == 768) {
2348                 for (j = 0; j < res_patch_table[0].table_length; j++) {
2349                         index = res_patch_table[0].io_reg_table[j].index;
2350                         port = res_patch_table[0].io_reg_table[j].port;
2351                         value = res_patch_table[0].io_reg_table[j].value;
2352                         mask = res_patch_table[0].io_reg_table[j].mask;
2353                         viafb_write_reg_mask(index, port, value, mask);
2354                 }
2355         }
2356
2357         via_set_primary_pitch(viafbinfo->fix.line_length);
2358         via_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length
2359                 : viafbinfo->fix.line_length);
2360         via_set_primary_color_depth(viaparinfo->depth);
2361         via_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth
2362                 : viaparinfo->depth);
2363         /* Update Refresh Rate Setting */
2364
2365         /* Clear On Screen */
2366
2367         /* CRT set mode */
2368         if (viafb_CRT_ON) {
2369                 if (viafb_SAMM_ON && (viaparinfo->crt_setting_info->iga_path ==
2370                         IGA2)) {
2371                         viafb_fill_crtc_timing(crt_timing1, vmode_tbl1,
2372                                 video_bpp1 / 8,
2373                                 viaparinfo->crt_setting_info->iga_path);
2374                 } else {
2375                         viafb_fill_crtc_timing(crt_timing, vmode_tbl,
2376                                 video_bpp / 8,
2377                                 viaparinfo->crt_setting_info->iga_path);
2378                 }
2379
2380                 /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode
2381                 to 8 alignment (1368),there is several pixels (2 pixels)
2382                 on right side of screen. */
2383                 if (vmode_tbl->crtc[0].crtc.hor_addr % 8) {
2384                         viafb_unlock_crt();
2385                         viafb_write_reg(CR02, VIACR,
2386                                 viafb_read_reg(VIACR, CR02) - 1);
2387                         viafb_lock_crt();
2388                 }
2389
2390                 viafb_set_output_path(DEVICE_CRT,
2391                         viaparinfo->crt_setting_info->iga_path, 0);
2392         }
2393
2394         if (viafb_DVI_ON) {
2395                 if (viafb_SAMM_ON &&
2396                         (viaparinfo->tmds_setting_info->iga_path == IGA2)) {
2397                         viafb_dvi_set_mode(viafb_get_mode
2398                                      (viaparinfo->tmds_setting_info->h_active,
2399                                       viaparinfo->tmds_setting_info->
2400                                       v_active),
2401                                      video_bpp1, viaparinfo->
2402                                      tmds_setting_info->iga_path);
2403                 } else {
2404                         viafb_dvi_set_mode(viafb_get_mode
2405                                      (viaparinfo->tmds_setting_info->h_active,
2406                                       viaparinfo->
2407                                       tmds_setting_info->v_active),
2408                                      video_bpp, viaparinfo->
2409                                      tmds_setting_info->iga_path);
2410                 }
2411
2412                 viafb_set_output_path(DEVICE_DVI,
2413                         viaparinfo->tmds_setting_info->iga_path,
2414                         viaparinfo->chip_info->tmds_chip_info.output_interface);
2415         }
2416
2417         if (viafb_LCD_ON) {
2418                 if (viafb_SAMM_ON &&
2419                         (viaparinfo->lvds_setting_info->iga_path == IGA2)) {
2420                         viaparinfo->lvds_setting_info->bpp = video_bpp1;
2421                         viafb_lcd_set_mode(crt_timing1, viaparinfo->
2422                                 lvds_setting_info,
2423                                      &viaparinfo->chip_info->lvds_chip_info);
2424                 } else {
2425                         /* IGA1 doesn't have LCD scaling, so set it center. */
2426                         if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
2427                                 viaparinfo->lvds_setting_info->display_method =
2428                                     LCD_CENTERING;
2429                         }
2430                         viaparinfo->lvds_setting_info->bpp = video_bpp;
2431                         viafb_lcd_set_mode(crt_timing, viaparinfo->
2432                                 lvds_setting_info,
2433                                      &viaparinfo->chip_info->lvds_chip_info);
2434                 }
2435
2436                 viafb_set_output_path(DEVICE_LCD,
2437                         viaparinfo->lvds_setting_info->iga_path,
2438                         viaparinfo->chip_info->
2439                         lvds_chip_info.output_interface);
2440         }
2441         if (viafb_LCD2_ON) {
2442                 if (viafb_SAMM_ON &&
2443                         (viaparinfo->lvds_setting_info2->iga_path == IGA2)) {
2444                         viaparinfo->lvds_setting_info2->bpp = video_bpp1;
2445                         viafb_lcd_set_mode(crt_timing1, viaparinfo->
2446                                 lvds_setting_info2,
2447                                      &viaparinfo->chip_info->lvds_chip_info2);
2448                 } else {
2449                         /* IGA1 doesn't have LCD scaling, so set it center. */
2450                         if (viaparinfo->lvds_setting_info2->iga_path == IGA1) {
2451                                 viaparinfo->lvds_setting_info2->display_method =
2452                                     LCD_CENTERING;
2453                         }
2454                         viaparinfo->lvds_setting_info2->bpp = video_bpp;
2455                         viafb_lcd_set_mode(crt_timing, viaparinfo->
2456                                 lvds_setting_info2,
2457                                      &viaparinfo->chip_info->lvds_chip_info2);
2458                 }
2459
2460                 viafb_set_output_path(DEVICE_LCD,
2461                         viaparinfo->lvds_setting_info2->iga_path,
2462                         viaparinfo->chip_info->
2463                         lvds_chip_info2.output_interface);
2464         }
2465
2466         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
2467             && (viafb_LCD_ON || viafb_DVI_ON))
2468                 set_display_channel();
2469
2470         /* If set mode normally, save resolution information for hot-plug . */
2471         if (!viafb_hotplug) {
2472                 viafb_hotplug_Xres = vmode_tbl->crtc[0].crtc.hor_addr;
2473                 viafb_hotplug_Yres = vmode_tbl->crtc[0].crtc.ver_addr;
2474                 viafb_hotplug_bpp = video_bpp;
2475                 viafb_hotplug_refresh = viafb_refresh;
2476
2477                 if (viafb_DVI_ON)
2478                         viafb_DeviceStatus = DVI_Device;
2479                 else
2480                         viafb_DeviceStatus = CRT_Device;
2481         }
2482         device_on();
2483
2484         if (viafb_SAMM_ON == 1)
2485                 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
2486
2487         device_screen_on();
2488         return 1;
2489 }
2490
2491 int viafb_get_pixclock(int hres, int vres, int vmode_refresh)
2492 {
2493         int i;
2494
2495         for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2496                 if ((hres == res_map_refresh_tbl[i].hres)
2497                     && (vres == res_map_refresh_tbl[i].vres)
2498                     && (vmode_refresh == res_map_refresh_tbl[i].vmode_refresh))
2499                         return res_map_refresh_tbl[i].pixclock;
2500         }
2501         return RES_640X480_60HZ_PIXCLOCK;
2502
2503 }
2504
2505 int viafb_get_refresh(int hres, int vres, u32 long_refresh)
2506 {
2507 #define REFRESH_TOLERANCE 3
2508         int i, nearest = -1, diff = REFRESH_TOLERANCE;
2509         for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2510                 if ((hres == res_map_refresh_tbl[i].hres)
2511                     && (vres == res_map_refresh_tbl[i].vres)
2512                     && (diff > (abs(long_refresh -
2513                     res_map_refresh_tbl[i].vmode_refresh)))) {
2514                         diff = abs(long_refresh - res_map_refresh_tbl[i].
2515                                 vmode_refresh);
2516                         nearest = i;
2517                 }
2518         }
2519 #undef REFRESH_TOLERANCE
2520         if (nearest > 0)
2521                 return res_map_refresh_tbl[nearest].vmode_refresh;
2522         return 60;
2523 }
2524
2525 static void device_off(void)
2526 {
2527         viafb_crt_disable();
2528         viafb_dvi_disable();
2529         viafb_lcd_disable();
2530 }
2531
2532 static void device_on(void)
2533 {
2534         if (viafb_CRT_ON == 1)
2535                 viafb_crt_enable();
2536         if (viafb_DVI_ON == 1)
2537                 viafb_dvi_enable();
2538         if (viafb_LCD_ON == 1)
2539                 viafb_lcd_enable();
2540 }
2541
2542 void viafb_crt_disable(void)
2543 {
2544         viafb_write_reg_mask(CR36, VIACR, BIT5 + BIT4, BIT5 + BIT4);
2545 }
2546
2547 void viafb_crt_enable(void)
2548 {
2549         viafb_write_reg_mask(CR36, VIACR, 0x0, BIT5 + BIT4);
2550 }
2551
2552 static void enable_second_display_channel(void)
2553 {
2554         /* to enable second display channel. */
2555         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2556         viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);
2557         viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2558 }
2559
2560 static void disable_second_display_channel(void)
2561 {
2562         /* to disable second display channel. */
2563         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2564         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7);
2565         viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2566 }
2567
2568
2569 void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
2570                                         *p_gfx_dpa_setting)
2571 {
2572         switch (output_interface) {
2573         case INTERFACE_DVP0:
2574                 {
2575                         /* DVP0 Clock Polarity and Adjust: */
2576                         viafb_write_reg_mask(CR96, VIACR,
2577                                        p_gfx_dpa_setting->DVP0, 0x0F);
2578
2579                         /* DVP0 Clock and Data Pads Driving: */
2580                         viafb_write_reg_mask(SR1E, VIASR,
2581                                        p_gfx_dpa_setting->DVP0ClockDri_S, BIT2);
2582                         viafb_write_reg_mask(SR2A, VIASR,
2583                                        p_gfx_dpa_setting->DVP0ClockDri_S1,
2584                                        BIT4);
2585                         viafb_write_reg_mask(SR1B, VIASR,
2586                                        p_gfx_dpa_setting->DVP0DataDri_S, BIT1);
2587                         viafb_write_reg_mask(SR2A, VIASR,
2588                                        p_gfx_dpa_setting->DVP0DataDri_S1, BIT5);
2589                         break;
2590                 }
2591
2592         case INTERFACE_DVP1:
2593                 {
2594                         /* DVP1 Clock Polarity and Adjust: */
2595                         viafb_write_reg_mask(CR9B, VIACR,
2596                                        p_gfx_dpa_setting->DVP1, 0x0F);
2597
2598                         /* DVP1 Clock and Data Pads Driving: */
2599                         viafb_write_reg_mask(SR65, VIASR,
2600                                        p_gfx_dpa_setting->DVP1Driving, 0x0F);
2601                         break;
2602                 }
2603
2604         case INTERFACE_DFP_HIGH:
2605                 {
2606                         viafb_write_reg_mask(CR97, VIACR,
2607                                        p_gfx_dpa_setting->DFPHigh, 0x0F);
2608                         break;
2609                 }
2610
2611         case INTERFACE_DFP_LOW:
2612                 {
2613                         viafb_write_reg_mask(CR99, VIACR,
2614                                        p_gfx_dpa_setting->DFPLow, 0x0F);
2615                         break;
2616                 }
2617
2618         case INTERFACE_DFP:
2619                 {
2620                         viafb_write_reg_mask(CR97, VIACR,
2621                                        p_gfx_dpa_setting->DFPHigh, 0x0F);
2622                         viafb_write_reg_mask(CR99, VIACR,
2623                                        p_gfx_dpa_setting->DFPLow, 0x0F);
2624                         break;
2625                 }
2626         }
2627 }
2628
2629 /*According var's xres, yres fill var's other timing information*/
2630 void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
2631         struct VideoModeTable *vmode_tbl)
2632 {
2633         struct crt_mode_table *crt_timing = NULL;
2634         struct display_timing crt_reg;
2635         int i = 0, index = 0;
2636         crt_timing = vmode_tbl->crtc;
2637         for (i = 0; i < vmode_tbl->mode_array; i++) {
2638                 index = i;
2639                 if (crt_timing[i].refresh_rate == refresh)
2640                         break;
2641         }
2642
2643         crt_reg = crt_timing[index].crtc;
2644         var->pixclock = viafb_get_pixclock(var->xres, var->yres, refresh);
2645         var->left_margin =
2646             crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end);
2647         var->right_margin = crt_reg.hor_sync_start - crt_reg.hor_addr;
2648         var->hsync_len = crt_reg.hor_sync_end;
2649         var->upper_margin =
2650             crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end);
2651         var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr;
2652         var->vsync_len = crt_reg.ver_sync_end;
2653 }