2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 #define viafb_read_reg(p, i) via_read_reg(p, i)
30 #define viafb_write_reg(i, p, d) via_write_reg(p, i, d)
31 #define viafb_write_reg_mask(i, p, d, m) via_write_reg_mask(p, i, d, m)
33 /***************************************************
34 * Definition IGA1 Design Method of CRTC Registers *
35 ****************************************************/
36 #define IGA1_HOR_TOTAL_FORMULA(x) (((x)/8)-5)
37 #define IGA1_HOR_ADDR_FORMULA(x) (((x)/8)-1)
38 #define IGA1_HOR_BLANK_START_FORMULA(x) (((x)/8)-1)
39 #define IGA1_HOR_BLANK_END_FORMULA(x, y) (((x+y)/8)-1)
40 #define IGA1_HOR_SYNC_START_FORMULA(x) ((x)/8)
41 #define IGA1_HOR_SYNC_END_FORMULA(x, y) ((x+y)/8)
43 #define IGA1_VER_TOTAL_FORMULA(x) ((x)-2)
44 #define IGA1_VER_ADDR_FORMULA(x) ((x)-1)
45 #define IGA1_VER_BLANK_START_FORMULA(x) ((x)-1)
46 #define IGA1_VER_BLANK_END_FORMULA(x, y) ((x+y)-1)
47 #define IGA1_VER_SYNC_START_FORMULA(x) ((x)-1)
48 #define IGA1_VER_SYNC_END_FORMULA(x, y) ((x+y)-1)
50 /***************************************************
51 ** Definition IGA2 Design Method of CRTC Registers *
52 ****************************************************/
53 #define IGA2_HOR_TOTAL_FORMULA(x) ((x)-1)
54 #define IGA2_HOR_ADDR_FORMULA(x) ((x)-1)
55 #define IGA2_HOR_BLANK_START_FORMULA(x) ((x)-1)
56 #define IGA2_HOR_BLANK_END_FORMULA(x, y) ((x+y)-1)
57 #define IGA2_HOR_SYNC_START_FORMULA(x) ((x)-1)
58 #define IGA2_HOR_SYNC_END_FORMULA(x, y) ((x+y)-1)
60 #define IGA2_VER_TOTAL_FORMULA(x) ((x)-1)
61 #define IGA2_VER_ADDR_FORMULA(x) ((x)-1)
62 #define IGA2_VER_BLANK_START_FORMULA(x) ((x)-1)
63 #define IGA2_VER_BLANK_END_FORMULA(x, y) ((x+y)-1)
64 #define IGA2_VER_SYNC_START_FORMULA(x) ((x)-1)
65 #define IGA2_VER_SYNC_END_FORMULA(x, y) ((x+y)-1)
67 /**********************************************************/
68 /* Definition IGA2 Design Method of CRTC Shadow Registers */
69 /**********************************************************/
70 #define IGA2_HOR_TOTAL_SHADOW_FORMULA(x) ((x/8)-5)
71 #define IGA2_HOR_BLANK_END_SHADOW_FORMULA(x, y) (((x+y)/8)-1)
72 #define IGA2_VER_TOTAL_SHADOW_FORMULA(x) ((x)-2)
73 #define IGA2_VER_ADDR_SHADOW_FORMULA(x) ((x)-1)
74 #define IGA2_VER_BLANK_START_SHADOW_FORMULA(x) ((x)-1)
75 #define IGA2_VER_BLANK_END_SHADOW_FORMULA(x, y) ((x+y)-1)
76 #define IGA2_VER_SYNC_START_SHADOW_FORMULA(x) (x)
77 #define IGA2_VER_SYNC_END_SHADOW_FORMULA(x, y) (x+y)
79 /* Define Register Number for IGA1 CRTC Timing */
81 /* location: {CR00,0,7},{CR36,3,3} */
82 #define IGA1_HOR_TOTAL_REG_NUM 2
83 /* location: {CR01,0,7} */
84 #define IGA1_HOR_ADDR_REG_NUM 1
85 /* location: {CR02,0,7} */
86 #define IGA1_HOR_BLANK_START_REG_NUM 1
87 /* location: {CR03,0,4},{CR05,7,7},{CR33,5,5} */
88 #define IGA1_HOR_BLANK_END_REG_NUM 3
89 /* location: {CR04,0,7},{CR33,4,4} */
90 #define IGA1_HOR_SYNC_START_REG_NUM 2
91 /* location: {CR05,0,4} */
92 #define IGA1_HOR_SYNC_END_REG_NUM 1
93 /* location: {CR06,0,7},{CR07,0,0},{CR07,5,5},{CR35,0,0} */
94 #define IGA1_VER_TOTAL_REG_NUM 4
95 /* location: {CR12,0,7},{CR07,1,1},{CR07,6,6},{CR35,2,2} */
96 #define IGA1_VER_ADDR_REG_NUM 4
97 /* location: {CR15,0,7},{CR07,3,3},{CR09,5,5},{CR35,3,3} */
98 #define IGA1_VER_BLANK_START_REG_NUM 4
99 /* location: {CR16,0,7} */
100 #define IGA1_VER_BLANK_END_REG_NUM 1
101 /* location: {CR10,0,7},{CR07,2,2},{CR07,7,7},{CR35,1,1} */
102 #define IGA1_VER_SYNC_START_REG_NUM 4
103 /* location: {CR11,0,3} */
104 #define IGA1_VER_SYNC_END_REG_NUM 1
106 /* Define Register Number for IGA2 Shadow CRTC Timing */
108 /* location: {CR6D,0,7},{CR71,3,3} */
109 #define IGA2_SHADOW_HOR_TOTAL_REG_NUM 2
110 /* location: {CR6E,0,7} */
111 #define IGA2_SHADOW_HOR_BLANK_END_REG_NUM 1
112 /* location: {CR6F,0,7},{CR71,0,2} */
113 #define IGA2_SHADOW_VER_TOTAL_REG_NUM 2
114 /* location: {CR70,0,7},{CR71,4,6} */
115 #define IGA2_SHADOW_VER_ADDR_REG_NUM 2
116 /* location: {CR72,0,7},{CR74,4,6} */
117 #define IGA2_SHADOW_VER_BLANK_START_REG_NUM 2
118 /* location: {CR73,0,7},{CR74,0,2} */
119 #define IGA2_SHADOW_VER_BLANK_END_REG_NUM 2
120 /* location: {CR75,0,7},{CR76,4,6} */
121 #define IGA2_SHADOW_VER_SYNC_START_REG_NUM 2
122 /* location: {CR76,0,3} */
123 #define IGA2_SHADOW_VER_SYNC_END_REG_NUM 1
125 /* Define Register Number for IGA2 CRTC Timing */
127 /* location: {CR50,0,7},{CR55,0,3} */
128 #define IGA2_HOR_TOTAL_REG_NUM 2
129 /* location: {CR51,0,7},{CR55,4,6} */
130 #define IGA2_HOR_ADDR_REG_NUM 2
131 /* location: {CR52,0,7},{CR54,0,2} */
132 #define IGA2_HOR_BLANK_START_REG_NUM 2
133 /* location: CLE266: {CR53,0,7},{CR54,3,5} => CLE266's CR5D[6]
134 is reserved, so it may have problem to set 1600x1200 on IGA2. */
135 /* Others: {CR53,0,7},{CR54,3,5},{CR5D,6,6} */
136 #define IGA2_HOR_BLANK_END_REG_NUM 3
137 /* location: {CR56,0,7},{CR54,6,7},{CR5C,7,7} */
138 /* VT3314 and Later: {CR56,0,7},{CR54,6,7},{CR5C,7,7}, {CR5D,7,7} */
139 #define IGA2_HOR_SYNC_START_REG_NUM 4
141 /* location: {CR57,0,7},{CR5C,6,6} */
142 #define IGA2_HOR_SYNC_END_REG_NUM 2
143 /* location: {CR58,0,7},{CR5D,0,2} */
144 #define IGA2_VER_TOTAL_REG_NUM 2
145 /* location: {CR59,0,7},{CR5D,3,5} */
146 #define IGA2_VER_ADDR_REG_NUM 2
147 /* location: {CR5A,0,7},{CR5C,0,2} */
148 #define IGA2_VER_BLANK_START_REG_NUM 2
149 /* location: {CR5E,0,7},{CR5C,3,5} */
150 #define IGA2_VER_BLANK_END_REG_NUM 2
151 /* location: {CR5E,0,7},{CR5F,5,7} */
152 #define IGA2_VER_SYNC_START_REG_NUM 2
153 /* location: {CR5F,0,4} */
154 #define IGA2_VER_SYNC_END_REG_NUM 1
156 /* Define Fetch Count Register*/
158 /* location: {SR1C,0,7},{SR1D,0,1} */
159 #define IGA1_FETCH_COUNT_REG_NUM 2
160 /* 16 bytes alignment. */
161 #define IGA1_FETCH_COUNT_ALIGN_BYTE 16
162 /* x: H resolution, y: color depth */
163 #define IGA1_FETCH_COUNT_PATCH_VALUE 4
164 #define IGA1_FETCH_COUNT_FORMULA(x, y) \
165 (((x*y)/IGA1_FETCH_COUNT_ALIGN_BYTE) + IGA1_FETCH_COUNT_PATCH_VALUE)
167 /* location: {CR65,0,7},{CR67,2,3} */
168 #define IGA2_FETCH_COUNT_REG_NUM 2
169 #define IGA2_FETCH_COUNT_ALIGN_BYTE 16
170 #define IGA2_FETCH_COUNT_PATCH_VALUE 0
171 #define IGA2_FETCH_COUNT_FORMULA(x, y) \
172 (((x*y)/IGA2_FETCH_COUNT_ALIGN_BYTE) + IGA2_FETCH_COUNT_PATCH_VALUE)
176 /* location: {CR0C,0,7},{CR0D,0,7},{CR34,0,7},{CR48,0,1} */
177 #define IGA1_STARTING_ADDR_REG_NUM 4
178 /* location: {CR62,1,7},{CR63,0,7},{CR64,0,7} */
179 #define IGA2_STARTING_ADDR_REG_NUM 3
181 /* Define Display OFFSET*/
182 /* These value are by HW suggested value*/
183 /* location: {SR17,0,7} */
184 #define K800_IGA1_FIFO_MAX_DEPTH 384
185 /* location: {SR16,0,5},{SR16,7,7} */
186 #define K800_IGA1_FIFO_THRESHOLD 328
187 /* location: {SR18,0,5},{SR18,7,7} */
188 #define K800_IGA1_FIFO_HIGH_THRESHOLD 296
189 /* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */
190 /* because HW only 5 bits */
191 #define K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 0
193 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
194 #define K800_IGA2_FIFO_MAX_DEPTH 384
195 /* location: {CR68,0,3},{CR95,4,6} */
196 #define K800_IGA2_FIFO_THRESHOLD 328
197 /* location: {CR92,0,3},{CR95,0,2} */
198 #define K800_IGA2_FIFO_HIGH_THRESHOLD 296
199 /* location: {CR94,0,6} */
200 #define K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128
202 /* location: {SR17,0,7} */
203 #define P880_IGA1_FIFO_MAX_DEPTH 192
204 /* location: {SR16,0,5},{SR16,7,7} */
205 #define P880_IGA1_FIFO_THRESHOLD 128
206 /* location: {SR18,0,5},{SR18,7,7} */
207 #define P880_IGA1_FIFO_HIGH_THRESHOLD 64
208 /* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */
209 /* because HW only 5 bits */
210 #define P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 0
212 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
213 #define P880_IGA2_FIFO_MAX_DEPTH 96
214 /* location: {CR68,0,3},{CR95,4,6} */
215 #define P880_IGA2_FIFO_THRESHOLD 64
216 /* location: {CR92,0,3},{CR95,0,2} */
217 #define P880_IGA2_FIFO_HIGH_THRESHOLD 32
218 /* location: {CR94,0,6} */
219 #define P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128
223 /* location: {SR17,0,7} */
224 #define CN700_IGA1_FIFO_MAX_DEPTH 96
225 /* location: {SR16,0,5},{SR16,7,7} */
226 #define CN700_IGA1_FIFO_THRESHOLD 80
227 /* location: {SR18,0,5},{SR18,7,7} */
228 #define CN700_IGA1_FIFO_HIGH_THRESHOLD 64
229 /* location: {SR22,0,4}. (128/4) =64, P800 must be set zero,
230 because HW only 5 bits */
231 #define CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 0
232 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
233 #define CN700_IGA2_FIFO_MAX_DEPTH 96
234 /* location: {CR68,0,3},{CR95,4,6} */
235 #define CN700_IGA2_FIFO_THRESHOLD 80
236 /* location: {CR92,0,3},{CR95,0,2} */
237 #define CN700_IGA2_FIFO_HIGH_THRESHOLD 32
238 /* location: {CR94,0,6} */
239 #define CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128
241 /* For VT3324, these values are suggested by HW */
242 /* location: {SR17,0,7} */
243 #define CX700_IGA1_FIFO_MAX_DEPTH 192
244 /* location: {SR16,0,5},{SR16,7,7} */
245 #define CX700_IGA1_FIFO_THRESHOLD 128
246 /* location: {SR18,0,5},{SR18,7,7} */
247 #define CX700_IGA1_FIFO_HIGH_THRESHOLD 128
248 /* location: {SR22,0,4} */
249 #define CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 124
251 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
252 #define CX700_IGA2_FIFO_MAX_DEPTH 96
253 /* location: {CR68,0,3},{CR95,4,6} */
254 #define CX700_IGA2_FIFO_THRESHOLD 64
255 /* location: {CR92,0,3},{CR95,0,2} */
256 #define CX700_IGA2_FIFO_HIGH_THRESHOLD 32
257 /* location: {CR94,0,6} */
258 #define CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128
261 /* location: {SR17,0,7} */
262 #define K8M890_IGA1_FIFO_MAX_DEPTH 360
263 /* location: {SR16,0,5},{SR16,7,7} */
264 #define K8M890_IGA1_FIFO_THRESHOLD 328
265 /* location: {SR18,0,5},{SR18,7,7} */
266 #define K8M890_IGA1_FIFO_HIGH_THRESHOLD 296
267 /* location: {SR22,0,4}. */
268 #define K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 124
270 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
271 #define K8M890_IGA2_FIFO_MAX_DEPTH 360
272 /* location: {CR68,0,3},{CR95,4,6} */
273 #define K8M890_IGA2_FIFO_THRESHOLD 328
274 /* location: {CR92,0,3},{CR95,0,2} */
275 #define K8M890_IGA2_FIFO_HIGH_THRESHOLD 296
276 /* location: {CR94,0,6} */
277 #define K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 124
280 /* location: {SR17,0,7} */
281 #define P4M890_IGA1_FIFO_MAX_DEPTH 96
282 /* location: {SR16,0,5},{SR16,7,7} */
283 #define P4M890_IGA1_FIFO_THRESHOLD 76
284 /* location: {SR18,0,5},{SR18,7,7} */
285 #define P4M890_IGA1_FIFO_HIGH_THRESHOLD 64
286 /* location: {SR22,0,4}. (32/4) =8 */
287 #define P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 32
288 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
289 #define P4M890_IGA2_FIFO_MAX_DEPTH 96
290 /* location: {CR68,0,3},{CR95,4,6} */
291 #define P4M890_IGA2_FIFO_THRESHOLD 76
292 /* location: {CR92,0,3},{CR95,0,2} */
293 #define P4M890_IGA2_FIFO_HIGH_THRESHOLD 64
294 /* location: {CR94,0,6} */
295 #define P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 32
298 /* location: {SR17,0,7} */
299 #define P4M900_IGA1_FIFO_MAX_DEPTH 96
300 /* location: {SR16,0,5},{SR16,7,7} */
301 #define P4M900_IGA1_FIFO_THRESHOLD 76
302 /* location: {SR18,0,5},{SR18,7,7} */
303 #define P4M900_IGA1_FIFO_HIGH_THRESHOLD 76
304 /* location: {SR22,0,4}. */
305 #define P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 32
306 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
307 #define P4M900_IGA2_FIFO_MAX_DEPTH 96
308 /* location: {CR68,0,3},{CR95,4,6} */
309 #define P4M900_IGA2_FIFO_THRESHOLD 76
310 /* location: {CR92,0,3},{CR95,0,2} */
311 #define P4M900_IGA2_FIFO_HIGH_THRESHOLD 76
312 /* location: {CR94,0,6} */
313 #define P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 32
315 /* For VT3353, these values are suggested by HW */
316 /* location: {SR17,0,7} */
317 #define VX800_IGA1_FIFO_MAX_DEPTH 192
318 /* location: {SR16,0,5},{SR16,7,7} */
319 #define VX800_IGA1_FIFO_THRESHOLD 152
320 /* location: {SR18,0,5},{SR18,7,7} */
321 #define VX800_IGA1_FIFO_HIGH_THRESHOLD 152
322 /* location: {SR22,0,4} */
323 #define VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 64
324 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
325 #define VX800_IGA2_FIFO_MAX_DEPTH 96
326 /* location: {CR68,0,3},{CR95,4,6} */
327 #define VX800_IGA2_FIFO_THRESHOLD 64
328 /* location: {CR92,0,3},{CR95,0,2} */
329 #define VX800_IGA2_FIFO_HIGH_THRESHOLD 32
330 /* location: {CR94,0,6} */
331 #define VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128
334 #define VX855_IGA1_FIFO_MAX_DEPTH 400
335 #define VX855_IGA1_FIFO_THRESHOLD 320
336 #define VX855_IGA1_FIFO_HIGH_THRESHOLD 320
337 #define VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 160
339 #define VX855_IGA2_FIFO_MAX_DEPTH 200
340 #define VX855_IGA2_FIFO_THRESHOLD 160
341 #define VX855_IGA2_FIFO_HIGH_THRESHOLD 160
342 #define VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 320
344 #define IGA1_FIFO_DEPTH_SELECT_REG_NUM 1
345 #define IGA1_FIFO_THRESHOLD_REG_NUM 2
346 #define IGA1_FIFO_HIGH_THRESHOLD_REG_NUM 2
347 #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM 1
349 #define IGA2_FIFO_DEPTH_SELECT_REG_NUM 3
350 #define IGA2_FIFO_THRESHOLD_REG_NUM 2
351 #define IGA2_FIFO_HIGH_THRESHOLD_REG_NUM 2
352 #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM 1
354 #define IGA1_FIFO_DEPTH_SELECT_FORMULA(x) ((x/2)-1)
355 #define IGA1_FIFO_THRESHOLD_FORMULA(x) (x/4)
356 #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x) (x/4)
357 #define IGA1_FIFO_HIGH_THRESHOLD_FORMULA(x) (x/4)
358 #define IGA2_FIFO_DEPTH_SELECT_FORMULA(x) (((x/2)/4)-1)
359 #define IGA2_FIFO_THRESHOLD_FORMULA(x) (x/4)
360 #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x) (x/4)
361 #define IGA2_FIFO_HIGH_THRESHOLD_FORMULA(x) (x/4)
363 /************************************************************************/
365 /************************************************************************/
367 /* 500 ms = 500000 us */
368 #define LCD_POWER_SEQ_TD0 500000
369 /* 50 ms = 50000 us */
370 #define LCD_POWER_SEQ_TD1 50000
372 #define LCD_POWER_SEQ_TD2 0
373 /* 210 ms = 210000 us */
374 #define LCD_POWER_SEQ_TD3 210000
375 /* 2^10 * (1/14.31818M) = 71.475 us (K400.revA) */
376 #define CLE266_POWER_SEQ_UNIT 71
377 /* 2^11 * (1/14.31818M) = 142.95 us (K400.revB) */
378 #define K800_POWER_SEQ_UNIT 142
379 /* 2^13 * (1/14.31818M) = 572.1 us */
380 #define P880_POWER_SEQ_UNIT 572
382 #define CLE266_POWER_SEQ_FORMULA(x) ((x)/CLE266_POWER_SEQ_UNIT)
383 #define K800_POWER_SEQ_FORMULA(x) ((x)/K800_POWER_SEQ_UNIT)
384 #define P880_POWER_SEQ_FORMULA(x) ((x)/P880_POWER_SEQ_UNIT)
386 /* location: {CR8B,0,7},{CR8F,0,3} */
387 #define LCD_POWER_SEQ_TD0_REG_NUM 2
388 /* location: {CR8C,0,7},{CR8F,4,7} */
389 #define LCD_POWER_SEQ_TD1_REG_NUM 2
390 /* location: {CR8D,0,7},{CR90,0,3} */
391 #define LCD_POWER_SEQ_TD2_REG_NUM 2
392 /* location: {CR8E,0,7},{CR90,4,7} */
393 #define LCD_POWER_SEQ_TD3_REG_NUM 2
395 /* LCD Scaling factor*/
396 /* x: indicate setting horizontal size*/
397 /* y: indicate panel horizontal size*/
399 /* Horizontal scaling factor 10 bits (2^10) */
400 #define CLE266_LCD_HOR_SCF_FORMULA(x, y) (((x-1)*1024)/(y-1))
401 /* Vertical scaling factor 10 bits (2^10) */
402 #define CLE266_LCD_VER_SCF_FORMULA(x, y) (((x-1)*1024)/(y-1))
403 /* Horizontal scaling factor 10 bits (2^12) */
404 #define K800_LCD_HOR_SCF_FORMULA(x, y) (((x-1)*4096)/(y-1))
405 /* Vertical scaling factor 10 bits (2^11) */
406 #define K800_LCD_VER_SCF_FORMULA(x, y) (((x-1)*2048)/(y-1))
408 /* location: {CR9F,0,1},{CR77,0,7},{CR79,4,5} */
409 #define LCD_HOR_SCALING_FACTOR_REG_NUM 3
410 /* location: {CR79,3,3},{CR78,0,7},{CR79,6,7} */
411 #define LCD_VER_SCALING_FACTOR_REG_NUM 3
412 /* location: {CR77,0,7},{CR79,4,5} */
413 #define LCD_HOR_SCALING_FACTOR_REG_NUM_CLE 2
414 /* location: {CR78,0,7},{CR79,6,7} */
415 #define LCD_VER_SCALING_FACTOR_REG_NUM_CLE 2
417 /************************************************
418 ***** Define IGA1 Display Timing *****
419 ************************************************/
426 /* IGA1 Horizontal Total */
427 struct iga1_hor_total {
429 struct io_register reg[IGA1_HOR_TOTAL_REG_NUM];
432 /* IGA1 Horizontal Addressable Video */
433 struct iga1_hor_addr {
435 struct io_register reg[IGA1_HOR_ADDR_REG_NUM];
438 /* IGA1 Horizontal Blank Start */
439 struct iga1_hor_blank_start {
441 struct io_register reg[IGA1_HOR_BLANK_START_REG_NUM];
444 /* IGA1 Horizontal Blank End */
445 struct iga1_hor_blank_end {
447 struct io_register reg[IGA1_HOR_BLANK_END_REG_NUM];
450 /* IGA1 Horizontal Sync Start */
451 struct iga1_hor_sync_start {
453 struct io_register reg[IGA1_HOR_SYNC_START_REG_NUM];
456 /* IGA1 Horizontal Sync End */
457 struct iga1_hor_sync_end {
459 struct io_register reg[IGA1_HOR_SYNC_END_REG_NUM];
462 /* IGA1 Vertical Total */
463 struct iga1_ver_total {
465 struct io_register reg[IGA1_VER_TOTAL_REG_NUM];
468 /* IGA1 Vertical Addressable Video */
469 struct iga1_ver_addr {
471 struct io_register reg[IGA1_VER_ADDR_REG_NUM];
474 /* IGA1 Vertical Blank Start */
475 struct iga1_ver_blank_start {
477 struct io_register reg[IGA1_VER_BLANK_START_REG_NUM];
480 /* IGA1 Vertical Blank End */
481 struct iga1_ver_blank_end {
483 struct io_register reg[IGA1_VER_BLANK_END_REG_NUM];
486 /* IGA1 Vertical Sync Start */
487 struct iga1_ver_sync_start {
489 struct io_register reg[IGA1_VER_SYNC_START_REG_NUM];
492 /* IGA1 Vertical Sync End */
493 struct iga1_ver_sync_end {
495 struct io_register reg[IGA1_VER_SYNC_END_REG_NUM];
498 /*****************************************************
499 ** Define IGA2 Shadow Display Timing ****
500 *****************************************************/
502 /* IGA2 Shadow Horizontal Total */
503 struct iga2_shadow_hor_total {
505 struct io_register reg[IGA2_SHADOW_HOR_TOTAL_REG_NUM];
508 /* IGA2 Shadow Horizontal Blank End */
509 struct iga2_shadow_hor_blank_end {
511 struct io_register reg[IGA2_SHADOW_HOR_BLANK_END_REG_NUM];
514 /* IGA2 Shadow Vertical Total */
515 struct iga2_shadow_ver_total {
517 struct io_register reg[IGA2_SHADOW_VER_TOTAL_REG_NUM];
520 /* IGA2 Shadow Vertical Addressable Video */
521 struct iga2_shadow_ver_addr {
523 struct io_register reg[IGA2_SHADOW_VER_ADDR_REG_NUM];
526 /* IGA2 Shadow Vertical Blank Start */
527 struct iga2_shadow_ver_blank_start {
529 struct io_register reg[IGA2_SHADOW_VER_BLANK_START_REG_NUM];
532 /* IGA2 Shadow Vertical Blank End */
533 struct iga2_shadow_ver_blank_end {
535 struct io_register reg[IGA2_SHADOW_VER_BLANK_END_REG_NUM];
538 /* IGA2 Shadow Vertical Sync Start */
539 struct iga2_shadow_ver_sync_start {
541 struct io_register reg[IGA2_SHADOW_VER_SYNC_START_REG_NUM];
544 /* IGA2 Shadow Vertical Sync End */
545 struct iga2_shadow_ver_sync_end {
547 struct io_register reg[IGA2_SHADOW_VER_SYNC_END_REG_NUM];
550 /*****************************************************
551 ** Define IGA2 Display Timing ****
552 ******************************************************/
554 /* IGA2 Horizontal Total */
555 struct iga2_hor_total {
557 struct io_register reg[IGA2_HOR_TOTAL_REG_NUM];
560 /* IGA2 Horizontal Addressable Video */
561 struct iga2_hor_addr {
563 struct io_register reg[IGA2_HOR_ADDR_REG_NUM];
566 /* IGA2 Horizontal Blank Start */
567 struct iga2_hor_blank_start {
569 struct io_register reg[IGA2_HOR_BLANK_START_REG_NUM];
572 /* IGA2 Horizontal Blank End */
573 struct iga2_hor_blank_end {
575 struct io_register reg[IGA2_HOR_BLANK_END_REG_NUM];
578 /* IGA2 Horizontal Sync Start */
579 struct iga2_hor_sync_start {
581 struct io_register reg[IGA2_HOR_SYNC_START_REG_NUM];
584 /* IGA2 Horizontal Sync End */
585 struct iga2_hor_sync_end {
587 struct io_register reg[IGA2_HOR_SYNC_END_REG_NUM];
590 /* IGA2 Vertical Total */
591 struct iga2_ver_total {
593 struct io_register reg[IGA2_VER_TOTAL_REG_NUM];
596 /* IGA2 Vertical Addressable Video */
597 struct iga2_ver_addr {
599 struct io_register reg[IGA2_VER_ADDR_REG_NUM];
602 /* IGA2 Vertical Blank Start */
603 struct iga2_ver_blank_start {
605 struct io_register reg[IGA2_VER_BLANK_START_REG_NUM];
608 /* IGA2 Vertical Blank End */
609 struct iga2_ver_blank_end {
611 struct io_register reg[IGA2_VER_BLANK_END_REG_NUM];
614 /* IGA2 Vertical Sync Start */
615 struct iga2_ver_sync_start {
617 struct io_register reg[IGA2_VER_SYNC_START_REG_NUM];
620 /* IGA2 Vertical Sync End */
621 struct iga2_ver_sync_end {
623 struct io_register reg[IGA2_VER_SYNC_END_REG_NUM];
626 /* IGA1 Fetch Count Register */
627 struct iga1_fetch_count {
629 struct io_register reg[IGA1_FETCH_COUNT_REG_NUM];
632 /* IGA2 Fetch Count Register */
633 struct iga2_fetch_count {
635 struct io_register reg[IGA2_FETCH_COUNT_REG_NUM];
639 struct iga1_fetch_count iga1_fetch_count_reg;
640 struct iga2_fetch_count iga2_fetch_count_reg;
643 /* Starting Address Register */
644 struct iga1_starting_addr {
646 struct io_register reg[IGA1_STARTING_ADDR_REG_NUM];
649 struct iga2_starting_addr {
651 struct io_register reg[IGA2_STARTING_ADDR_REG_NUM];
654 struct starting_addr {
655 struct iga1_starting_addr iga1_starting_addr_reg;
656 struct iga2_starting_addr iga2_starting_addr_reg;
659 /* LCD Power Sequence Timer */
660 struct lcd_pwd_seq_td0 {
662 struct io_register reg[LCD_POWER_SEQ_TD0_REG_NUM];
665 struct lcd_pwd_seq_td1 {
667 struct io_register reg[LCD_POWER_SEQ_TD1_REG_NUM];
670 struct lcd_pwd_seq_td2 {
672 struct io_register reg[LCD_POWER_SEQ_TD2_REG_NUM];
675 struct lcd_pwd_seq_td3 {
677 struct io_register reg[LCD_POWER_SEQ_TD3_REG_NUM];
680 struct _lcd_pwd_seq_timer {
681 struct lcd_pwd_seq_td0 td0;
682 struct lcd_pwd_seq_td1 td1;
683 struct lcd_pwd_seq_td2 td2;
684 struct lcd_pwd_seq_td3 td3;
687 /* LCD Scaling Factor */
688 struct _lcd_hor_scaling_factor {
690 struct io_register reg[LCD_HOR_SCALING_FACTOR_REG_NUM];
693 struct _lcd_ver_scaling_factor {
695 struct io_register reg[LCD_VER_SCALING_FACTOR_REG_NUM];
698 struct _lcd_scaling_factor {
699 struct _lcd_hor_scaling_factor lcd_hor_scaling_factor;
700 struct _lcd_ver_scaling_factor lcd_ver_scaling_factor;
717 struct lcd_pwd_seq_timer {
724 /* Display FIFO Relation Registers*/
725 struct iga1_fifo_depth_select {
727 struct io_register reg[IGA1_FIFO_DEPTH_SELECT_REG_NUM];
730 struct iga1_fifo_threshold_select {
732 struct io_register reg[IGA1_FIFO_THRESHOLD_REG_NUM];
735 struct iga1_fifo_high_threshold_select {
737 struct io_register reg[IGA1_FIFO_HIGH_THRESHOLD_REG_NUM];
740 struct iga1_display_queue_expire_num {
742 struct io_register reg[IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];
745 struct iga2_fifo_depth_select {
747 struct io_register reg[IGA2_FIFO_DEPTH_SELECT_REG_NUM];
750 struct iga2_fifo_threshold_select {
752 struct io_register reg[IGA2_FIFO_THRESHOLD_REG_NUM];
755 struct iga2_fifo_high_threshold_select {
757 struct io_register reg[IGA2_FIFO_HIGH_THRESHOLD_REG_NUM];
760 struct iga2_display_queue_expire_num {
762 struct io_register reg[IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];
765 struct fifo_depth_select {
766 struct iga1_fifo_depth_select iga1_fifo_depth_select_reg;
767 struct iga2_fifo_depth_select iga2_fifo_depth_select_reg;
770 struct fifo_threshold_select {
771 struct iga1_fifo_threshold_select iga1_fifo_threshold_select_reg;
772 struct iga2_fifo_threshold_select iga2_fifo_threshold_select_reg;
775 struct fifo_high_threshold_select {
776 struct iga1_fifo_high_threshold_select
777 iga1_fifo_high_threshold_select_reg;
778 struct iga2_fifo_high_threshold_select
779 iga2_fifo_high_threshold_select_reg;
782 struct display_queue_expire_num {
783 struct iga1_display_queue_expire_num
784 iga1_display_queue_expire_num_reg;
785 struct iga2_display_queue_expire_num
786 iga2_display_queue_expire_num_reg;
789 struct iga1_crtc_timing {
790 struct iga1_hor_total hor_total;
791 struct iga1_hor_addr hor_addr;
792 struct iga1_hor_blank_start hor_blank_start;
793 struct iga1_hor_blank_end hor_blank_end;
794 struct iga1_hor_sync_start hor_sync_start;
795 struct iga1_hor_sync_end hor_sync_end;
796 struct iga1_ver_total ver_total;
797 struct iga1_ver_addr ver_addr;
798 struct iga1_ver_blank_start ver_blank_start;
799 struct iga1_ver_blank_end ver_blank_end;
800 struct iga1_ver_sync_start ver_sync_start;
801 struct iga1_ver_sync_end ver_sync_end;
804 struct iga2_shadow_crtc_timing {
805 struct iga2_shadow_hor_total hor_total_shadow;
806 struct iga2_shadow_hor_blank_end hor_blank_end_shadow;
807 struct iga2_shadow_ver_total ver_total_shadow;
808 struct iga2_shadow_ver_addr ver_addr_shadow;
809 struct iga2_shadow_ver_blank_start ver_blank_start_shadow;
810 struct iga2_shadow_ver_blank_end ver_blank_end_shadow;
811 struct iga2_shadow_ver_sync_start ver_sync_start_shadow;
812 struct iga2_shadow_ver_sync_end ver_sync_end_shadow;
815 struct iga2_crtc_timing {
816 struct iga2_hor_total hor_total;
817 struct iga2_hor_addr hor_addr;
818 struct iga2_hor_blank_start hor_blank_start;
819 struct iga2_hor_blank_end hor_blank_end;
820 struct iga2_hor_sync_start hor_sync_start;
821 struct iga2_hor_sync_end hor_sync_end;
822 struct iga2_ver_total ver_total;
823 struct iga2_ver_addr ver_addr;
824 struct iga2_ver_blank_start ver_blank_start;
825 struct iga2_ver_blank_end ver_blank_end;
826 struct iga2_ver_sync_start ver_sync_start;
827 struct iga2_ver_sync_end ver_sync_end;
831 #define CLE266_FUNCTION3 0x3123
832 #define KM400_FUNCTION3 0x3205
833 #define CN400_FUNCTION2 0x2259
834 #define CN400_FUNCTION3 0x3259
835 /* support VT3314 chipset */
836 #define CN700_FUNCTION2 0x2314
837 #define CN700_FUNCTION3 0x3208
839 #define CX700_FUNCTION2 0x2324
840 #define CX700_FUNCTION3 0x3324
842 #define KM800_FUNCTION3 0x3204
844 #define KM890_FUNCTION3 0x3336
846 #define P4M890_FUNCTION3 0x3327
848 #define CN750_FUNCTION3 0x3208
850 #define P4M900_FUNCTION3 0x3364
852 #define VX800_FUNCTION3 0x3353
854 #define VX855_FUNCTION3 0x3409
856 #define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value)
864 struct pci_device_id_info {
870 extern unsigned int viafb_second_virtual_xres;
871 extern int viafb_SAMM_ON;
872 extern int viafb_dual_fb;
873 extern int viafb_LCD2_ON;
874 extern int viafb_LCD_ON;
875 extern int viafb_DVI_ON;
876 extern int viafb_hotplug;
878 void viafb_set_output_path(int device, int set_iga,
879 int output_interface);
881 void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
882 struct VideoModeTable *video_mode, int bpp_byte, int set_iga);
884 void viafb_set_vclock(u32 CLK, int set_iga);
885 void viafb_load_reg(int timing_value, int viafb_load_reg_num,
886 struct io_register *reg,
888 void viafb_crt_disable(void);
889 void viafb_crt_enable(void);
890 void init_ad9389(void);
891 /* Access I/O Function */
892 void viafb_lock_crt(void);
893 void viafb_unlock_crt(void);
894 void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga);
895 void viafb_write_regx(struct io_reg RegTable[], int ItemNum);
896 u32 viafb_get_clk_value(int clk);
897 void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active);
898 void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
901 int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
902 struct VideoModeTable *vmode_tbl1, int video_bpp1);
903 void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
904 struct VideoModeTable *vmode_tbl);
905 void viafb_init_chip_info(int chip_type);
906 void viafb_init_dac(int set_iga);
907 int viafb_get_pixclock(int hres, int vres, int vmode_refresh);
908 int viafb_get_refresh(int hres, int vres, u32 float_refresh);
909 void viafb_update_device_setting(int hres, int vres, int bpp,
910 int vmode_refresh, int flag);
912 void viafb_set_iga_path(void);
913 void viafb_set_primary_address(u32 addr);
914 void viafb_set_secondary_address(u32 addr);
915 void viafb_set_primary_pitch(u32 pitch);
916 void viafb_set_secondary_pitch(u32 pitch);
917 void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue);
918 void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue);
919 void viafb_get_fb_info(unsigned int *fb_base, unsigned int *fb_len);
921 #endif /* __HW_H__ */