drivers/video/via/hw.h

   1 /*
   2  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
   3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
   4
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public
   7  * License as published by the Free Software Foundation;
   8  * either version 2, or (at your option) any later version.
   9
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
  12  * the implied warranty of MERCHANTABILITY or FITNESS FOR
  13  * A PARTICULAR PURPOSE.See the GNU General Public License
  14  * for more details.
  15
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc.,
  19  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20  */
  21
  22 #ifndef __HW_H__
  23 #define __HW_H__
  24
  25 #include "viamode.h"
  26 #include "global.h"
  27 #include "via_io.h"
  28 #include "via_modesetting.h"
  29
  30 #define viafb_read_reg(p, i)                    via_read_reg(p, i)
  31 #define viafb_write_reg(i, p, d)                via_write_reg(p, i, d)
  32 #define viafb_write_reg_mask(i, p, d, m)        via_write_reg_mask(p, i, d, m)
  33
  34 /***************************************************
  35 * Definition IGA1 Design Method of CRTC Registers *
  36 ****************************************************/
  37 #define IGA1_HOR_TOTAL_FORMULA(x)           (((x)/8)-5)
  38 #define IGA1_HOR_ADDR_FORMULA(x)            (((x)/8)-1)
  39 #define IGA1_HOR_BLANK_START_FORMULA(x)     (((x)/8)-1)
  40 #define IGA1_HOR_BLANK_END_FORMULA(x, y)     (((x+y)/8)-1)
  41 #define IGA1_HOR_SYNC_START_FORMULA(x)      ((x)/8)
  42 #define IGA1_HOR_SYNC_END_FORMULA(x, y)      ((x+y)/8)
  43
  44 #define IGA1_VER_TOTAL_FORMULA(x)           ((x)-2)
  45 #define IGA1_VER_ADDR_FORMULA(x)            ((x)-1)
  46 #define IGA1_VER_BLANK_START_FORMULA(x)     ((x)-1)
  47 #define IGA1_VER_BLANK_END_FORMULA(x, y)     ((x+y)-1)
  48 #define IGA1_VER_SYNC_START_FORMULA(x)      ((x)-1)
  49 #define IGA1_VER_SYNC_END_FORMULA(x, y)      ((x+y)-1)
  50
  51 /***************************************************
  52 ** Definition IGA2 Design Method of CRTC Registers *
  53 ****************************************************/
  54 #define IGA2_HOR_TOTAL_FORMULA(x)           ((x)-1)
  55 #define IGA2_HOR_ADDR_FORMULA(x)            ((x)-1)
  56 #define IGA2_HOR_BLANK_START_FORMULA(x)     ((x)-1)
  57 #define IGA2_HOR_BLANK_END_FORMULA(x, y)     ((x+y)-1)
  58 #define IGA2_HOR_SYNC_START_FORMULA(x)      ((x)-1)
  59 #define IGA2_HOR_SYNC_END_FORMULA(x, y)      ((x+y)-1)
  60
  61 #define IGA2_VER_TOTAL_FORMULA(x)           ((x)-1)
  62 #define IGA2_VER_ADDR_FORMULA(x)            ((x)-1)
  63 #define IGA2_VER_BLANK_START_FORMULA(x)     ((x)-1)
  64 #define IGA2_VER_BLANK_END_FORMULA(x, y)     ((x+y)-1)
  65 #define IGA2_VER_SYNC_START_FORMULA(x)      ((x)-1)
  66 #define IGA2_VER_SYNC_END_FORMULA(x, y)      ((x+y)-1)
  67
  68 /**********************************************************/
  69 /* Definition IGA2 Design Method of CRTC Shadow Registers */
  70 /**********************************************************/
  71 #define IGA2_HOR_TOTAL_SHADOW_FORMULA(x)           ((x/8)-5)
  72 #define IGA2_HOR_BLANK_END_SHADOW_FORMULA(x, y)     (((x+y)/8)-1)
  73 #define IGA2_VER_TOTAL_SHADOW_FORMULA(x)           ((x)-2)
  74 #define IGA2_VER_ADDR_SHADOW_FORMULA(x)            ((x)-1)
  75 #define IGA2_VER_BLANK_START_SHADOW_FORMULA(x)     ((x)-1)
  76 #define IGA2_VER_BLANK_END_SHADOW_FORMULA(x, y)     ((x+y)-1)
  77 #define IGA2_VER_SYNC_START_SHADOW_FORMULA(x)      (x)
  78 #define IGA2_VER_SYNC_END_SHADOW_FORMULA(x, y)      (x+y)
  79
  80 /* Define Register Number for IGA1 CRTC Timing */
  81
  82 /* location: {CR00,0,7},{CR36,3,3} */
  83 #define IGA1_HOR_TOTAL_REG_NUM          2
  84 /* location: {CR01,0,7} */
  85 #define IGA1_HOR_ADDR_REG_NUM           1
  86 /* location: {CR02,0,7} */
  87 #define IGA1_HOR_BLANK_START_REG_NUM    1
  88 /* location: {CR03,0,4},{CR05,7,7},{CR33,5,5} */
  89 #define IGA1_HOR_BLANK_END_REG_NUM      3
  90 /* location: {CR04,0,7},{CR33,4,4} */
  91 #define IGA1_HOR_SYNC_START_REG_NUM     2
  92 /* location: {CR05,0,4} */
  93 #define IGA1_HOR_SYNC_END_REG_NUM       1
  94 /* location: {CR06,0,7},{CR07,0,0},{CR07,5,5},{CR35,0,0} */
  95 #define IGA1_VER_TOTAL_REG_NUM          4
  96 /* location: {CR12,0,7},{CR07,1,1},{CR07,6,6},{CR35,2,2} */
  97 #define IGA1_VER_ADDR_REG_NUM           4
  98 /* location: {CR15,0,7},{CR07,3,3},{CR09,5,5},{CR35,3,3} */
  99 #define IGA1_VER_BLANK_START_REG_NUM    4
 100 /* location: {CR16,0,7} */
 101 #define IGA1_VER_BLANK_END_REG_NUM      1
 102 /* location: {CR10,0,7},{CR07,2,2},{CR07,7,7},{CR35,1,1} */
 103 #define IGA1_VER_SYNC_START_REG_NUM     4
 104 /* location: {CR11,0,3} */
 105 #define IGA1_VER_SYNC_END_REG_NUM       1
 106
 107 /* Define Register Number for IGA2 Shadow CRTC Timing */
 108
 109 /* location: {CR6D,0,7},{CR71,3,3} */
 110 #define IGA2_SHADOW_HOR_TOTAL_REG_NUM       2
 111 /* location: {CR6E,0,7} */
 112 #define IGA2_SHADOW_HOR_BLANK_END_REG_NUM   1
 113 /* location: {CR6F,0,7},{CR71,0,2} */
 114 #define IGA2_SHADOW_VER_TOTAL_REG_NUM       2
 115 /* location: {CR70,0,7},{CR71,4,6} */
 116 #define IGA2_SHADOW_VER_ADDR_REG_NUM        2
 117 /* location: {CR72,0,7},{CR74,4,6} */
 118 #define IGA2_SHADOW_VER_BLANK_START_REG_NUM 2
 119 /* location: {CR73,0,7},{CR74,0,2} */
 120 #define IGA2_SHADOW_VER_BLANK_END_REG_NUM   2
 121 /* location: {CR75,0,7},{CR76,4,6} */
 122 #define IGA2_SHADOW_VER_SYNC_START_REG_NUM  2
 123 /* location: {CR76,0,3} */
 124 #define IGA2_SHADOW_VER_SYNC_END_REG_NUM    1
 125
 126 /* Define Register Number for IGA2 CRTC Timing */
 127
 128 /* location: {CR50,0,7},{CR55,0,3} */
 129 #define IGA2_HOR_TOTAL_REG_NUM          2
 130 /* location: {CR51,0,7},{CR55,4,6} */
 131 #define IGA2_HOR_ADDR_REG_NUM           2
 132 /* location: {CR52,0,7},{CR54,0,2} */
 133 #define IGA2_HOR_BLANK_START_REG_NUM    2
 134 /* location: CLE266: {CR53,0,7},{CR54,3,5} => CLE266's CR5D[6]
 135 is reserved, so it may have problem to set 1600x1200 on IGA2. */
 136 /*              Others: {CR53,0,7},{CR54,3,5},{CR5D,6,6} */
 137 #define IGA2_HOR_BLANK_END_REG_NUM      3
 138 /* location: {CR56,0,7},{CR54,6,7},{CR5C,7,7} */
 139 /* VT3314 and Later: {CR56,0,7},{CR54,6,7},{CR5C,7,7}, {CR5D,7,7} */
 140 #define IGA2_HOR_SYNC_START_REG_NUM     4
 141
 142 /* location: {CR57,0,7},{CR5C,6,6} */
 143 #define IGA2_HOR_SYNC_END_REG_NUM       2
 144 /* location: {CR58,0,7},{CR5D,0,2} */
 145 #define IGA2_VER_TOTAL_REG_NUM          2
 146 /* location: {CR59,0,7},{CR5D,3,5} */
 147 #define IGA2_VER_ADDR_REG_NUM           2
 148 /* location: {CR5A,0,7},{CR5C,0,2} */
 149 #define IGA2_VER_BLANK_START_REG_NUM    2
 150 /* location: {CR5E,0,7},{CR5C,3,5} */
 151 #define IGA2_VER_BLANK_END_REG_NUM      2
 152 /* location: {CR5E,0,7},{CR5F,5,7} */
 153 #define IGA2_VER_SYNC_START_REG_NUM     2
 154 /* location: {CR5F,0,4} */
 155 #define IGA2_VER_SYNC_END_REG_NUM       1
 156
 157 /* Define Fetch Count Register*/
 158
 159 /* location: {SR1C,0,7},{SR1D,0,1} */
 160 #define IGA1_FETCH_COUNT_REG_NUM        2
 161 /* 16 bytes alignment. */
 162 #define IGA1_FETCH_COUNT_ALIGN_BYTE     16
 163 /* x: H resolution, y: color depth */
 164 #define IGA1_FETCH_COUNT_PATCH_VALUE    4
 165 #define IGA1_FETCH_COUNT_FORMULA(x, y)   \
 166         (((x*y)/IGA1_FETCH_COUNT_ALIGN_BYTE) + IGA1_FETCH_COUNT_PATCH_VALUE)
 167
 168 /* location: {CR65,0,7},{CR67,2,3} */
 169 #define IGA2_FETCH_COUNT_REG_NUM        2
 170 #define IGA2_FETCH_COUNT_ALIGN_BYTE     16
 171 #define IGA2_FETCH_COUNT_PATCH_VALUE    0
 172 #define IGA2_FETCH_COUNT_FORMULA(x, y)   \
 173         (((x*y)/IGA2_FETCH_COUNT_ALIGN_BYTE) + IGA2_FETCH_COUNT_PATCH_VALUE)
 174
 175 /* Staring Address*/
 176
 177 /* location: {CR0C,0,7},{CR0D,0,7},{CR34,0,7},{CR48,0,1} */
 178 #define IGA1_STARTING_ADDR_REG_NUM      4
 179 /* location: {CR62,1,7},{CR63,0,7},{CR64,0,7} */
 180 #define IGA2_STARTING_ADDR_REG_NUM      3
 181
 182 /* Define Display OFFSET*/
 183 /* These value are by HW suggested value*/
 184 /* location: {SR17,0,7} */
 185 #define K800_IGA1_FIFO_MAX_DEPTH                384
 186 /* location: {SR16,0,5},{SR16,7,7} */
 187 #define K800_IGA1_FIFO_THRESHOLD                328
 188 /* location: {SR18,0,5},{SR18,7,7} */
 189 #define K800_IGA1_FIFO_HIGH_THRESHOLD           296
 190 /* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */
 191                                 /* because HW only 5 bits */
 192 #define K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM      0
 193
 194 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
 195 #define K800_IGA2_FIFO_MAX_DEPTH                384
 196 /* location: {CR68,0,3},{CR95,4,6} */
 197 #define K800_IGA2_FIFO_THRESHOLD                328
 198 /* location: {CR92,0,3},{CR95,0,2} */
 199 #define K800_IGA2_FIFO_HIGH_THRESHOLD           296
 200 /* location: {CR94,0,6} */
 201 #define K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM      128
 202
 203 /* location: {SR17,0,7} */
 204 #define P880_IGA1_FIFO_MAX_DEPTH                192
 205 /* location: {SR16,0,5},{SR16,7,7} */
 206 #define P880_IGA1_FIFO_THRESHOLD                128
 207 /* location: {SR18,0,5},{SR18,7,7} */
 208 #define P880_IGA1_FIFO_HIGH_THRESHOLD           64
 209 /* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */
 210                                 /* because HW only 5 bits */
 211 #define P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM      0
 212
 213 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
 214 #define P880_IGA2_FIFO_MAX_DEPTH                96
 215 /* location: {CR68,0,3},{CR95,4,6} */
 216 #define P880_IGA2_FIFO_THRESHOLD                64
 217 /* location: {CR92,0,3},{CR95,0,2} */
 218 #define P880_IGA2_FIFO_HIGH_THRESHOLD           32
 219 /* location: {CR94,0,6} */
 220 #define P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM      128
 221
 222 /* VT3314 chipset*/
 223
 224 /* location: {SR17,0,7} */
 225 #define CN700_IGA1_FIFO_MAX_DEPTH               96
 226 /* location: {SR16,0,5},{SR16,7,7} */
 227 #define CN700_IGA1_FIFO_THRESHOLD               80
 228 /* location: {SR18,0,5},{SR18,7,7} */
 229 #define CN700_IGA1_FIFO_HIGH_THRESHOLD          64
 230 /* location: {SR22,0,4}. (128/4) =64, P800 must be set zero,
 231                                 because HW only 5 bits */
 232 #define CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     0
 233 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
 234 #define CN700_IGA2_FIFO_MAX_DEPTH               96
 235 /* location: {CR68,0,3},{CR95,4,6} */
 236 #define CN700_IGA2_FIFO_THRESHOLD               80
 237 /* location: {CR92,0,3},{CR95,0,2} */
 238 #define CN700_IGA2_FIFO_HIGH_THRESHOLD          32
 239 /* location: {CR94,0,6} */
 240 #define CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     128
 241
 242 /* For VT3324, these values are suggested by HW */
 243 /* location: {SR17,0,7} */
 244 #define CX700_IGA1_FIFO_MAX_DEPTH               192
 245 /* location: {SR16,0,5},{SR16,7,7} */
 246 #define CX700_IGA1_FIFO_THRESHOLD               128
 247 /* location: {SR18,0,5},{SR18,7,7} */
 248 #define CX700_IGA1_FIFO_HIGH_THRESHOLD          128
 249 /* location: {SR22,0,4} */
 250 #define CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     124
 251
 252 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
 253 #define CX700_IGA2_FIFO_MAX_DEPTH               96
 254 /* location: {CR68,0,3},{CR95,4,6} */
 255 #define CX700_IGA2_FIFO_THRESHOLD               64
 256 /* location: {CR92,0,3},{CR95,0,2} */
 257 #define CX700_IGA2_FIFO_HIGH_THRESHOLD          32
 258 /* location: {CR94,0,6} */
 259 #define CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     128
 260
 261 /* VT3336 chipset*/
 262 /* location: {SR17,0,7} */
 263 #define K8M890_IGA1_FIFO_MAX_DEPTH               360
 264 /* location: {SR16,0,5},{SR16,7,7} */
 265 #define K8M890_IGA1_FIFO_THRESHOLD               328
 266 /* location: {SR18,0,5},{SR18,7,7} */
 267 #define K8M890_IGA1_FIFO_HIGH_THRESHOLD          296
 268 /* location: {SR22,0,4}. */
 269 #define K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     124
 270
 271 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
 272 #define K8M890_IGA2_FIFO_MAX_DEPTH               360
 273 /* location: {CR68,0,3},{CR95,4,6} */
 274 #define K8M890_IGA2_FIFO_THRESHOLD               328
 275 /* location: {CR92,0,3},{CR95,0,2} */
 276 #define K8M890_IGA2_FIFO_HIGH_THRESHOLD          296
 277 /* location: {CR94,0,6} */
 278 #define K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     124
 279
 280 /* VT3327 chipset*/
 281 /* location: {SR17,0,7} */
 282 #define P4M890_IGA1_FIFO_MAX_DEPTH               96
 283 /* location: {SR16,0,5},{SR16,7,7} */
 284 #define P4M890_IGA1_FIFO_THRESHOLD               76
 285 /* location: {SR18,0,5},{SR18,7,7} */
 286 #define P4M890_IGA1_FIFO_HIGH_THRESHOLD          64
 287 /* location: {SR22,0,4}. (32/4) =8 */
 288 #define P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     32
 289 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
 290 #define P4M890_IGA2_FIFO_MAX_DEPTH               96
 291 /* location: {CR68,0,3},{CR95,4,6} */
 292 #define P4M890_IGA2_FIFO_THRESHOLD               76
 293 /* location: {CR92,0,3},{CR95,0,2} */
 294 #define P4M890_IGA2_FIFO_HIGH_THRESHOLD          64
 295 /* location: {CR94,0,6} */
 296 #define P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     32
 297
 298 /* VT3364 chipset*/
 299 /* location: {SR17,0,7} */
 300 #define P4M900_IGA1_FIFO_MAX_DEPTH               96
 301 /* location: {SR16,0,5},{SR16,7,7} */
 302 #define P4M900_IGA1_FIFO_THRESHOLD               76
 303 /* location: {SR18,0,5},{SR18,7,7} */
 304 #define P4M900_IGA1_FIFO_HIGH_THRESHOLD          76
 305 /* location: {SR22,0,4}. */
 306 #define P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     32
 307 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
 308 #define P4M900_IGA2_FIFO_MAX_DEPTH               96
 309 /* location: {CR68,0,3},{CR95,4,6} */
 310 #define P4M900_IGA2_FIFO_THRESHOLD               76
 311 /* location: {CR92,0,3},{CR95,0,2} */
 312 #define P4M900_IGA2_FIFO_HIGH_THRESHOLD          76
 313 /* location: {CR94,0,6} */
 314 #define P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     32
 315
 316 /* For VT3353, these values are suggested by HW */
 317 /* location: {SR17,0,7} */
 318 #define VX800_IGA1_FIFO_MAX_DEPTH               192
 319 /* location: {SR16,0,5},{SR16,7,7} */
 320 #define VX800_IGA1_FIFO_THRESHOLD               152
 321 /* location: {SR18,0,5},{SR18,7,7} */
 322 #define VX800_IGA1_FIFO_HIGH_THRESHOLD          152
 323 /* location: {SR22,0,4} */
 324 #define VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM      64
 325 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
 326 #define VX800_IGA2_FIFO_MAX_DEPTH               96
 327 /* location: {CR68,0,3},{CR95,4,6} */
 328 #define VX800_IGA2_FIFO_THRESHOLD               64
 329 /* location: {CR92,0,3},{CR95,0,2} */
 330 #define VX800_IGA2_FIFO_HIGH_THRESHOLD          32
 331 /* location: {CR94,0,6} */
 332 #define VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     128
 333
 334 /* For VT3409 */
 335 #define VX855_IGA1_FIFO_MAX_DEPTH               400
 336 #define VX855_IGA1_FIFO_THRESHOLD               320
 337 #define VX855_IGA1_FIFO_HIGH_THRESHOLD          320
 338 #define VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     160
 339
 340 #define VX855_IGA2_FIFO_MAX_DEPTH               200
 341 #define VX855_IGA2_FIFO_THRESHOLD               160
 342 #define VX855_IGA2_FIFO_HIGH_THRESHOLD          160
 343 #define VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     320
 344
 345 #define IGA1_FIFO_DEPTH_SELECT_REG_NUM          1
 346 #define IGA1_FIFO_THRESHOLD_REG_NUM             2
 347 #define IGA1_FIFO_HIGH_THRESHOLD_REG_NUM        2
 348 #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM   1
 349
 350 #define IGA2_FIFO_DEPTH_SELECT_REG_NUM          3
 351 #define IGA2_FIFO_THRESHOLD_REG_NUM             2
 352 #define IGA2_FIFO_HIGH_THRESHOLD_REG_NUM        2
 353 #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM   1
 354
 355 #define IGA1_FIFO_DEPTH_SELECT_FORMULA(x)                   ((x/2)-1)
 356 #define IGA1_FIFO_THRESHOLD_FORMULA(x)                      (x/4)
 357 #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x)            (x/4)
 358 #define IGA1_FIFO_HIGH_THRESHOLD_FORMULA(x)                 (x/4)
 359 #define IGA2_FIFO_DEPTH_SELECT_FORMULA(x)                   (((x/2)/4)-1)
 360 #define IGA2_FIFO_THRESHOLD_FORMULA(x)                      (x/4)
 361 #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x)            (x/4)
 362 #define IGA2_FIFO_HIGH_THRESHOLD_FORMULA(x)                 (x/4)
 363
 364 /************************************************************************/
 365 /*  LCD Timing                                                          */
 366 /************************************************************************/
 367
 368 /* 500 ms = 500000 us */
 369 #define LCD_POWER_SEQ_TD0               500000
 370 /* 50 ms = 50000 us */
 371 #define LCD_POWER_SEQ_TD1               50000
 372 /* 0 us */
 373 #define LCD_POWER_SEQ_TD2               0
 374 /* 210 ms = 210000 us */
 375 #define LCD_POWER_SEQ_TD3               210000
 376 /* 2^10 * (1/14.31818M) = 71.475 us (K400.revA) */
 377 #define CLE266_POWER_SEQ_UNIT           71
 378 /* 2^11 * (1/14.31818M) = 142.95 us (K400.revB) */
 379 #define K800_POWER_SEQ_UNIT             142
 380 /* 2^13 * (1/14.31818M) = 572.1 us */
 381 #define P880_POWER_SEQ_UNIT             572
 382
 383 #define CLE266_POWER_SEQ_FORMULA(x)     ((x)/CLE266_POWER_SEQ_UNIT)
 384 #define K800_POWER_SEQ_FORMULA(x)       ((x)/K800_POWER_SEQ_UNIT)
 385 #define P880_POWER_SEQ_FORMULA(x)       ((x)/P880_POWER_SEQ_UNIT)
 386
 387 /* location: {CR8B,0,7},{CR8F,0,3} */
 388 #define LCD_POWER_SEQ_TD0_REG_NUM       2
 389 /* location: {CR8C,0,7},{CR8F,4,7} */
 390 #define LCD_POWER_SEQ_TD1_REG_NUM       2
 391 /* location: {CR8D,0,7},{CR90,0,3} */
 392 #define LCD_POWER_SEQ_TD2_REG_NUM       2
 393 /* location: {CR8E,0,7},{CR90,4,7} */
 394 #define LCD_POWER_SEQ_TD3_REG_NUM       2
 395
 396 /* LCD Scaling factor*/
 397 /* x: indicate setting horizontal size*/
 398 /* y: indicate panel horizontal size*/
 399
 400 /* Horizontal scaling factor 10 bits (2^10) */
 401 #define CLE266_LCD_HOR_SCF_FORMULA(x, y)   (((x-1)*1024)/(y-1))
 402 /* Vertical scaling factor 10 bits (2^10) */
 403 #define CLE266_LCD_VER_SCF_FORMULA(x, y)   (((x-1)*1024)/(y-1))
 404 /* Horizontal scaling factor 10 bits (2^12) */
 405 #define K800_LCD_HOR_SCF_FORMULA(x, y)     (((x-1)*4096)/(y-1))
 406 /* Vertical scaling factor 10 bits (2^11) */
 407 #define K800_LCD_VER_SCF_FORMULA(x, y)     (((x-1)*2048)/(y-1))
 408
 409 /* location: {CR9F,0,1},{CR77,0,7},{CR79,4,5} */
 410 #define LCD_HOR_SCALING_FACTOR_REG_NUM  3
 411 /* location: {CR79,3,3},{CR78,0,7},{CR79,6,7} */
 412 #define LCD_VER_SCALING_FACTOR_REG_NUM  3
 413 /* location: {CR77,0,7},{CR79,4,5} */
 414 #define LCD_HOR_SCALING_FACTOR_REG_NUM_CLE  2
 415 /* location: {CR78,0,7},{CR79,6,7} */
 416 #define LCD_VER_SCALING_FACTOR_REG_NUM_CLE  2
 417
 418 /************************************************
 419  *****     Define IGA1 Display Timing       *****
 420  ************************************************/
 421 struct io_register {
 422         u8 io_addr;
 423         u8 start_bit;
 424         u8 end_bit;
 425 };
 426
 427 /* IGA1 Horizontal Total */
 428 struct iga1_hor_total {
 429         int reg_num;
 430         struct io_register reg[IGA1_HOR_TOTAL_REG_NUM];
 431 };
 432
 433 /* IGA1 Horizontal Addressable Video */
 434 struct iga1_hor_addr {
 435         int reg_num;
 436         struct io_register reg[IGA1_HOR_ADDR_REG_NUM];
 437 };
 438
 439 /* IGA1 Horizontal Blank Start */
 440 struct iga1_hor_blank_start {
 441         int reg_num;
 442         struct io_register reg[IGA1_HOR_BLANK_START_REG_NUM];
 443 };
 444
 445 /* IGA1 Horizontal Blank End */
 446 struct iga1_hor_blank_end {
 447         int reg_num;
 448         struct io_register reg[IGA1_HOR_BLANK_END_REG_NUM];
 449 };
 450
 451 /* IGA1 Horizontal Sync Start */
 452 struct iga1_hor_sync_start {
 453         int reg_num;
 454         struct io_register reg[IGA1_HOR_SYNC_START_REG_NUM];
 455 };
 456
 457 /* IGA1 Horizontal Sync End */
 458 struct iga1_hor_sync_end {
 459         int reg_num;
 460         struct io_register reg[IGA1_HOR_SYNC_END_REG_NUM];
 461 };
 462
 463 /* IGA1 Vertical Total */
 464 struct iga1_ver_total {
 465         int reg_num;
 466         struct io_register reg[IGA1_VER_TOTAL_REG_NUM];
 467 };
 468
 469 /* IGA1 Vertical Addressable Video */
 470 struct iga1_ver_addr {
 471         int reg_num;
 472         struct io_register reg[IGA1_VER_ADDR_REG_NUM];
 473 };
 474
 475 /* IGA1 Vertical Blank Start */
 476 struct iga1_ver_blank_start {
 477         int reg_num;
 478         struct io_register reg[IGA1_VER_BLANK_START_REG_NUM];
 479 };
 480
 481 /* IGA1 Vertical Blank End */
 482 struct iga1_ver_blank_end {
 483         int reg_num;
 484         struct io_register reg[IGA1_VER_BLANK_END_REG_NUM];
 485 };
 486
 487 /* IGA1 Vertical Sync Start */
 488 struct iga1_ver_sync_start {
 489         int reg_num;
 490         struct io_register reg[IGA1_VER_SYNC_START_REG_NUM];
 491 };
 492
 493 /* IGA1 Vertical Sync End */
 494 struct iga1_ver_sync_end {
 495         int reg_num;
 496         struct io_register reg[IGA1_VER_SYNC_END_REG_NUM];
 497 };
 498
 499 /*****************************************************
 500 **      Define IGA2 Shadow Display Timing         ****
 501 *****************************************************/
 502
 503 /* IGA2 Shadow Horizontal Total */
 504 struct iga2_shadow_hor_total {
 505         int reg_num;
 506         struct io_register reg[IGA2_SHADOW_HOR_TOTAL_REG_NUM];
 507 };
 508
 509 /* IGA2 Shadow Horizontal Blank End */
 510 struct iga2_shadow_hor_blank_end {
 511         int reg_num;
 512         struct io_register reg[IGA2_SHADOW_HOR_BLANK_END_REG_NUM];
 513 };
 514
 515 /* IGA2 Shadow Vertical Total */
 516 struct iga2_shadow_ver_total {
 517         int reg_num;
 518         struct io_register reg[IGA2_SHADOW_VER_TOTAL_REG_NUM];
 519 };
 520
 521 /* IGA2 Shadow Vertical Addressable Video */
 522 struct iga2_shadow_ver_addr {
 523         int reg_num;
 524         struct io_register reg[IGA2_SHADOW_VER_ADDR_REG_NUM];
 525 };
 526
 527 /* IGA2 Shadow Vertical Blank Start */
 528 struct iga2_shadow_ver_blank_start {
 529         int reg_num;
 530         struct io_register reg[IGA2_SHADOW_VER_BLANK_START_REG_NUM];
 531 };
 532
 533 /* IGA2 Shadow Vertical Blank End */
 534 struct iga2_shadow_ver_blank_end {
 535         int reg_num;
 536         struct io_register reg[IGA2_SHADOW_VER_BLANK_END_REG_NUM];
 537 };
 538
 539 /* IGA2 Shadow Vertical Sync Start */
 540 struct iga2_shadow_ver_sync_start {
 541         int reg_num;
 542         struct io_register reg[IGA2_SHADOW_VER_SYNC_START_REG_NUM];
 543 };
 544
 545 /* IGA2 Shadow Vertical Sync End */
 546 struct iga2_shadow_ver_sync_end {
 547         int reg_num;
 548         struct io_register reg[IGA2_SHADOW_VER_SYNC_END_REG_NUM];
 549 };
 550
 551 /*****************************************************
 552 **      Define IGA2 Display Timing                ****
 553 ******************************************************/
 554
 555 /* IGA2 Horizontal Total */
 556 struct iga2_hor_total {
 557         int reg_num;
 558         struct io_register reg[IGA2_HOR_TOTAL_REG_NUM];
 559 };
 560
 561 /* IGA2 Horizontal Addressable Video */
 562 struct iga2_hor_addr {
 563         int reg_num;
 564         struct io_register reg[IGA2_HOR_ADDR_REG_NUM];
 565 };
 566
 567 /* IGA2 Horizontal Blank Start */
 568 struct iga2_hor_blank_start {
 569         int reg_num;
 570         struct io_register reg[IGA2_HOR_BLANK_START_REG_NUM];
 571 };
 572
 573 /* IGA2 Horizontal Blank End */
 574 struct iga2_hor_blank_end {
 575         int reg_num;
 576         struct io_register reg[IGA2_HOR_BLANK_END_REG_NUM];
 577 };
 578
 579 /* IGA2 Horizontal Sync Start */
 580 struct iga2_hor_sync_start {
 581         int reg_num;
 582         struct io_register reg[IGA2_HOR_SYNC_START_REG_NUM];
 583 };
 584
 585 /* IGA2 Horizontal Sync End */
 586 struct iga2_hor_sync_end {
 587         int reg_num;
 588         struct io_register reg[IGA2_HOR_SYNC_END_REG_NUM];
 589 };
 590
 591 /* IGA2 Vertical Total */
 592 struct iga2_ver_total {
 593         int reg_num;
 594         struct io_register reg[IGA2_VER_TOTAL_REG_NUM];
 595 };
 596
 597 /* IGA2 Vertical Addressable Video */
 598 struct iga2_ver_addr {
 599         int reg_num;
 600         struct io_register reg[IGA2_VER_ADDR_REG_NUM];
 601 };
 602
 603 /* IGA2 Vertical Blank Start */
 604 struct iga2_ver_blank_start {
 605         int reg_num;
 606         struct io_register reg[IGA2_VER_BLANK_START_REG_NUM];
 607 };
 608
 609 /* IGA2 Vertical Blank End */
 610 struct iga2_ver_blank_end {
 611         int reg_num;
 612         struct io_register reg[IGA2_VER_BLANK_END_REG_NUM];
 613 };
 614
 615 /* IGA2 Vertical Sync Start */
 616 struct iga2_ver_sync_start {
 617         int reg_num;
 618         struct io_register reg[IGA2_VER_SYNC_START_REG_NUM];
 619 };
 620
 621 /* IGA2 Vertical Sync End */
 622 struct iga2_ver_sync_end {
 623         int reg_num;
 624         struct io_register reg[IGA2_VER_SYNC_END_REG_NUM];
 625 };
 626
 627 /* IGA1 Fetch Count Register */
 628 struct iga1_fetch_count {
 629         int reg_num;
 630         struct io_register reg[IGA1_FETCH_COUNT_REG_NUM];
 631 };
 632
 633 /* IGA2 Fetch Count Register */
 634 struct iga2_fetch_count {
 635         int reg_num;
 636         struct io_register reg[IGA2_FETCH_COUNT_REG_NUM];
 637 };
 638
 639 struct fetch_count {
 640         struct iga1_fetch_count iga1_fetch_count_reg;
 641         struct iga2_fetch_count iga2_fetch_count_reg;
 642 };
 643
 644 /* Starting Address Register */
 645 struct iga1_starting_addr {
 646         int reg_num;
 647         struct io_register reg[IGA1_STARTING_ADDR_REG_NUM];
 648 };
 649
 650 struct iga2_starting_addr {
 651         int reg_num;
 652         struct io_register reg[IGA2_STARTING_ADDR_REG_NUM];
 653 };
 654
 655 struct starting_addr {
 656         struct iga1_starting_addr iga1_starting_addr_reg;
 657         struct iga2_starting_addr iga2_starting_addr_reg;
 658 };
 659
 660 /* LCD Power Sequence Timer */
 661 struct lcd_pwd_seq_td0 {
 662         int reg_num;
 663         struct io_register reg[LCD_POWER_SEQ_TD0_REG_NUM];
 664 };
 665
 666 struct lcd_pwd_seq_td1 {
 667         int reg_num;
 668         struct io_register reg[LCD_POWER_SEQ_TD1_REG_NUM];
 669 };
 670
 671 struct lcd_pwd_seq_td2 {
 672         int reg_num;
 673         struct io_register reg[LCD_POWER_SEQ_TD2_REG_NUM];
 674 };
 675
 676 struct lcd_pwd_seq_td3 {
 677         int reg_num;
 678         struct io_register reg[LCD_POWER_SEQ_TD3_REG_NUM];
 679 };
 680
 681 struct _lcd_pwd_seq_timer {
 682         struct lcd_pwd_seq_td0 td0;
 683         struct lcd_pwd_seq_td1 td1;
 684         struct lcd_pwd_seq_td2 td2;
 685         struct lcd_pwd_seq_td3 td3;
 686 };
 687
 688 /* LCD Scaling Factor */
 689 struct _lcd_hor_scaling_factor {
 690         int reg_num;
 691         struct io_register reg[LCD_HOR_SCALING_FACTOR_REG_NUM];
 692 };
 693
 694 struct _lcd_ver_scaling_factor {
 695         int reg_num;
 696         struct io_register reg[LCD_VER_SCALING_FACTOR_REG_NUM];
 697 };
 698
 699 struct _lcd_scaling_factor {
 700         struct _lcd_hor_scaling_factor lcd_hor_scaling_factor;
 701         struct _lcd_ver_scaling_factor lcd_ver_scaling_factor;
 702 };
 703
 704 struct pll_map {
 705         u32 clk;
 706         u32 cle266_pll;
 707         u32 k800_pll;
 708         u32 cx700_pll;
 709         u32 vx855_pll;
 710 };
 711
 712 struct rgbLUT {
 713         u8 red;
 714         u8 green;
 715         u8 blue;
 716 };
 717
 718 struct lcd_pwd_seq_timer {
 719         u16 td0;
 720         u16 td1;
 721         u16 td2;
 722         u16 td3;
 723 };
 724
 725 /* Display FIFO Relation Registers*/
 726 struct iga1_fifo_depth_select {
 727         int reg_num;
 728         struct io_register reg[IGA1_FIFO_DEPTH_SELECT_REG_NUM];
 729 };
 730
 731 struct iga1_fifo_threshold_select {
 732         int reg_num;
 733         struct io_register reg[IGA1_FIFO_THRESHOLD_REG_NUM];
 734 };
 735
 736 struct iga1_fifo_high_threshold_select {
 737         int reg_num;
 738         struct io_register reg[IGA1_FIFO_HIGH_THRESHOLD_REG_NUM];
 739 };
 740
 741 struct iga1_display_queue_expire_num {
 742         int reg_num;
 743         struct io_register reg[IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];
 744 };
 745
 746 struct iga2_fifo_depth_select {
 747         int reg_num;
 748         struct io_register reg[IGA2_FIFO_DEPTH_SELECT_REG_NUM];
 749 };
 750
 751 struct iga2_fifo_threshold_select {
 752         int reg_num;
 753         struct io_register reg[IGA2_FIFO_THRESHOLD_REG_NUM];
 754 };
 755
 756 struct iga2_fifo_high_threshold_select {
 757         int reg_num;
 758         struct io_register reg[IGA2_FIFO_HIGH_THRESHOLD_REG_NUM];
 759 };
 760
 761 struct iga2_display_queue_expire_num {
 762         int reg_num;
 763         struct io_register reg[IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];
 764 };
 765
 766 struct fifo_depth_select {
 767         struct iga1_fifo_depth_select iga1_fifo_depth_select_reg;
 768         struct iga2_fifo_depth_select iga2_fifo_depth_select_reg;
 769 };
 770
 771 struct fifo_threshold_select {
 772         struct iga1_fifo_threshold_select iga1_fifo_threshold_select_reg;
 773         struct iga2_fifo_threshold_select iga2_fifo_threshold_select_reg;
 774 };
 775
 776 struct fifo_high_threshold_select {
 777         struct iga1_fifo_high_threshold_select
 778          iga1_fifo_high_threshold_select_reg;
 779         struct iga2_fifo_high_threshold_select
 780          iga2_fifo_high_threshold_select_reg;
 781 };
 782
 783 struct display_queue_expire_num {
 784         struct iga1_display_queue_expire_num
 785          iga1_display_queue_expire_num_reg;
 786         struct iga2_display_queue_expire_num
 787          iga2_display_queue_expire_num_reg;
 788 };
 789
 790 struct iga1_crtc_timing {
 791         struct iga1_hor_total hor_total;
 792         struct iga1_hor_addr hor_addr;
 793         struct iga1_hor_blank_start hor_blank_start;
 794         struct iga1_hor_blank_end hor_blank_end;
 795         struct iga1_hor_sync_start hor_sync_start;
 796         struct iga1_hor_sync_end hor_sync_end;
 797         struct iga1_ver_total ver_total;
 798         struct iga1_ver_addr ver_addr;
 799         struct iga1_ver_blank_start ver_blank_start;
 800         struct iga1_ver_blank_end ver_blank_end;
 801         struct iga1_ver_sync_start ver_sync_start;
 802         struct iga1_ver_sync_end ver_sync_end;
 803 };
 804
 805 struct iga2_shadow_crtc_timing {
 806         struct iga2_shadow_hor_total hor_total_shadow;
 807         struct iga2_shadow_hor_blank_end hor_blank_end_shadow;
 808         struct iga2_shadow_ver_total ver_total_shadow;
 809         struct iga2_shadow_ver_addr ver_addr_shadow;
 810         struct iga2_shadow_ver_blank_start ver_blank_start_shadow;
 811         struct iga2_shadow_ver_blank_end ver_blank_end_shadow;
 812         struct iga2_shadow_ver_sync_start ver_sync_start_shadow;
 813         struct iga2_shadow_ver_sync_end ver_sync_end_shadow;
 814 };
 815
 816 struct iga2_crtc_timing {
 817         struct iga2_hor_total hor_total;
 818         struct iga2_hor_addr hor_addr;
 819         struct iga2_hor_blank_start hor_blank_start;
 820         struct iga2_hor_blank_end hor_blank_end;
 821         struct iga2_hor_sync_start hor_sync_start;
 822         struct iga2_hor_sync_end hor_sync_end;
 823         struct iga2_ver_total ver_total;
 824         struct iga2_ver_addr ver_addr;
 825         struct iga2_ver_blank_start ver_blank_start;
 826         struct iga2_ver_blank_end ver_blank_end;
 827         struct iga2_ver_sync_start ver_sync_start;
 828         struct iga2_ver_sync_end ver_sync_end;
 829 };
 830
 831 /* device ID */
 832 #define CLE266_FUNCTION3    0x3123
 833 #define KM400_FUNCTION3     0x3205
 834 #define CN400_FUNCTION2     0x2259
 835 #define CN400_FUNCTION3     0x3259
 836 /* support VT3314 chipset */
 837 #define CN700_FUNCTION2     0x2314
 838 #define CN700_FUNCTION3     0x3208
 839 /* VT3324 chipset */
 840 #define CX700_FUNCTION2     0x2324
 841 #define CX700_FUNCTION3     0x3324
 842 /* VT3204 chipset*/
 843 #define KM800_FUNCTION3      0x3204
 844 /* VT3336 chipset*/
 845 #define KM890_FUNCTION3      0x3336
 846 /* VT3327 chipset*/
 847 #define P4M890_FUNCTION3     0x3327
 848 /* VT3293 chipset*/
 849 #define CN750_FUNCTION3     0x3208
 850 /* VT3364 chipset*/
 851 #define P4M900_FUNCTION3    0x3364
 852 /* VT3353 chipset*/
 853 #define VX800_FUNCTION3     0x3353
 854 /* VT3409 chipset*/
 855 #define VX855_FUNCTION3     0x3409
 856
 857 #define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value)
 858
 859 struct IODATA {
 860         u8 Index;
 861         u8 Mask;
 862         u8 Data;
 863 };
 864
 865 struct pci_device_id_info {
 866         u32 vendor;
 867         u32 device;
 868         u32 chip_index;
 869 };
 870
 871 extern unsigned int viafb_second_virtual_xres;
 872 extern int viafb_SAMM_ON;
 873 extern int viafb_dual_fb;
 874 extern int viafb_LCD2_ON;
 875 extern int viafb_LCD_ON;
 876 extern int viafb_DVI_ON;
 877 extern int viafb_hotplug;
 878
 879 void viafb_set_output_path(int device, int set_iga,
 880         int output_interface);
 881
 882 void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
 883         struct VideoModeTable *video_mode, int bpp_byte, int set_iga);
 884
 885 void viafb_set_vclock(u32 CLK, int set_iga);
 886 void viafb_load_reg(int timing_value, int viafb_load_reg_num,
 887         struct io_register *reg,
 888               int io_type);
 889 void viafb_crt_disable(void);
 890 void viafb_crt_enable(void);
 891 void init_ad9389(void);
 892 /* Access I/O Function */
 893 void viafb_lock_crt(void);
 894 void viafb_unlock_crt(void);
 895 void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga);
 896 void viafb_write_regx(struct io_reg RegTable[], int ItemNum);
 897 u32 viafb_get_clk_value(int clk);
 898 void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active);
 899 void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
 900                                         *p_gfx_dpa_setting);
 901
 902 int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
 903         struct VideoModeTable *vmode_tbl1, int video_bpp1);
 904 void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
 905         struct VideoModeTable *vmode_tbl);
 906 void viafb_init_chip_info(int chip_type);
 907 void viafb_init_dac(int set_iga);
 908 int viafb_get_pixclock(int hres, int vres, int vmode_refresh);
 909 int viafb_get_refresh(int hres, int vres, u32 float_refresh);
 910 void viafb_update_device_setting(int hres, int vres, int bpp,
 911                            int vmode_refresh, int flag);
 912
 913 void viafb_set_iga_path(void);
 914 void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue);
 915 void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue);
 916 void viafb_get_fb_info(unsigned int *fb_base, unsigned int *fb_len);
 917
 918 #endif /* __HW_H__ */