2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
25 /* Define Return Value */
33 /* Define Bit Field */
43 /* Video Memory Size */
44 #define VIDEO_MEMORY_SIZE_16M 0x1000000
46 /* standard VGA IO port
48 #define VIARMisc 0x3CC
49 #define VIAWMisc 0x3C2
50 #define VIAStatus 0x3DA
67 /* Define Color Depth */
76 /* Sequencer Registers */
121 /* CRT Controller Registers */
148 /* Extend CRT Controller Registers */
270 #define LUT_DATA 0x3C9 /* DACDATA */
271 #define LUT_INDEX_READ 0x3C7 /* DACRX */
272 #define LUT_INDEX_WRITE 0x3C8 /* DACWX */
273 #define DACMASK 0x3C6
275 /* Definition Device */
276 #define DEVICE_CRT 0x01
277 #define DEVICE_DVI 0x03
278 #define DEVICE_LCD 0x04
280 /* Device output interface */
281 #define INTERFACE_NONE 0x00
282 #define INTERFACE_ANALOG_RGB 0x01
283 #define INTERFACE_DVP0 0x02
284 #define INTERFACE_DVP1 0x03
285 #define INTERFACE_DFP_HIGH 0x04
286 #define INTERFACE_DFP_LOW 0x05
287 #define INTERFACE_DFP 0x06
288 #define INTERFACE_LVDS0 0x07
289 #define INTERFACE_LVDS1 0x08
290 #define INTERFACE_LVDS0LVDS1 0x09
291 #define INTERFACE_TMDS 0x0A
293 #define HW_LAYOUT_LCD_ONLY 0x01
294 #define HW_LAYOUT_DVI_ONLY 0x02
295 #define HW_LAYOUT_LCD_DVI 0x03
296 #define HW_LAYOUT_LCD1_LCD2 0x04
297 #define HW_LAYOUT_LCD_EXTERNAL_LCD2 0x10
299 /* Definition Refresh Rate */
300 #define REFRESH_50 50
301 #define REFRESH_60 60
302 #define REFRESH_75 75
303 #define REFRESH_85 85
304 #define REFRESH_100 100
305 #define REFRESH_120 120
307 /* Definition Sync Polarity*/
311 /*480x640@60 Sync Polarity (GTF)
313 #define M480X640_R60_HSP NEGATIVE
314 #define M480X640_R60_VSP POSITIVE
316 /*640x480@60 Sync Polarity (VESA Mode)
318 #define M640X480_R60_HSP NEGATIVE
319 #define M640X480_R60_VSP NEGATIVE
321 /*640x480@75 Sync Polarity (VESA Mode)
323 #define M640X480_R75_HSP NEGATIVE
324 #define M640X480_R75_VSP NEGATIVE
326 /*640x480@85 Sync Polarity (VESA Mode)
328 #define M640X480_R85_HSP NEGATIVE
329 #define M640X480_R85_VSP NEGATIVE
331 /*640x480@100 Sync Polarity (GTF Mode)
333 #define M640X480_R100_HSP NEGATIVE
334 #define M640X480_R100_VSP POSITIVE
336 /*640x480@120 Sync Polarity (GTF Mode)
338 #define M640X480_R120_HSP NEGATIVE
339 #define M640X480_R120_VSP POSITIVE
341 /*720x480@60 Sync Polarity (GTF Mode)
343 #define M720X480_R60_HSP NEGATIVE
344 #define M720X480_R60_VSP POSITIVE
346 /*720x576@60 Sync Polarity (GTF Mode)
348 #define M720X576_R60_HSP NEGATIVE
349 #define M720X576_R60_VSP POSITIVE
351 /*800x600@60 Sync Polarity (VESA Mode)
353 #define M800X600_R60_HSP POSITIVE
354 #define M800X600_R60_VSP POSITIVE
356 /*800x600@75 Sync Polarity (VESA Mode)
358 #define M800X600_R75_HSP POSITIVE
359 #define M800X600_R75_VSP POSITIVE
361 /*800x600@85 Sync Polarity (VESA Mode)
363 #define M800X600_R85_HSP POSITIVE
364 #define M800X600_R85_VSP POSITIVE
366 /*800x600@100 Sync Polarity (GTF Mode)
368 #define M800X600_R100_HSP NEGATIVE
369 #define M800X600_R100_VSP POSITIVE
371 /*800x600@120 Sync Polarity (GTF Mode)
373 #define M800X600_R120_HSP NEGATIVE
374 #define M800X600_R120_VSP POSITIVE
376 /*800x480@60 Sync Polarity (CVT Mode)
378 #define M800X480_R60_HSP NEGATIVE
379 #define M800X480_R60_VSP POSITIVE
381 /*848x480@60 Sync Polarity (CVT Mode)
383 #define M848X480_R60_HSP NEGATIVE
384 #define M848X480_R60_VSP POSITIVE
386 /*852x480@60 Sync Polarity (GTF Mode)
388 #define M852X480_R60_HSP NEGATIVE
389 #define M852X480_R60_VSP POSITIVE
391 /*1024x512@60 Sync Polarity (GTF Mode)
393 #define M1024X512_R60_HSP NEGATIVE
394 #define M1024X512_R60_VSP POSITIVE
396 /*1024x600@60 Sync Polarity (GTF Mode)
398 #define M1024X600_R60_HSP NEGATIVE
399 #define M1024X600_R60_VSP POSITIVE
401 /*1024x768@60 Sync Polarity (VESA Mode)
403 #define M1024X768_R60_HSP NEGATIVE
404 #define M1024X768_R60_VSP NEGATIVE
406 /*1024x768@75 Sync Polarity (VESA Mode)
408 #define M1024X768_R75_HSP POSITIVE
409 #define M1024X768_R75_VSP POSITIVE
411 /*1024x768@85 Sync Polarity (VESA Mode)
413 #define M1024X768_R85_HSP POSITIVE
414 #define M1024X768_R85_VSP POSITIVE
416 /*1024x768@100 Sync Polarity (GTF Mode)
418 #define M1024X768_R100_HSP NEGATIVE
419 #define M1024X768_R100_VSP POSITIVE
421 /*1152x864@75 Sync Polarity (VESA Mode)
423 #define M1152X864_R75_HSP POSITIVE
424 #define M1152X864_R75_VSP POSITIVE
426 /*1280x720@60 Sync Polarity (GTF Mode)
428 #define M1280X720_R60_HSP NEGATIVE
429 #define M1280X720_R60_VSP POSITIVE
431 /* 1280x768@50 Sync Polarity (GTF Mode) */
432 #define M1280X768_R50_HSP NEGATIVE
433 #define M1280X768_R50_VSP POSITIVE
435 /*1280x768@60 Sync Polarity (GTF Mode)
437 #define M1280X768_R60_HSP NEGATIVE
438 #define M1280X768_R60_VSP POSITIVE
440 /*1280x800@60 Sync Polarity (CVT Mode)
442 #define M1280X800_R60_HSP NEGATIVE
443 #define M1280X800_R60_VSP POSITIVE
445 /*1280x960@60 Sync Polarity (VESA Mode)
447 #define M1280X960_R60_HSP POSITIVE
448 #define M1280X960_R60_VSP POSITIVE
450 /*1280x1024@60 Sync Polarity (VESA Mode)
452 #define M1280X1024_R60_HSP POSITIVE
453 #define M1280X1024_R60_VSP POSITIVE
455 /* 1360x768@60 Sync Polarity (CVT Mode) */
456 #define M1360X768_R60_HSP POSITIVE
457 #define M1360X768_R60_VSP POSITIVE
459 /* 1360x768@60 Sync Polarity (CVT Reduce Blanking Mode) */
460 #define M1360X768_RB_R60_HSP POSITIVE
461 #define M1360X768_RB_R60_VSP NEGATIVE
463 /* 1368x768@50 Sync Polarity (GTF Mode) */
464 #define M1368X768_R50_HSP NEGATIVE
465 #define M1368X768_R50_VSP POSITIVE
467 /* 1368x768@60 Sync Polarity (VESA Mode) */
468 #define M1368X768_R60_HSP NEGATIVE
469 #define M1368X768_R60_VSP POSITIVE
471 /*1280x1024@75 Sync Polarity (VESA Mode)
473 #define M1280X1024_R75_HSP POSITIVE
474 #define M1280X1024_R75_VSP POSITIVE
476 /*1280x1024@85 Sync Polarity (VESA Mode)
478 #define M1280X1024_R85_HSP POSITIVE
479 #define M1280X1024_R85_VSP POSITIVE
481 /*1440x1050@60 Sync Polarity (GTF Mode)
483 #define M1440X1050_R60_HSP NEGATIVE
484 #define M1440X1050_R60_VSP POSITIVE
486 /*1600x1200@60 Sync Polarity (VESA Mode)
488 #define M1600X1200_R60_HSP POSITIVE
489 #define M1600X1200_R60_VSP POSITIVE
491 /*1600x1200@75 Sync Polarity (VESA Mode)
493 #define M1600X1200_R75_HSP POSITIVE
494 #define M1600X1200_R75_VSP POSITIVE
496 /* 1680x1050@60 Sync Polarity (CVT Mode) */
497 #define M1680x1050_R60_HSP NEGATIVE
498 #define M1680x1050_R60_VSP NEGATIVE
500 /* 1680x1050@60 Sync Polarity (CVT Reduce Blanking Mode) */
501 #define M1680x1050_RB_R60_HSP POSITIVE
502 #define M1680x1050_RB_R60_VSP NEGATIVE
504 /* 1680x1050@75 Sync Polarity (CVT Mode) */
505 #define M1680x1050_R75_HSP NEGATIVE
506 #define M1680x1050_R75_VSP POSITIVE
508 /*1920x1080@60 Sync Polarity (CVT Mode)
510 #define M1920X1080_R60_HSP NEGATIVE
511 #define M1920X1080_R60_VSP POSITIVE
513 /* 1920x1080@60 Sync Polarity (CVT Reduce Blanking Mode) */
514 #define M1920X1080_RB_R60_HSP POSITIVE
515 #define M1920X1080_RB_R60_VSP NEGATIVE
517 /*1920x1440@60 Sync Polarity (VESA Mode)
519 #define M1920X1440_R60_HSP NEGATIVE
520 #define M1920X1440_R60_VSP POSITIVE
522 /*1920x1440@75 Sync Polarity (VESA Mode)
524 #define M1920X1440_R75_HSP NEGATIVE
525 #define M1920X1440_R75_VSP POSITIVE
528 /* 1400x1050@60 Sync Polarity (VESA Mode) */
529 #define M1400X1050_R60_HSP NEGATIVE
530 #define M1400X1050_R60_VSP NEGATIVE
533 /* 1400x1050@60 Sync Polarity (CVT Mode) */
534 #define M1400X1050_R60_HSP NEGATIVE
535 #define M1400X1050_R60_VSP POSITIVE
537 /* 1400x1050@60 Sync Polarity (CVT Reduce Blanking Mode) */
538 #define M1400X1050_RB_R60_HSP POSITIVE
539 #define M1400X1050_RB_R60_VSP NEGATIVE
541 /* 1400x1050@75 Sync Polarity (CVT Mode) */
542 #define M1400X1050_R75_HSP NEGATIVE
543 #define M1400X1050_R75_VSP POSITIVE
545 /* 960x600@60 Sync Polarity (CVT Mode) */
546 #define M960X600_R60_HSP NEGATIVE
547 #define M960X600_R60_VSP POSITIVE
549 /* 1000x600@60 Sync Polarity (GTF Mode) */
550 #define M1000X600_R60_HSP NEGATIVE
551 #define M1000X600_R60_VSP POSITIVE
553 /* 1024x576@60 Sync Polarity (GTF Mode) */
554 #define M1024X576_R60_HSP NEGATIVE
555 #define M1024X576_R60_VSP POSITIVE
557 /*1024x600@60 Sync Polarity (GTF Mode)*/
558 #define M1024X600_R60_HSP NEGATIVE
559 #define M1024X600_R60_VSP POSITIVE
561 /* 1088x612@60 Sync Polarity (CVT Mode) */
562 #define M1088X612_R60_HSP NEGATIVE
563 #define M1088X612_R60_VSP POSITIVE
565 /* 1152x720@60 Sync Polarity (CVT Mode) */
566 #define M1152X720_R60_HSP NEGATIVE
567 #define M1152X720_R60_VSP POSITIVE
569 /* 1200x720@60 Sync Polarity (GTF Mode) */
570 #define M1200X720_R60_HSP NEGATIVE
571 #define M1200X720_R60_VSP POSITIVE
573 /* 1200x900@60 Sync Polarity (DCON) */
574 #define M1200X900_R60_HSP NEGATIVE
575 #define M1200X900_R60_VSP NEGATIVE
577 /* 1280x600@60 Sync Polarity (GTF Mode) */
578 #define M1280x600_R60_HSP NEGATIVE
579 #define M1280x600_R60_VSP POSITIVE
581 /* 1280x720@50 Sync Polarity (GTF Mode) */
582 #define M1280X720_R50_HSP NEGATIVE
583 #define M1280X720_R50_VSP POSITIVE
585 /* 1280x720@60 Sync Polarity (CEA Mode) */
586 #define M1280X720_CEA_R60_HSP POSITIVE
587 #define M1280X720_CEA_R60_VSP POSITIVE
589 /* 1440x900@60 Sync Polarity (CVT Mode) */
590 #define M1440X900_R60_HSP NEGATIVE
591 #define M1440X900_R60_VSP POSITIVE
593 /* 1440x900@75 Sync Polarity (CVT Mode) */
594 #define M1440X900_R75_HSP NEGATIVE
595 #define M1440X900_R75_VSP POSITIVE
597 /* 1440x900@60 Sync Polarity (CVT Reduce Blanking Mode) */
598 #define M1440X900_RB_R60_HSP POSITIVE
599 #define M1440X900_RB_R60_VSP NEGATIVE
601 /* 1600x900@60 Sync Polarity (CVT Mode) */
602 #define M1600X900_R60_HSP NEGATIVE
603 #define M1600X900_R60_VSP POSITIVE
605 /* 1600x900@60 Sync Polarity (CVT Reduce Blanking Mode) */
606 #define M1600X900_RB_R60_HSP POSITIVE
607 #define M1600X900_RB_R60_VSP NEGATIVE
609 /* 1600x1024@60 Sync Polarity (GTF Mode) */
610 #define M1600X1024_R60_HSP NEGATIVE
611 #define M1600X1024_R60_VSP POSITIVE
613 /* 1792x1344@60 Sync Polarity (DMT Mode) */
614 #define M1792x1344_R60_HSP NEGATIVE
615 #define M1792x1344_R60_VSP POSITIVE
617 /* 1856x1392@60 Sync Polarity (DMT Mode) */
618 #define M1856x1392_R60_HSP NEGATIVE
619 #define M1856x1392_R60_VSP POSITIVE
621 /* 1920x1200@60 Sync Polarity (CVT Mode) */
622 #define M1920X1200_R60_HSP NEGATIVE
623 #define M1920X1200_R60_VSP POSITIVE
625 /* 1920x1200@60 Sync Polarity (CVT Reduce Blanking Mode) */
626 #define M1920X1200_RB_R60_HSP POSITIVE
627 #define M1920X1200_RB_R60_VSP NEGATIVE
629 /* 1920x1080@60 Sync Polarity (CEA Mode) */
630 #define M1920X1080_CEA_R60_HSP POSITIVE
631 #define M1920X1080_CEA_R60_VSP POSITIVE
633 /* 2048x1536@60 Sync Polarity (CVT Mode) */
634 #define M2048x1536_R60_HSP NEGATIVE
635 #define M2048x1536_R60_VSP POSITIVE
637 /* define PLL index: */
638 #define CLK_25_175M 25175000
639 #define CLK_26_880M 26880000
640 #define CLK_29_581M 29581000
641 #define CLK_31_490M 31490000
642 #define CLK_31_500M 31500000
643 #define CLK_31_728M 31728000
644 #define CLK_32_668M 32688000
645 #define CLK_36_000M 36000000
646 #define CLK_40_000M 40000000
647 #define CLK_41_291M 41291000
648 #define CLK_43_163M 43163000
649 #define CLK_45_250M 45250000 /* 45.46MHz */
650 #define CLK_46_000M 46000000
651 #define CLK_46_996M 46996000
652 #define CLK_48_000M 48000000
653 #define CLK_48_875M 48875000
654 #define CLK_49_500M 49500000
655 #define CLK_52_406M 52406000
656 #define CLK_52_977M 52977000
657 #define CLK_56_250M 56250000
658 #define CLK_57_275M 57275000
659 #define CLK_60_466M 60466000
660 #define CLK_61_500M 61500000
661 #define CLK_65_000M 65000000
662 #define CLK_65_178M 65178000
663 #define CLK_66_750M 66750000 /* 67.116MHz */
664 #define CLK_68_179M 68179000
665 #define CLK_69_924M 69924000
666 #define CLK_70_159M 70159000
667 #define CLK_72_000M 72000000
668 #define CLK_74_270M 74270000
669 #define CLK_78_750M 78750000
670 #define CLK_80_136M 80136000
671 #define CLK_83_375M 83375000
672 #define CLK_83_950M 83950000
673 #define CLK_84_750M 84750000 /* 84.537Mhz */
674 #define CLK_85_860M 85860000
675 #define CLK_88_750M 88750000
676 #define CLK_94_500M 94500000
677 #define CLK_97_750M 97750000
678 #define CLK_101_000M 101000000
679 #define CLK_106_500M 106500000
680 #define CLK_108_000M 108000000
681 #define CLK_113_309M 113309000
682 #define CLK_118_840M 118840000
683 #define CLK_119_000M 119000000
684 #define CLK_121_750M 121750000 /* 121.704MHz */
685 #define CLK_125_104M 125104000
686 #define CLK_133_308M 133308000
687 #define CLK_135_000M 135000000
688 #define CLK_136_700M 136700000
689 #define CLK_138_400M 138400000
690 #define CLK_146_760M 146760000
691 #define CLK_148_500M 148500000
693 #define CLK_153_920M 153920000
694 #define CLK_156_000M 156000000
695 #define CLK_157_500M 157500000
696 #define CLK_162_000M 162000000
697 #define CLK_187_000M 187000000
698 #define CLK_193_295M 193295000
699 #define CLK_202_500M 202500000
700 #define CLK_204_000M 204000000
701 #define CLK_218_500M 218500000
702 #define CLK_234_000M 234000000
703 #define CLK_267_250M 267250000
704 #define CLK_297_500M 297500000
705 #define CLK_74_481M 74481000
706 #define CLK_172_798M 172798000
707 #define CLK_122_614M 122614000
711 #define CLE266_PLL_25_175M 0x0000C763
712 #define CLE266_PLL_26_880M 0x0000440F
713 #define CLE266_PLL_29_581M 0x00008421
714 #define CLE266_PLL_31_490M 0x00004721
715 #define CLE266_PLL_31_500M 0x0000C3B5
716 #define CLE266_PLL_31_728M 0x0000471F
717 #define CLE266_PLL_32_668M 0x0000C449
718 #define CLE266_PLL_36_000M 0x0000C5E5
719 #define CLE266_PLL_40_000M 0x0000C459
720 #define CLE266_PLL_41_291M 0x00004417
721 #define CLE266_PLL_43_163M 0x0000C579
722 #define CLE266_PLL_45_250M 0x0000C57F /* 45.46MHz */
723 #define CLE266_PLL_46_000M 0x0000875A
724 #define CLE266_PLL_46_996M 0x0000C4E9
725 #define CLE266_PLL_48_000M 0x00001443
726 #define CLE266_PLL_48_875M 0x00001D63
727 #define CLE266_PLL_49_500M 0x00008653
728 #define CLE266_PLL_52_406M 0x0000C475
729 #define CLE266_PLL_52_977M 0x00004525
730 #define CLE266_PLL_56_250M 0x000047B7
731 #define CLE266_PLL_60_466M 0x0000494C
732 #define CLE266_PLL_61_500M 0x00001456
733 #define CLE266_PLL_65_000M 0x000086ED
734 #define CLE266_PLL_65_178M 0x0000855B
735 #define CLE266_PLL_66_750M 0x0000844B /* 67.116MHz */
736 #define CLE266_PLL_68_179M 0x00000413
737 #define CLE266_PLL_69_924M 0x00001153
738 #define CLE266_PLL_70_159M 0x00001462
739 #define CLE266_PLL_72_000M 0x00001879
740 #define CLE266_PLL_74_270M 0x00004853
741 #define CLE266_PLL_78_750M 0x00004321
742 #define CLE266_PLL_80_136M 0x0000051C
743 #define CLE266_PLL_83_375M 0x0000C25D
744 #define CLE266_PLL_83_950M 0x00000729
745 #define CLE266_PLL_84_750M 0x00008576 /* 84.537MHz */
746 #define CLE266_PLL_85_860M 0x00004754
747 #define CLE266_PLL_88_750M 0x0000051F
748 #define CLE266_PLL_94_500M 0x00000521
749 #define CLE266_PLL_97_750M 0x00004652
750 #define CLE266_PLL_101_000M 0x0000497F
751 #define CLE266_PLL_106_500M 0x00008477 /* 106.491463 MHz */
752 #define CLE266_PLL_108_000M 0x00008479
753 #define CLE266_PLL_113_309M 0x00000C5F
754 #define CLE266_PLL_118_840M 0x00004553
755 #define CLE266_PLL_119_000M 0x00000D6C
756 #define CLE266_PLL_121_750M 0x00004555 /* 121.704MHz */
757 #define CLE266_PLL_125_104M 0x000006B5
758 #define CLE266_PLL_133_308M 0x0000465F
759 #define CLE266_PLL_135_000M 0x0000455E
760 #define CLE266_PLL_136_700M 0x00000C73
761 #define CLE266_PLL_138_400M 0x00000957
762 #define CLE266_PLL_146_760M 0x00004567
763 #define CLE266_PLL_148_500M 0x00000853
764 #define CLE266_PLL_153_920M 0x00000856
765 #define CLE266_PLL_156_000M 0x0000456D
766 #define CLE266_PLL_157_500M 0x000005B7
767 #define CLE266_PLL_162_000M 0x00004571
768 #define CLE266_PLL_187_000M 0x00000976
769 #define CLE266_PLL_193_295M 0x0000086C
770 #define CLE266_PLL_202_500M 0x00000763
771 #define CLE266_PLL_204_000M 0x00000764
772 #define CLE266_PLL_218_500M 0x0000065C
773 #define CLE266_PLL_234_000M 0x00000662
774 #define CLE266_PLL_267_250M 0x00000670
775 #define CLE266_PLL_297_500M 0x000005E6
776 #define CLE266_PLL_74_481M 0x0000051A
777 #define CLE266_PLL_172_798M 0x00004579
778 #define CLE266_PLL_122_614M 0x0000073C
782 #define K800_PLL_25_175M 0x00539001
783 #define K800_PLL_26_880M 0x001C8C80
784 #define K800_PLL_29_581M 0x00409080
785 #define K800_PLL_31_490M 0x006F9001
786 #define K800_PLL_31_500M 0x008B9002
787 #define K800_PLL_31_728M 0x00AF9003
788 #define K800_PLL_32_668M 0x00909002
789 #define K800_PLL_36_000M 0x009F9002
790 #define K800_PLL_40_000M 0x00578C02
791 #define K800_PLL_41_291M 0x00438C01
792 #define K800_PLL_43_163M 0x00778C03
793 #define K800_PLL_45_250M 0x007D8C83 /* 45.46MHz */
794 #define K800_PLL_46_000M 0x00658C02
795 #define K800_PLL_46_996M 0x00818C83
796 #define K800_PLL_48_000M 0x00848C83
797 #define K800_PLL_48_875M 0x00508C81
798 #define K800_PLL_49_500M 0x00518C01
799 #define K800_PLL_52_406M 0x00738C02
800 #define K800_PLL_52_977M 0x00928C83
801 #define K800_PLL_56_250M 0x007C8C02
802 #define K800_PLL_60_466M 0x00A78C83
803 #define K800_PLL_61_500M 0x00AA8C83
804 #define K800_PLL_65_000M 0x006B8C01
805 #define K800_PLL_65_178M 0x00B48C83
806 #define K800_PLL_66_750M 0x00948C82 /* 67.116MHz */
807 #define K800_PLL_68_179M 0x00708C01
808 #define K800_PLL_69_924M 0x00C18C83
809 #define K800_PLL_70_159M 0x00C28C83
810 #define K800_PLL_72_000M 0x009F8C82
811 #define K800_PLL_74_270M 0x00ce0c03
812 #define K800_PLL_78_750M 0x00408801
813 #define K800_PLL_80_136M 0x00428801
814 #define K800_PLL_83_375M 0x005B0882
815 #define K800_PLL_83_950M 0x00738803
816 #define K800_PLL_84_750M 0x00748883 /* 84.477MHz */
817 #define K800_PLL_85_860M 0x00768883
818 #define K800_PLL_88_750M 0x007A8883
819 #define K800_PLL_94_500M 0x00828803
820 #define K800_PLL_97_750M 0x00878883
821 #define K800_PLL_101_000M 0x008B8883
822 #define K800_PLL_106_500M 0x00758882 /* 106.491463 MHz */
823 #define K800_PLL_108_000M 0x00778882
824 #define K800_PLL_113_309M 0x005D8881
825 #define K800_PLL_118_840M 0x00A48883
826 #define K800_PLL_119_000M 0x00838882
827 #define K800_PLL_121_750M 0x00A88883 /* 121.704MHz */
828 #define K800_PLL_125_104M 0x00688801
829 #define K800_PLL_133_308M 0x005D8801
830 #define K800_PLL_135_000M 0x001A4081
831 #define K800_PLL_136_700M 0x00BD8883
832 #define K800_PLL_138_400M 0x00728881
833 #define K800_PLL_146_760M 0x00CC8883
834 #define K800_PLL_148_500M 0x00ce0803
835 #define K800_PLL_153_920M 0x00548482
836 #define K800_PLL_156_000M 0x006B8483
837 #define K800_PLL_157_500M 0x00142080
838 #define K800_PLL_162_000M 0x006F8483
839 #define K800_PLL_187_000M 0x00818483
840 #define K800_PLL_193_295M 0x004F8481
841 #define K800_PLL_202_500M 0x00538481
842 #define K800_PLL_204_000M 0x008D8483
843 #define K800_PLL_218_500M 0x00978483
844 #define K800_PLL_234_000M 0x00608401
845 #define K800_PLL_267_250M 0x006E8481
846 #define K800_PLL_297_500M 0x00A48402
847 #define K800_PLL_74_481M 0x007B8C81
848 #define K800_PLL_172_798M 0x00778483
849 #define K800_PLL_122_614M 0x00878882
852 #define CX700_25_175M 0x008B1003
853 #define CX700_26_719M 0x00931003
854 #define CX700_26_880M 0x00941003
855 #define CX700_29_581M 0x00A49003
856 #define CX700_31_490M 0x00AE1003
857 #define CX700_31_500M 0x00AE1003
858 #define CX700_31_728M 0x00AF1003
859 #define CX700_32_668M 0x00B51003
860 #define CX700_36_000M 0x00C81003
861 #define CX700_40_000M 0x006E0C03
862 #define CX700_41_291M 0x00710C03
863 #define CX700_43_163M 0x00770C03
864 #define CX700_45_250M 0x007D0C03 /* 45.46MHz */
865 #define CX700_46_000M 0x007F0C03
866 #define CX700_46_996M 0x00818C83
867 #define CX700_48_000M 0x00840C03
868 #define CX700_48_875M 0x00508C81
869 #define CX700_49_500M 0x00880C03
870 #define CX700_52_406M 0x00730C02
871 #define CX700_52_977M 0x00920C03
872 #define CX700_56_250M 0x009B0C03
873 #define CX700_60_466M 0x00460C00
874 #define CX700_61_500M 0x00AA0C03
875 #define CX700_65_000M 0x006B0C01
876 #define CX700_65_178M 0x006B0C01
877 #define CX700_66_750M 0x00940C02 /*67.116MHz */
878 #define CX700_68_179M 0x00BC0C03
879 #define CX700_69_924M 0x00C10C03
880 #define CX700_70_159M 0x00C20C03
881 #define CX700_72_000M 0x009F0C02
882 #define CX700_74_270M 0x00CE0C03
883 #define CX700_74_481M 0x00CE0C03
884 #define CX700_78_750M 0x006C0803
885 #define CX700_80_136M 0x006E0803
886 #define CX700_83_375M 0x005B0882
887 #define CX700_83_950M 0x00730803
888 #define CX700_84_750M 0x00740803 /* 84.537Mhz */
889 #define CX700_85_860M 0x00760803
890 #define CX700_88_750M 0x00AC8885
891 #define CX700_94_500M 0x00820803
892 #define CX700_97_750M 0x00870803
893 #define CX700_101_000M 0x008B0803
894 #define CX700_106_500M 0x00750802
895 #define CX700_108_000M 0x00950803
896 #define CX700_113_309M 0x005D0801
897 #define CX700_118_840M 0x00A40803
898 #define CX700_119_000M 0x00830802
899 #define CX700_121_750M 0x00420800 /* 121.704MHz */
900 #define CX700_125_104M 0x00AD0803
901 #define CX700_133_308M 0x00930802
902 #define CX700_135_000M 0x00950802
903 #define CX700_136_700M 0x00BD0803
904 #define CX700_138_400M 0x00720801
905 #define CX700_146_760M 0x00CC0803
906 #define CX700_148_500M 0x00a40802
907 #define CX700_153_920M 0x00540402
908 #define CX700_156_000M 0x006B0403
909 #define CX700_157_500M 0x006C0403
910 #define CX700_162_000M 0x006F0403
911 #define CX700_172_798M 0x00770403
912 #define CX700_187_000M 0x00810403
913 #define CX700_193_295M 0x00850403
914 #define CX700_202_500M 0x008C0403
915 #define CX700_204_000M 0x008D0403
916 #define CX700_218_500M 0x00970403
917 #define CX700_234_000M 0x00600401
918 #define CX700_267_250M 0x00B90403
919 #define CX700_297_500M 0x00CE0403
920 #define CX700_122_614M 0x00870802
923 #define VX855_22_000M 0x007B1005
924 #define VX855_25_175M 0x008D1005
925 #define VX855_26_719M 0x00961005
926 #define VX855_26_880M 0x00961005
927 #define VX855_27_000M 0x00971005
928 #define VX855_29_581M 0x00A51005
929 #define VX855_29_829M 0x00641003
930 #define VX855_31_490M 0x00B01005
931 #define VX855_31_500M 0x00B01005
932 #define VX855_31_728M 0x008E1004
933 #define VX855_32_668M 0x00921004
934 #define VX855_36_000M 0x00A11004
935 #define VX855_40_000M 0x00700C05
936 #define VX855_41_291M 0x00730C05
937 #define VX855_43_163M 0x00790C05
938 #define VX855_45_250M 0x007F0C05 /* 45.46MHz */
939 #define VX855_46_000M 0x00670C04
940 #define VX855_46_996M 0x00690C04
941 #define VX855_48_000M 0x00860C05
942 #define VX855_48_875M 0x00890C05
943 #define VX855_49_500M 0x00530C03
944 #define VX855_52_406M 0x00580C03
945 #define VX855_52_977M 0x00940C05
946 #define VX855_56_250M 0x009D0C05
947 #define VX855_57_275M 0x009D8C85 /* Used by XO panel */
948 #define VX855_60_466M 0x00A90C05
949 #define VX855_61_500M 0x00AC0C05
950 #define VX855_65_000M 0x006D0C03
951 #define VX855_65_178M 0x00B60C05
952 #define VX855_66_750M 0x00700C03 /*67.116MHz */
953 #define VX855_67_295M 0x00BC0C05
954 #define VX855_68_179M 0x00BF0C05
955 #define VX855_68_369M 0x00BF0C05
956 #define VX855_69_924M 0x00C30C05
957 #define VX855_70_159M 0x00C30C05
958 #define VX855_72_000M 0x00A10C04
959 #define VX855_73_023M 0x00CC0C05
960 #define VX855_74_481M 0x00D10C05
961 #define VX855_78_750M 0x006E0805
962 #define VX855_79_466M 0x006F0805
963 #define VX855_80_136M 0x00700805
964 #define VX855_81_627M 0x00720805
965 #define VX855_83_375M 0x00750805
966 #define VX855_83_527M 0x00750805
967 #define VX855_83_950M 0x00750805
968 #define VX855_84_537M 0x00760805
969 #define VX855_84_750M 0x00760805 /* 84.537Mhz */
970 #define VX855_85_500M 0x00760805 /* 85.909080 MHz*/
971 #define VX855_85_860M 0x00760805
972 #define VX855_85_909M 0x00760805
973 #define VX855_88_750M 0x007C0805
974 #define VX855_89_489M 0x007D0805
975 #define VX855_94_500M 0x00840805
976 #define VX855_96_648M 0x00870805
977 #define VX855_97_750M 0x00890805
978 #define VX855_101_000M 0x008D0805
979 #define VX855_106_500M 0x00950805
980 #define VX855_108_000M 0x00970805
981 #define VX855_110_125M 0x00990805
982 #define VX855_112_000M 0x009D0805
983 #define VX855_113_309M 0x009F0805
984 #define VX855_115_000M 0x00A10805
985 #define VX855_118_840M 0x00A60805
986 #define VX855_119_000M 0x00A70805
987 #define VX855_121_750M 0x00AA0805 /* 121.704MHz */
988 #define VX855_122_614M 0x00AC0805
989 #define VX855_126_266M 0x00B10805
990 #define VX855_130_250M 0x00B60805 /* 130.250 */
991 #define VX855_135_000M 0x00BD0805
992 #define VX855_136_700M 0x00BF0805
993 #define VX855_137_750M 0x00C10805
994 #define VX855_138_400M 0x00C20805
995 #define VX855_144_300M 0x00CA0805
996 #define VX855_146_760M 0x00CE0805
997 #define VX855_148_500M 0x00D00805
998 #define VX855_153_920M 0x00540402
999 #define VX855_156_000M 0x006C0405
1000 #define VX855_156_867M 0x006E0405
1001 #define VX855_157_500M 0x006E0405
1002 #define VX855_162_000M 0x00710405
1003 #define VX855_172_798M 0x00790405
1004 #define VX855_187_000M 0x00830405
1005 #define VX855_193_295M 0x00870405
1006 #define VX855_202_500M 0x008E0405
1007 #define VX855_204_000M 0x008F0405
1008 #define VX855_218_500M 0x00990405
1009 #define VX855_229_500M 0x00A10405
1010 #define VX855_234_000M 0x00A40405
1011 #define VX855_267_250M 0x00BB0405
1012 #define VX855_297_500M 0x00D00405
1013 #define VX855_339_500M 0x00770005
1014 #define VX855_340_772M 0x00770005
1017 /* Definition CRTC Timing Index */
1018 #define H_TOTAL_INDEX 0
1019 #define H_ADDR_INDEX 1
1020 #define H_BLANK_START_INDEX 2
1021 #define H_BLANK_END_INDEX 3
1022 #define H_SYNC_START_INDEX 4
1023 #define H_SYNC_END_INDEX 5
1024 #define V_TOTAL_INDEX 6
1025 #define V_ADDR_INDEX 7
1026 #define V_BLANK_START_INDEX 8
1027 #define V_BLANK_END_INDEX 9
1028 #define V_SYNC_START_INDEX 10
1029 #define V_SYNC_END_INDEX 11
1030 #define H_TOTAL_SHADOW_INDEX 12
1031 #define H_BLANK_END_SHADOW_INDEX 13
1032 #define V_TOTAL_SHADOW_INDEX 14
1033 #define V_ADDR_SHADOW_INDEX 15
1034 #define V_BLANK_SATRT_SHADOW_INDEX 16
1035 #define V_BLANK_END_SHADOW_INDEX 17
1036 #define V_SYNC_SATRT_SHADOW_INDEX 18
1037 #define V_SYNC_END_SHADOW_INDEX 19
1039 /* Definition Video Mode Pixel Clock (picoseconds)
1041 #define RES_480X640_60HZ_PIXCLOCK 39722
1042 #define RES_640X480_60HZ_PIXCLOCK 39722
1043 #define RES_640X480_75HZ_PIXCLOCK 31747
1044 #define RES_640X480_85HZ_PIXCLOCK 27777
1045 #define RES_640X480_100HZ_PIXCLOCK 23168
1046 #define RES_640X480_120HZ_PIXCLOCK 19081
1047 #define RES_720X480_60HZ_PIXCLOCK 37020
1048 #define RES_720X576_60HZ_PIXCLOCK 30611
1049 #define RES_800X600_60HZ_PIXCLOCK 25000
1050 #define RES_800X600_75HZ_PIXCLOCK 20203
1051 #define RES_800X600_85HZ_PIXCLOCK 17777
1052 #define RES_800X600_100HZ_PIXCLOCK 14667
1053 #define RES_800X600_120HZ_PIXCLOCK 11912
1054 #define RES_800X480_60HZ_PIXCLOCK 33805
1055 #define RES_848X480_60HZ_PIXCLOCK 31756
1056 #define RES_856X480_60HZ_PIXCLOCK 31518
1057 #define RES_1024X512_60HZ_PIXCLOCK 24218
1058 #define RES_1024X600_60HZ_PIXCLOCK 20460
1059 #define RES_1024X768_60HZ_PIXCLOCK 15385
1060 #define RES_1024X768_75HZ_PIXCLOCK 12699
1061 #define RES_1024X768_85HZ_PIXCLOCK 10582
1062 #define RES_1024X768_100HZ_PIXCLOCK 8825
1063 #define RES_1152X864_75HZ_PIXCLOCK 9259
1064 #define RES_1280X768_60HZ_PIXCLOCK 12480
1065 #define RES_1280X800_60HZ_PIXCLOCK 11994
1066 #define RES_1280X960_60HZ_PIXCLOCK 9259
1067 #define RES_1280X1024_60HZ_PIXCLOCK 9260
1068 #define RES_1280X1024_75HZ_PIXCLOCK 7408
1069 #define RES_1280X768_85HZ_PIXCLOCK 6349
1070 #define RES_1440X1050_60HZ_PIXCLOCK 7993
1071 #define RES_1600X1200_60HZ_PIXCLOCK 6172
1072 #define RES_1600X1200_75HZ_PIXCLOCK 4938
1073 #define RES_1280X720_60HZ_PIXCLOCK 13426
1074 #define RES_1200X900_60HZ_PIXCLOCK 17459
1075 #define RES_1920X1080_60HZ_PIXCLOCK 5787
1076 #define RES_1400X1050_60HZ_PIXCLOCK 8214
1077 #define RES_1400X1050_75HZ_PIXCLOCK 6410
1078 #define RES_1368X768_60HZ_PIXCLOCK 11647
1079 #define RES_960X600_60HZ_PIXCLOCK 22099
1080 #define RES_1000X600_60HZ_PIXCLOCK 20834
1081 #define RES_1024X576_60HZ_PIXCLOCK 21278
1082 #define RES_1088X612_60HZ_PIXCLOCK 18877
1083 #define RES_1152X720_60HZ_PIXCLOCK 14981
1084 #define RES_1200X720_60HZ_PIXCLOCK 14253
1085 #define RES_1280X600_60HZ_PIXCLOCK 16260
1086 #define RES_1280X720_50HZ_PIXCLOCK 16538
1087 #define RES_1280X768_50HZ_PIXCLOCK 15342
1088 #define RES_1366X768_50HZ_PIXCLOCK 14301
1089 #define RES_1366X768_60HZ_PIXCLOCK 11646
1090 #define RES_1360X768_60HZ_PIXCLOCK 11799
1091 #define RES_1440X900_60HZ_PIXCLOCK 9390
1092 #define RES_1440X900_75HZ_PIXCLOCK 7315
1093 #define RES_1600X900_60HZ_PIXCLOCK 8415
1094 #define RES_1600X1024_60HZ_PIXCLOCK 7315
1095 #define RES_1680X1050_60HZ_PIXCLOCK 6814
1096 #define RES_1680X1050_75HZ_PIXCLOCK 5348
1097 #define RES_1792X1344_60HZ_PIXCLOCK 4902
1098 #define RES_1856X1392_60HZ_PIXCLOCK 4577
1099 #define RES_1920X1200_60HZ_PIXCLOCK 5173
1100 #define RES_1920X1440_60HZ_PIXCLOCK 4274
1101 #define RES_1920X1440_75HZ_PIXCLOCK 3367
1102 #define RES_2048X1536_60HZ_PIXCLOCK 3742
1104 #define RES_1360X768_RB_60HZ_PIXCLOCK 13889
1105 #define RES_1400X1050_RB_60HZ_PIXCLOCK 9901
1106 #define RES_1440X900_RB_60HZ_PIXCLOCK 11268
1107 #define RES_1600X900_RB_60HZ_PIXCLOCK 10230
1108 #define RES_1680X1050_RB_60HZ_PIXCLOCK 8403
1109 #define RES_1920X1080_RB_60HZ_PIXCLOCK 7225
1110 #define RES_1920X1200_RB_60HZ_PIXCLOCK 6497
1112 /* LCD display method
1114 #define LCD_EXPANDSION 0x00
1115 #define LCD_CENTERING 0x01
1119 #define LCD_OPENLDI 0x00
1120 #define LCD_SPWG 0x01
1122 /* Define display timing
1124 struct display_timing {
1127 u16 hor_blank_start;
1133 u16 ver_blank_start;
1139 struct crt_mode_table {
1142 int h_sync_polarity;
1143 int v_sync_polarity;
1144 struct display_timing crtc;
1154 #endif /* __SHARE_H__ */