2 * Xilinx TFT frame buffer driver
4 * Author: MontaVista Software, Inc.
7 * 2002-2007 (c) MontaVista Software, Inc.
8 * 2007 (c) Secret Lab Technologies, Ltd.
11 * This file is licensed under the terms of the GNU General Public License
12 * version 2. This program is licensed "as is" without any warranty of any
13 * kind, whether express or implied.
17 * This driver was based on au1100fb.c by MontaVista rewritten for 2.6
18 * by Embedded Alley Solutions <source@embeddedalley.com>, which in turn
19 * was based on skeletonfb.c, Skeleton for a frame buffer device by
23 #include <linux/device.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/version.h>
27 #include <linux/errno.h>
28 #include <linux/string.h>
31 #include <linux/init.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/of_device.h>
34 #include <linux/of_platform.h>
36 #include <linux/xilinxfb.h>
37 #include <linux/slab.h>
40 #define DRIVER_NAME "xilinxfb"
44 * Xilinx calls it "PLB TFT LCD Controller" though it can also be used for
45 * the VGA port on the Xilinx ML40x board. This is a hardware display
46 * controller for a 640x480 resolution TFT or VGA screen.
48 * The interface to the framebuffer is nice and simple. There are two
49 * control registers. The first tells the LCD interface where in memory
50 * the frame buffer is (only the 11 most significant bits are used, so
51 * don't start thinking about scrolling). The second allows the LCD to
52 * be turned on or off as well as rotated 180 degrees.
54 * In case of direct PLB access the second control register will be at
55 * an offset of 4 as compared to the DCR access where the offset is 1
56 * i.e. REG_CTRL. So this is taken care in the function
57 * xilinx_fb_out_be32 where it left shifts the offset 2 times in case of
63 #define REG_CTRL_ENABLE 0x0001
64 #define REG_CTRL_ROTATE 0x0002
67 * The hardware only handles a single mode: 640x480 24 bit true
68 * color. Each pixel gets a word (32 bits) of memory. Within each word,
69 * the 8 most significant bits are ignored, the next 8 bits are the red
70 * level, the next 8 bits are the green level and the 8 least
71 * significant bits are the blue level. Each row of the LCD uses 1024
72 * words, but only the first 640 pixels are displayed with the other 384
73 * words being ignored. There are 480 rows.
75 #define BYTES_PER_PIXEL 4
76 #define BITS_PER_PIXEL (BYTES_PER_PIXEL * 8)
82 #define PALETTE_ENTRIES_NO 16 /* passed to fb_alloc_cmap() */
85 * Default xilinxfb configuration
87 static struct xilinxfb_platform_data xilinx_fb_default_pdata = {
95 * Here are the default fb_fix_screeninfo and fb_var_screeninfo structures
97 static struct fb_fix_screeninfo xilinx_fb_fix = {
99 .type = FB_TYPE_PACKED_PIXELS,
100 .visual = FB_VISUAL_TRUECOLOR,
101 .accel = FB_ACCEL_NONE
104 static struct fb_var_screeninfo xilinx_fb_var = {
105 .bits_per_pixel = BITS_PER_PIXEL,
107 .red = { RED_SHIFT, 8, 0 },
108 .green = { GREEN_SHIFT, 8, 0 },
109 .blue = { BLUE_SHIFT, 8, 0 },
110 .transp = { 0, 0, 0 },
112 .activate = FB_ACTIVATE_NOW
116 #define PLB_ACCESS_FLAG 0x1 /* 1 = PLB, 0 = DCR */
118 struct xilinxfb_drvdata {
120 struct fb_info info; /* FB driver info record */
122 phys_addr_t regs_phys; /* phys. address of the control
124 void __iomem *regs; /* virt. address of the control
128 unsigned int dcr_len;
130 void *fb_virt; /* virt. address of the frame buffer */
131 dma_addr_t fb_phys; /* phys. address of the frame buffer */
132 int fb_alloced; /* Flag, was the fb memory alloced? */
134 u8 flags; /* features of the driver */
136 u32 reg_ctrl_default;
138 u32 pseudo_palette[PALETTE_ENTRIES_NO];
139 /* Fake palette of 16 colors */
142 #define to_xilinxfb_drvdata(_info) \
143 container_of(_info, struct xilinxfb_drvdata, info)
146 * The XPS TFT Controller can be accessed through PLB or DCR interface.
147 * To perform the read/write on the registers we need to check on
148 * which bus its connected and call the appropriate write API.
150 static void xilinx_fb_out_be32(struct xilinxfb_drvdata *drvdata, u32 offset,
153 if (drvdata->flags & PLB_ACCESS_FLAG)
154 out_be32(drvdata->regs + (offset << 2), val);
156 dcr_write(drvdata->dcr_host, offset, val);
161 xilinx_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
162 unsigned transp, struct fb_info *fbi)
164 u32 *palette = fbi->pseudo_palette;
166 if (regno >= PALETTE_ENTRIES_NO)
169 if (fbi->var.grayscale) {
170 /* Convert color to grayscale.
171 * grayscale = 0.30*R + 0.59*G + 0.11*B */
173 (red * 77 + green * 151 + blue * 28 + 127) >> 8;
176 /* fbi->fix.visual is always FB_VISUAL_TRUECOLOR */
178 /* We only handle 8 bits of each color. */
182 palette[regno] = (red << RED_SHIFT) | (green << GREEN_SHIFT) |
183 (blue << BLUE_SHIFT);
189 xilinx_fb_blank(int blank_mode, struct fb_info *fbi)
191 struct xilinxfb_drvdata *drvdata = to_xilinxfb_drvdata(fbi);
193 switch (blank_mode) {
194 case FB_BLANK_UNBLANK:
196 xilinx_fb_out_be32(drvdata, REG_CTRL, drvdata->reg_ctrl_default);
199 case FB_BLANK_NORMAL:
200 case FB_BLANK_VSYNC_SUSPEND:
201 case FB_BLANK_HSYNC_SUSPEND:
202 case FB_BLANK_POWERDOWN:
204 xilinx_fb_out_be32(drvdata, REG_CTRL, 0);
209 return 0; /* success */
212 static struct fb_ops xilinxfb_ops =
214 .owner = THIS_MODULE,
215 .fb_setcolreg = xilinx_fb_setcolreg,
216 .fb_blank = xilinx_fb_blank,
217 .fb_fillrect = cfb_fillrect,
218 .fb_copyarea = cfb_copyarea,
219 .fb_imageblit = cfb_imageblit,
222 /* ---------------------------------------------------------------------
223 * Bus independent setup/teardown
226 static int xilinxfb_assign(struct device *dev,
227 struct xilinxfb_drvdata *drvdata,
228 unsigned long physaddr,
229 struct xilinxfb_platform_data *pdata)
232 int fbsize = pdata->xvirt * pdata->yvirt * BYTES_PER_PIXEL;
234 if (drvdata->flags & PLB_ACCESS_FLAG) {
236 * Map the control registers in if the controller
237 * is on direct PLB interface.
239 if (!request_mem_region(physaddr, 8, DRIVER_NAME)) {
240 dev_err(dev, "Couldn't lock memory region at 0x%08lX\n",
246 drvdata->regs_phys = physaddr;
247 drvdata->regs = ioremap(physaddr, 8);
248 if (!drvdata->regs) {
249 dev_err(dev, "Couldn't lock memory region at 0x%08lX\n",
256 /* Allocate the framebuffer memory */
257 if (pdata->fb_phys) {
258 drvdata->fb_phys = pdata->fb_phys;
259 drvdata->fb_virt = ioremap(pdata->fb_phys, fbsize);
261 drvdata->fb_alloced = 1;
262 drvdata->fb_virt = dma_alloc_coherent(dev, PAGE_ALIGN(fbsize),
263 &drvdata->fb_phys, GFP_KERNEL);
266 if (!drvdata->fb_virt) {
267 dev_err(dev, "Could not allocate frame buffer memory\n");
269 if (drvdata->flags & PLB_ACCESS_FLAG)
275 /* Clear (turn to black) the framebuffer */
276 memset_io((void __iomem *)drvdata->fb_virt, 0, fbsize);
278 /* Tell the hardware where the frame buffer is */
279 xilinx_fb_out_be32(drvdata, REG_FB_ADDR, drvdata->fb_phys);
281 /* Turn on the display */
282 drvdata->reg_ctrl_default = REG_CTRL_ENABLE;
283 if (pdata->rotate_screen)
284 drvdata->reg_ctrl_default |= REG_CTRL_ROTATE;
285 xilinx_fb_out_be32(drvdata, REG_CTRL,
286 drvdata->reg_ctrl_default);
288 /* Fill struct fb_info */
289 drvdata->info.device = dev;
290 drvdata->info.screen_base = (void __iomem *)drvdata->fb_virt;
291 drvdata->info.fbops = &xilinxfb_ops;
292 drvdata->info.fix = xilinx_fb_fix;
293 drvdata->info.fix.smem_start = drvdata->fb_phys;
294 drvdata->info.fix.smem_len = fbsize;
295 drvdata->info.fix.line_length = pdata->xvirt * BYTES_PER_PIXEL;
297 drvdata->info.pseudo_palette = drvdata->pseudo_palette;
298 drvdata->info.flags = FBINFO_DEFAULT;
299 drvdata->info.var = xilinx_fb_var;
300 drvdata->info.var.height = pdata->screen_height_mm;
301 drvdata->info.var.width = pdata->screen_width_mm;
302 drvdata->info.var.xres = pdata->xres;
303 drvdata->info.var.yres = pdata->yres;
304 drvdata->info.var.xres_virtual = pdata->xvirt;
305 drvdata->info.var.yres_virtual = pdata->yvirt;
307 /* Allocate a colour map */
308 rc = fb_alloc_cmap(&drvdata->info.cmap, PALETTE_ENTRIES_NO, 0);
310 dev_err(dev, "Fail to allocate colormap (%d entries)\n",
315 /* Register new frame buffer */
316 rc = register_framebuffer(&drvdata->info);
318 dev_err(dev, "Could not register frame buffer\n");
322 if (drvdata->flags & PLB_ACCESS_FLAG) {
323 /* Put a banner in the log (for DEBUG) */
324 dev_dbg(dev, "regs: phys=%lx, virt=%p\n", physaddr,
327 /* Put a banner in the log (for DEBUG) */
328 dev_dbg(dev, "fb: phys=%llx, virt=%p, size=%x\n",
329 (unsigned long long)drvdata->fb_phys, drvdata->fb_virt, fbsize);
331 return 0; /* success */
334 fb_dealloc_cmap(&drvdata->info.cmap);
337 if (drvdata->fb_alloced)
338 dma_free_coherent(dev, PAGE_ALIGN(fbsize), drvdata->fb_virt,
341 iounmap(drvdata->fb_virt);
343 /* Turn off the display */
344 xilinx_fb_out_be32(drvdata, REG_CTRL, 0);
347 if (drvdata->flags & PLB_ACCESS_FLAG)
348 iounmap(drvdata->regs);
351 if (drvdata->flags & PLB_ACCESS_FLAG)
352 release_mem_region(physaddr, 8);
356 dev_set_drvdata(dev, NULL);
361 static int xilinxfb_release(struct device *dev)
363 struct xilinxfb_drvdata *drvdata = dev_get_drvdata(dev);
365 #if !defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_LOGO)
366 xilinx_fb_blank(VESA_POWERDOWN, &drvdata->info);
369 unregister_framebuffer(&drvdata->info);
371 fb_dealloc_cmap(&drvdata->info.cmap);
373 if (drvdata->fb_alloced)
374 dma_free_coherent(dev, PAGE_ALIGN(drvdata->info.fix.smem_len),
375 drvdata->fb_virt, drvdata->fb_phys);
377 iounmap(drvdata->fb_virt);
379 /* Turn off the display */
380 xilinx_fb_out_be32(drvdata, REG_CTRL, 0);
382 /* Release the resources, as allocated based on interface */
383 if (drvdata->flags & PLB_ACCESS_FLAG) {
384 iounmap(drvdata->regs);
385 release_mem_region(drvdata->regs_phys, 8);
387 dcr_unmap(drvdata->dcr_host, drvdata->dcr_len);
390 dev_set_drvdata(dev, NULL);
395 /* ---------------------------------------------------------------------
400 xilinxfb_of_probe(struct of_device *op, const struct of_device_id *match)
405 struct xilinxfb_platform_data pdata;
408 struct xilinxfb_drvdata *drvdata;
410 /* Copy with the default pdata (not a ptr reference!) */
411 pdata = xilinx_fb_default_pdata;
413 dev_dbg(&op->dev, "xilinxfb_of_probe(%p, %p)\n", op, match);
415 /* Allocate the driver data region */
416 drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL);
418 dev_err(&op->dev, "Couldn't allocate device private record\n");
423 * To check whether the core is connected directly to DCR or PLB
424 * interface and initialize the tft_access accordingly.
426 p = (u32 *)of_get_property(op->dev.of_node, "xlnx,dcr-splb-slave-if", NULL);
427 tft_access = p ? *p : 0;
430 * Fill the resource structure if its direct PLB interface
431 * otherwise fill the dcr_host structure.
434 drvdata->flags |= PLB_ACCESS_FLAG;
435 rc = of_address_to_resource(op->dev.of_node, 0, &res);
437 dev_err(&op->dev, "invalid address\n");
442 start = dcr_resource_start(op->dev.of_node, 0);
443 drvdata->dcr_len = dcr_resource_len(op->dev.of_node, 0);
444 drvdata->dcr_host = dcr_map(op->dev.of_node, start, drvdata->dcr_len);
445 if (!DCR_MAP_OK(drvdata->dcr_host)) {
446 dev_err(&op->dev, "invalid DCR address\n");
451 prop = of_get_property(op->dev.of_node, "phys-size", &size);
452 if ((prop) && (size >= sizeof(u32)*2)) {
453 pdata.screen_width_mm = prop[0];
454 pdata.screen_height_mm = prop[1];
457 prop = of_get_property(op->dev.of_node, "resolution", &size);
458 if ((prop) && (size >= sizeof(u32)*2)) {
459 pdata.xres = prop[0];
460 pdata.yres = prop[1];
463 prop = of_get_property(op->dev.of_node, "virtual-resolution", &size);
464 if ((prop) && (size >= sizeof(u32)*2)) {
465 pdata.xvirt = prop[0];
466 pdata.yvirt = prop[1];
469 if (of_find_property(op->dev.of_node, "rotate-display", NULL))
470 pdata.rotate_screen = 1;
472 dev_set_drvdata(&op->dev, drvdata);
473 return xilinxfb_assign(&op->dev, drvdata, res.start, &pdata);
480 static int __devexit xilinxfb_of_remove(struct of_device *op)
482 return xilinxfb_release(&op->dev);
485 /* Match table for of_platform binding */
486 static struct of_device_id xilinxfb_of_match[] __devinitdata = {
487 { .compatible = "xlnx,xps-tft-1.00.a", },
488 { .compatible = "xlnx,xps-tft-2.00.a", },
489 { .compatible = "xlnx,xps-tft-2.01.a", },
490 { .compatible = "xlnx,plb-tft-cntlr-ref-1.00.a", },
491 { .compatible = "xlnx,plb-dvi-cntlr-ref-1.00.c", },
494 MODULE_DEVICE_TABLE(of, xilinxfb_of_match);
496 static struct of_platform_driver xilinxfb_of_driver = {
497 .probe = xilinxfb_of_probe,
498 .remove = __devexit_p(xilinxfb_of_remove),
501 .owner = THIS_MODULE,
502 .of_match_table = xilinxfb_of_match,
507 /* ---------------------------------------------------------------------
508 * Module setup and teardown
514 return of_register_platform_driver(&xilinxfb_of_driver);
518 xilinxfb_cleanup(void)
520 of_unregister_platform_driver(&xilinxfb_of_driver);
523 module_init(xilinxfb_init);
524 module_exit(xilinxfb_cleanup);
526 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
527 MODULE_DESCRIPTION("Xilinx TFT frame buffer driver");
528 MODULE_LICENSE("GPL");