drivers/watchdog/coh901327_wdt.c

   1 /*
   2  * coh901327_wdt.c
   3  *
   4  * Copyright (C) 2008-2009 ST-Ericsson AB
   5  * License terms: GNU General Public License (GPL) version 2
   6  * Watchdog driver for the ST-Ericsson AB COH 901 327 IP core
   7  * Author: Linus Walleij <linus.walleij@stericsson.com>
   8  */
   9 #include <linux/module.h>
  10 #include <linux/types.h>
  11 #include <linux/watchdog.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/pm.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/io.h>
  16 #include <linux/bitops.h>
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/err.h>
  20
  21 #define DRV_NAME "WDOG COH 901 327"
  22
  23 /*
  24  * COH 901 327 register definitions
  25  */
  26
  27 /* WDOG_FEED Register 32bit (-/W) */
  28 #define U300_WDOG_FR                                                    0x00
  29 #define U300_WDOG_FR_FEED_RESTART_TIMER                                 0xFEEDU
  30 /* WDOG_TIMEOUT Register 32bit (R/W) */
  31 #define U300_WDOG_TR                                                    0x04
  32 #define U300_WDOG_TR_TIMEOUT_MASK                                       0x7FFFU
  33 /* WDOG_DISABLE1 Register 32bit (-/W) */
  34 #define U300_WDOG_D1R                                                   0x08
  35 #define U300_WDOG_D1R_DISABLE1_DISABLE_TIMER                            0x2BADU
  36 /* WDOG_DISABLE2 Register 32bit (R/W) */
  37 #define U300_WDOG_D2R                                                   0x0C
  38 #define U300_WDOG_D2R_DISABLE2_DISABLE_TIMER                            0xCAFEU
  39 #define U300_WDOG_D2R_DISABLE_STATUS_DISABLED                           0xDABEU
  40 #define U300_WDOG_D2R_DISABLE_STATUS_ENABLED                            0x0000U
  41 /* WDOG_STATUS Register 32bit (R/W) */
  42 #define U300_WDOG_SR                                                    0x10
  43 #define U300_WDOG_SR_STATUS_TIMED_OUT                                   0xCFE8U
  44 #define U300_WDOG_SR_STATUS_NORMAL                                      0x0000U
  45 #define U300_WDOG_SR_RESET_STATUS_RESET                                 0xE8B4U
  46 /* WDOG_COUNT Register 32bit (R/-) */
  47 #define U300_WDOG_CR                                                    0x14
  48 #define U300_WDOG_CR_VALID_IND                                          0x8000U
  49 #define U300_WDOG_CR_VALID_STABLE                                       0x0000U
  50 #define U300_WDOG_CR_COUNT_VALUE_MASK                                   0x7FFFU
  51 /* WDOG_JTAGOVR Register 32bit (R/W) */
  52 #define U300_WDOG_JOR                                                   0x18
  53 #define U300_WDOG_JOR_JTAG_MODE_IND                                     0x0002U
  54 #define U300_WDOG_JOR_JTAG_WATCHDOG_ENABLE                              0x0001U
  55 /* WDOG_RESTART Register 32bit (-/W) */
  56 #define U300_WDOG_RR                                                    0x1C
  57 #define U300_WDOG_RR_RESTART_VALUE_RESUME                               0xACEDU
  58 /* WDOG_IRQ_EVENT Register 32bit (R/W) */
  59 #define U300_WDOG_IER                                                   0x20
  60 #define U300_WDOG_IER_WILL_BARK_IRQ_EVENT_IND                           0x0001U
  61 #define U300_WDOG_IER_WILL_BARK_IRQ_ACK_ENABLE                          0x0001U
  62 /* WDOG_IRQ_MASK Register 32bit (R/W) */
  63 #define U300_WDOG_IMR                                                   0x24
  64 #define U300_WDOG_IMR_WILL_BARK_IRQ_ENABLE                              0x0001U
  65 /* WDOG_IRQ_FORCE Register 32bit (R/W) */
  66 #define U300_WDOG_IFR                                                   0x28
  67 #define U300_WDOG_IFR_WILL_BARK_IRQ_FORCE_ENABLE                        0x0001U
  68
  69 /* Default timeout in seconds = 1 minute */
  70 static unsigned int margin = 60;
  71 static resource_size_t phybase;
  72 static resource_size_t physize;
  73 static int irq;
  74 static void __iomem *virtbase;
  75 static struct device *parent;
  76
  77 static struct clk *clk;
  78
  79 /*
  80  * Enabling and disabling functions.
  81  */
  82 static void coh901327_enable(u16 timeout)
  83 {
  84         u16 val;
  85         unsigned long freq;
  86         unsigned long delay_ns;
  87
  88         /* Restart timer if it is disabled */
  89         val = readw(virtbase + U300_WDOG_D2R);
  90         if (val == U300_WDOG_D2R_DISABLE_STATUS_DISABLED)
  91                 writew(U300_WDOG_RR_RESTART_VALUE_RESUME,
  92                        virtbase + U300_WDOG_RR);
  93         /* Acknowledge any pending interrupt so it doesn't just fire off */
  94         writew(U300_WDOG_IER_WILL_BARK_IRQ_ACK_ENABLE,
  95                virtbase + U300_WDOG_IER);
  96         /*
  97          * The interrupt is cleared in the 32 kHz clock domain.
  98          * Wait 3 32 kHz cycles for it to take effect
  99          */
 100         freq = clk_get_rate(clk);
 101         delay_ns = DIV_ROUND_UP(1000000000, freq); /* Freq to ns and round up */
 102         delay_ns = 3 * delay_ns; /* Wait 3 cycles */
 103         ndelay(delay_ns);
 104         /* Enable the watchdog interrupt */
 105         writew(U300_WDOG_IMR_WILL_BARK_IRQ_ENABLE, virtbase + U300_WDOG_IMR);
 106         /* Activate the watchdog timer */
 107         writew(timeout, virtbase + U300_WDOG_TR);
 108         /* Start the watchdog timer */
 109         writew(U300_WDOG_FR_FEED_RESTART_TIMER, virtbase + U300_WDOG_FR);
 110         /*
 111          * Extra read so that this change propagate in the watchdog.
 112          */
 113         (void) readw(virtbase + U300_WDOG_CR);
 114         val = readw(virtbase + U300_WDOG_D2R);
 115         if (val != U300_WDOG_D2R_DISABLE_STATUS_ENABLED)
 116                 dev_err(parent,
 117                         "%s(): watchdog not enabled! D2R value %04x\n",
 118                         __func__, val);
 119 }
 120
 121 static void coh901327_disable(void)
 122 {
 123         u16 val;
 124
 125         /* Disable the watchdog interrupt if it is active */
 126         writew(0x0000U, virtbase + U300_WDOG_IMR);
 127         /* If the watchdog is currently enabled, attempt to disable it */
 128         val = readw(virtbase + U300_WDOG_D2R);
 129         if (val != U300_WDOG_D2R_DISABLE_STATUS_DISABLED) {
 130                 writew(U300_WDOG_D1R_DISABLE1_DISABLE_TIMER,
 131                        virtbase + U300_WDOG_D1R);
 132                 writew(U300_WDOG_D2R_DISABLE2_DISABLE_TIMER,
 133                        virtbase + U300_WDOG_D2R);
 134                 /* Write this twice (else problems occur) */
 135                 writew(U300_WDOG_D2R_DISABLE2_DISABLE_TIMER,
 136                        virtbase + U300_WDOG_D2R);
 137         }
 138         val = readw(virtbase + U300_WDOG_D2R);
 139         if (val != U300_WDOG_D2R_DISABLE_STATUS_DISABLED)
 140                 dev_err(parent,
 141                         "%s(): watchdog not disabled! D2R value %04x\n",
 142                         __func__, val);
 143 }
 144
 145 static int coh901327_start(struct watchdog_device *wdt_dev)
 146 {
 147         coh901327_enable(wdt_dev->timeout * 100);
 148         return 0;
 149 }
 150
 151 static int coh901327_stop(struct watchdog_device *wdt_dev)
 152 {
 153         coh901327_disable();
 154         return 0;
 155 }
 156
 157 static int coh901327_ping(struct watchdog_device *wdd)
 158 {
 159         /* Feed the watchdog */
 160         writew(U300_WDOG_FR_FEED_RESTART_TIMER,
 161                virtbase + U300_WDOG_FR);
 162         return 0;
 163 }
 164
 165 static int coh901327_settimeout(struct watchdog_device *wdt_dev,
 166                                 unsigned int time)
 167 {
 168         wdt_dev->timeout = time;
 169         /* Set new timeout value */
 170         writew(time * 100, virtbase + U300_WDOG_TR);
 171         /* Feed the dog */
 172         writew(U300_WDOG_FR_FEED_RESTART_TIMER,
 173                virtbase + U300_WDOG_FR);
 174         return 0;
 175 }
 176
 177 static unsigned int coh901327_gettimeleft(struct watchdog_device *wdt_dev)
 178 {
 179         u16 val;
 180
 181         /* Read repeatedly until the value is stable! */
 182         val = readw(virtbase + U300_WDOG_CR);
 183         while (val & U300_WDOG_CR_VALID_IND)
 184                 val = readw(virtbase + U300_WDOG_CR);
 185         val &= U300_WDOG_CR_COUNT_VALUE_MASK;
 186         if (val != 0)
 187                 val /= 100;
 188
 189         return val;
 190 }
 191
 192 /*
 193  * This interrupt occurs 10 ms before the watchdog WILL bark.
 194  */
 195 static irqreturn_t coh901327_interrupt(int irq, void *data)
 196 {
 197         u16 val;
 198
 199         /*
 200          * Ack IRQ? If this occurs we're FUBAR anyway, so
 201          * just acknowledge, disable the interrupt and await the imminent end.
 202          * If you at some point need a host of callbacks to be called
 203          * when the system is about to watchdog-reset, add them here!
 204          *
 205          * NOTE: on future versions of this IP-block, it will be possible
 206          * to prevent a watchdog reset by feeding the watchdog at this
 207          * point.
 208          */
 209         val = readw(virtbase + U300_WDOG_IER);
 210         if (val == U300_WDOG_IER_WILL_BARK_IRQ_EVENT_IND)
 211                 writew(U300_WDOG_IER_WILL_BARK_IRQ_ACK_ENABLE,
 212                        virtbase + U300_WDOG_IER);
 213         writew(0x0000U, virtbase + U300_WDOG_IMR);
 214         dev_crit(parent, "watchdog is barking!\n");
 215         return IRQ_HANDLED;
 216 }
 217
 218 static const struct watchdog_info coh901327_ident = {
 219         .options = WDIOF_CARDRESET | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
 220         .identity = DRV_NAME,
 221 };
 222
 223 static struct watchdog_ops coh901327_ops = {
 224         .owner = THIS_MODULE,
 225         .start = coh901327_start,
 226         .stop = coh901327_stop,
 227         .ping = coh901327_ping,
 228         .set_timeout = coh901327_settimeout,
 229         .get_timeleft = coh901327_gettimeleft,
 230 };
 231
 232 static struct watchdog_device coh901327_wdt = {
 233         .info = &coh901327_ident,
 234         .ops = &coh901327_ops,
 235         /*
 236          * Max timeout is 327 since the 10ms
 237          * timeout register is max
 238          * 0x7FFF = 327670ms ~= 327s.
 239          */
 240         .min_timeout = 0,
 241         .max_timeout = 327,
 242 };
 243
 244 static int __exit coh901327_remove(struct platform_device *pdev)
 245 {
 246         watchdog_unregister_device(&coh901327_wdt);
 247         coh901327_disable();
 248         free_irq(irq, pdev);
 249         clk_disable_unprepare(clk);
 250         clk_put(clk);
 251         iounmap(virtbase);
 252         release_mem_region(phybase, physize);
 253         return 0;
 254 }
 255
 256 static int __init coh901327_probe(struct platform_device *pdev)
 257 {
 258         int ret;
 259         u16 val;
 260         struct resource *res;
 261
 262         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 263         if (!res)
 264                 return -ENOENT;
 265
 266         parent = &pdev->dev;
 267         physize = resource_size(res);
 268         phybase = res->start;
 269
 270         if (request_mem_region(phybase, physize, DRV_NAME) == NULL) {
 271                 ret = -EBUSY;
 272                 goto out;
 273         }
 274
 275         virtbase = ioremap(phybase, physize);
 276         if (!virtbase) {
 277                 ret = -ENOMEM;
 278                 goto out_no_remap;
 279         }
 280
 281         clk = clk_get(&pdev->dev, NULL);
 282         if (IS_ERR(clk)) {
 283                 ret = PTR_ERR(clk);
 284                 dev_err(&pdev->dev, "could not get clock\n");
 285                 goto out_no_clk;
 286         }
 287         ret = clk_prepare_enable(clk);
 288         if (ret) {
 289                 dev_err(&pdev->dev, "could not prepare and enable clock\n");
 290                 goto out_no_clk_enable;
 291         }
 292
 293         val = readw(virtbase + U300_WDOG_SR);
 294         switch (val) {
 295         case U300_WDOG_SR_STATUS_TIMED_OUT:
 296                 dev_info(&pdev->dev,
 297                         "watchdog timed out since last chip reset!\n");
 298                 coh901327_wdt.bootstatus |= WDIOF_CARDRESET;
 299                 /* Status will be cleared below */
 300                 break;
 301         case U300_WDOG_SR_STATUS_NORMAL:
 302                 dev_info(&pdev->dev,
 303                         "in normal status, no timeouts have occurred.\n");
 304                 break;
 305         default:
 306                 dev_info(&pdev->dev,
 307                         "contains an illegal status code (%08x)\n", val);
 308                 break;
 309         }
 310
 311         val = readw(virtbase + U300_WDOG_D2R);
 312         switch (val) {
 313         case U300_WDOG_D2R_DISABLE_STATUS_DISABLED:
 314                 dev_info(&pdev->dev, "currently disabled.\n");
 315                 break;
 316         case U300_WDOG_D2R_DISABLE_STATUS_ENABLED:
 317                 dev_info(&pdev->dev,
 318                          "currently enabled! (disabling it now)\n");
 319                 coh901327_disable();
 320                 break;
 321         default:
 322                 dev_err(&pdev->dev,
 323                         "contains an illegal enable/disable code (%08x)\n",
 324                         val);
 325                 break;
 326         }
 327
 328         /* Reset the watchdog */
 329         writew(U300_WDOG_SR_RESET_STATUS_RESET, virtbase + U300_WDOG_SR);
 330
 331         irq = platform_get_irq(pdev, 0);
 332         if (request_irq(irq, coh901327_interrupt, 0,
 333                         DRV_NAME " Bark", pdev)) {
 334                 ret = -EIO;
 335                 goto out_no_irq;
 336         }
 337
 338         ret = watchdog_init_timeout(&coh901327_wdt, margin, &pdev->dev);
 339         if (ret < 0)
 340                 coh901327_wdt.timeout = 60;
 341
 342         coh901327_wdt.parent = &pdev->dev;
 343         ret = watchdog_register_device(&coh901327_wdt);
 344         if (ret)
 345                 goto out_no_wdog;
 346
 347         dev_info(&pdev->dev, "initialized. timer margin=%d sec\n", margin);
 348         return 0;
 349
 350 out_no_wdog:
 351         free_irq(irq, pdev);
 352 out_no_irq:
 353         clk_disable_unprepare(clk);
 354 out_no_clk_enable:
 355         clk_put(clk);
 356 out_no_clk:
 357         iounmap(virtbase);
 358 out_no_remap:
 359         release_mem_region(phybase, SZ_4K);
 360 out:
 361         return ret;
 362 }
 363
 364 #ifdef CONFIG_PM
 365
 366 static u16 wdogenablestore;
 367 static u16 irqmaskstore;
 368
 369 static int coh901327_suspend(struct platform_device *pdev, pm_message_t state)
 370 {
 371         irqmaskstore = readw(virtbase + U300_WDOG_IMR) & 0x0001U;
 372         wdogenablestore = readw(virtbase + U300_WDOG_D2R);
 373         /* If watchdog is on, disable it here and now */
 374         if (wdogenablestore == U300_WDOG_D2R_DISABLE_STATUS_ENABLED)
 375                 coh901327_disable();
 376         return 0;
 377 }
 378
 379 static int coh901327_resume(struct platform_device *pdev)
 380 {
 381         /* Restore the watchdog interrupt */
 382         writew(irqmaskstore, virtbase + U300_WDOG_IMR);
 383         if (wdogenablestore == U300_WDOG_D2R_DISABLE_STATUS_ENABLED) {
 384                 /* Restart the watchdog timer */
 385                 writew(U300_WDOG_RR_RESTART_VALUE_RESUME,
 386                        virtbase + U300_WDOG_RR);
 387                 writew(U300_WDOG_FR_FEED_RESTART_TIMER,
 388                        virtbase + U300_WDOG_FR);
 389         }
 390         return 0;
 391 }
 392 #else
 393 #define coh901327_suspend NULL
 394 #define coh901327_resume  NULL
 395 #endif
 396
 397 /*
 398  * Mistreating the watchdog is the only way to perform a software reset of the
 399  * system on EMP platforms. So we implement this and export a symbol for it.
 400  */
 401 void coh901327_watchdog_reset(void)
 402 {
 403         /* Enable even if on JTAG too */
 404         writew(U300_WDOG_JOR_JTAG_WATCHDOG_ENABLE,
 405                virtbase + U300_WDOG_JOR);
 406         /*
 407          * Timeout = 5s, we have to wait for the watchdog reset to
 408          * actually take place: the watchdog will be reloaded with the
 409          * default value immediately, so we HAVE to reboot and get back
 410          * into the kernel in 30s, or the device will reboot again!
 411          * The boot loader will typically deactivate the watchdog, so we
 412          * need time enough for the boot loader to get to the point of
 413          * deactivating the watchdog before it is shut down by it.
 414          *
 415          * NOTE: on future versions of the watchdog, this restriction is
 416          * gone: the watchdog will be reloaded with a default value (1 min)
 417          * instead of last value, and you can conveniently set the watchdog
 418          * timeout to 10ms (value = 1) without any problems.
 419          */
 420         coh901327_enable(500);
 421         /* Return and await doom */
 422 }
 423
 424 static const struct of_device_id coh901327_dt_match[] = {
 425         { .compatible = "stericsson,coh901327" },
 426         {},
 427 };
 428
 429 static struct platform_driver coh901327_driver = {
 430         .driver = {
 431                 .name   = "coh901327_wdog",
 432                 .of_match_table = coh901327_dt_match,
 433         },
 434         .remove         = __exit_p(coh901327_remove),
 435         .suspend        = coh901327_suspend,
 436         .resume         = coh901327_resume,
 437 };
 438
 439 module_platform_driver_probe(coh901327_driver, coh901327_probe);
 440
 441 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
 442 MODULE_DESCRIPTION("COH 901 327 Watchdog");
 443
 444 module_param(margin, uint, 0);
 445 MODULE_PARM_DESC(margin, "Watchdog margin in seconds (default 60s)");
 446
 447 MODULE_LICENSE("GPL");
 448 MODULE_ALIAS("platform:coh901327-watchdog");