2 * intel TCO Watchdog Driver
4 * (c) Copyright 2006-2009 Wim Van Sebroeck <wim@iguana.be>.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
12 * provide warranty for any of this software. This material is
13 * provided "AS-IS" and at no charge.
15 * The TCO watchdog is implemented in the following I/O controller hubs:
16 * (See the intel documentation on http://developer.intel.com.)
17 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
18 * document number 290687-002, 298242-027: 82801BA (ICH2)
19 * document number 290733-003, 290739-013: 82801CA (ICH3-S)
20 * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
21 * document number 290744-001, 290745-025: 82801DB (ICH4)
22 * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
23 * document number 273599-001, 273645-002: 82801E (C-ICH)
24 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
25 * document number 300641-004, 300884-013: 6300ESB
26 * document number 301473-002, 301474-026: 82801F (ICH6)
27 * document number 313082-001, 313075-006: 631xESB, 632xESB
28 * document number 307013-003, 307014-024: 82801G (ICH7)
29 * document number 313056-003, 313057-017: 82801H (ICH8)
30 * document number 316972-004, 316973-012: 82801I (ICH9)
31 * document number 319973-002, 319974-002: 82801J (ICH10)
32 * document number 322169-001, 322170-001: 5 Series, 3400 Series (PCH)
36 * Includes, defines, variables, module parameters, ...
39 /* Module and version information */
40 #define DRV_NAME "iTCO_wdt"
41 #define DRV_VERSION "1.05"
42 #define PFX DRV_NAME ": "
45 #include <linux/module.h> /* For module specific items */
46 #include <linux/moduleparam.h> /* For new moduleparam's */
47 #include <linux/types.h> /* For standard types (like size_t) */
48 #include <linux/errno.h> /* For the -ENODEV/... values */
49 #include <linux/kernel.h> /* For printk/panic/... */
50 #include <linux/miscdevice.h> /* For MODULE_ALIAS_MISCDEV
52 #include <linux/watchdog.h> /* For the watchdog specific items */
53 #include <linux/init.h> /* For __init/__exit/... */
54 #include <linux/fs.h> /* For file operations */
55 #include <linux/platform_device.h> /* For platform_driver framework */
56 #include <linux/pci.h> /* For pci functions */
57 #include <linux/ioport.h> /* For io-port access */
58 #include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
59 #include <linux/uaccess.h> /* For copy_to_user/put_user/... */
60 #include <linux/io.h> /* For inb/outb/... */
62 #include "iTCO_vendor.h"
64 /* TCO related info */
66 TCO_ICH = 0, /* ICH */
69 TCO_ICH2M, /* ICH2-M */
70 TCO_ICH3, /* ICH3-S */
71 TCO_ICH3M, /* ICH3-M */
73 TCO_ICH4M, /* ICH4-M */
75 TCO_ICH5, /* ICH5 & ICH5R */
76 TCO_6300ESB, /* 6300ESB */
77 TCO_ICH6, /* ICH6 & ICH6R */
78 TCO_ICH6M, /* ICH6-M */
79 TCO_ICH6W, /* ICH6W & ICH6RW */
80 TCO_631XESB, /* 631xESB/632xESB */
81 TCO_ICH7, /* ICH7 & ICH7R */
82 TCO_ICH7DH, /* ICH7DH */
83 TCO_ICH7M, /* ICH7-M & ICH7-U */
84 TCO_ICH7MDH, /* ICH7-M DH */
85 TCO_ICH8, /* ICH8 & ICH8R */
86 TCO_ICH8DH, /* ICH8DH */
87 TCO_ICH8DO, /* ICH8DO */
88 TCO_ICH8M, /* ICH8M */
89 TCO_ICH8ME, /* ICH8M-E */
91 TCO_ICH9R, /* ICH9R */
92 TCO_ICH9DH, /* ICH9DH */
93 TCO_ICH9DO, /* ICH9DO */
94 TCO_ICH9M, /* ICH9M */
95 TCO_ICH9ME, /* ICH9M-E */
96 TCO_ICH10, /* ICH10 */
97 TCO_ICH10R, /* ICH10R */
98 TCO_ICH10D, /* ICH10D */
99 TCO_ICH10DO, /* ICH10DO */
100 TCO_PCH, /* PCH Desktop Full Featured */
101 TCO_PCHM, /* PCH Mobile Full Featured */
102 TCO_PCHMSFF, /* PCH Mobile SFF Full Featured */
107 unsigned int iTCO_version;
108 } iTCO_chipset_info[] __devinitdata = {
118 {"ICH5 or ICH5R", 1},
120 {"ICH6 or ICH6R", 2},
122 {"ICH6W or ICH6RW", 2},
123 {"631xESB/632xESB", 2},
124 {"ICH7 or ICH7R", 2},
126 {"ICH7-M or ICH7-U", 2},
128 {"ICH8 or ICH8R", 2},
143 {"PCH Desktop Full Featured", 2},
144 {"PCH Mobile Full Featured", 2},
145 {"PCH Mobile SFF Full Featured", 2},
149 #define ITCO_PCI_DEVICE(dev, data) \
150 .vendor = PCI_VENDOR_ID_INTEL, \
152 .subvendor = PCI_ANY_ID, \
153 .subdevice = PCI_ANY_ID, \
159 * This data only exists for exporting the supported PCI ids
160 * via MODULE_DEVICE_TABLE. We do not actually register a
161 * pci_driver, because the I/O Controller Hub has also other
162 * functions that probably will be registered by other drivers.
164 static struct pci_device_id iTCO_wdt_pci_tbl[] = {
165 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AA_0, TCO_ICH)},
166 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AB_0, TCO_ICH0)},
167 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_0, TCO_ICH2)},
168 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_10, TCO_ICH2M)},
169 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_0, TCO_ICH3)},
170 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_12, TCO_ICH3M)},
171 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_0, TCO_ICH4)},
172 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_12, TCO_ICH4M)},
173 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801E_0, TCO_CICH)},
174 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801EB_0, TCO_ICH5)},
175 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB_1, TCO_6300ESB)},
176 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_0, TCO_ICH6)},
177 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_1, TCO_ICH6M)},
178 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_2, TCO_ICH6W)},
179 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB2_0, TCO_631XESB)},
180 { ITCO_PCI_DEVICE(0x2671, TCO_631XESB)},
181 { ITCO_PCI_DEVICE(0x2672, TCO_631XESB)},
182 { ITCO_PCI_DEVICE(0x2673, TCO_631XESB)},
183 { ITCO_PCI_DEVICE(0x2674, TCO_631XESB)},
184 { ITCO_PCI_DEVICE(0x2675, TCO_631XESB)},
185 { ITCO_PCI_DEVICE(0x2676, TCO_631XESB)},
186 { ITCO_PCI_DEVICE(0x2677, TCO_631XESB)},
187 { ITCO_PCI_DEVICE(0x2678, TCO_631XESB)},
188 { ITCO_PCI_DEVICE(0x2679, TCO_631XESB)},
189 { ITCO_PCI_DEVICE(0x267a, TCO_631XESB)},
190 { ITCO_PCI_DEVICE(0x267b, TCO_631XESB)},
191 { ITCO_PCI_DEVICE(0x267c, TCO_631XESB)},
192 { ITCO_PCI_DEVICE(0x267d, TCO_631XESB)},
193 { ITCO_PCI_DEVICE(0x267e, TCO_631XESB)},
194 { ITCO_PCI_DEVICE(0x267f, TCO_631XESB)},
195 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_0, TCO_ICH7)},
196 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_30, TCO_ICH7DH)},
197 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_1, TCO_ICH7M)},
198 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_31, TCO_ICH7MDH)},
199 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_0, TCO_ICH8)},
200 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_2, TCO_ICH8DH)},
201 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_3, TCO_ICH8DO)},
202 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_4, TCO_ICH8M)},
203 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_1, TCO_ICH8ME)},
204 { ITCO_PCI_DEVICE(0x2918, TCO_ICH9)},
205 { ITCO_PCI_DEVICE(0x2916, TCO_ICH9R)},
206 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_2, TCO_ICH9DH)},
207 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_4, TCO_ICH9DO)},
208 { ITCO_PCI_DEVICE(0x2919, TCO_ICH9M)},
209 { ITCO_PCI_DEVICE(0x2917, TCO_ICH9ME)},
210 { ITCO_PCI_DEVICE(0x3a18, TCO_ICH10)},
211 { ITCO_PCI_DEVICE(0x3a16, TCO_ICH10R)},
212 { ITCO_PCI_DEVICE(0x3a1a, TCO_ICH10D)},
213 { ITCO_PCI_DEVICE(0x3a14, TCO_ICH10DO)},
214 { ITCO_PCI_DEVICE(0x3b00, TCO_PCH)},
215 { ITCO_PCI_DEVICE(0x3b01, TCO_PCHM)},
216 { ITCO_PCI_DEVICE(0x3b0d, TCO_PCHMSFF)},
217 { 0, }, /* End of list */
219 MODULE_DEVICE_TABLE(pci, iTCO_wdt_pci_tbl);
221 /* Address definitions for the TCO */
222 /* TCO base address */
223 #define TCOBASE (iTCO_wdt_private.ACPIBASE + 0x60)
224 /* SMI Control and Enable Register */
225 #define SMI_EN (iTCO_wdt_private.ACPIBASE + 0x30)
227 #define TCO_RLD (TCOBASE + 0x00) /* TCO Timer Reload and Curr. Value */
228 #define TCOv1_TMR (TCOBASE + 0x01) /* TCOv1 Timer Initial Value */
229 #define TCO_DAT_IN (TCOBASE + 0x02) /* TCO Data In Register */
230 #define TCO_DAT_OUT (TCOBASE + 0x03) /* TCO Data Out Register */
231 #define TCO1_STS (TCOBASE + 0x04) /* TCO1 Status Register */
232 #define TCO2_STS (TCOBASE + 0x06) /* TCO2 Status Register */
233 #define TCO1_CNT (TCOBASE + 0x08) /* TCO1 Control Register */
234 #define TCO2_CNT (TCOBASE + 0x0a) /* TCO2 Control Register */
235 #define TCOv2_TMR (TCOBASE + 0x12) /* TCOv2 Timer Initial Value */
237 /* internal variables */
238 static unsigned long is_active;
239 static char expect_release;
240 static struct { /* this is private data for the iTCO_wdt device */
241 /* TCO version/generation */
242 unsigned int iTCO_version;
243 /* The cards ACPIBASE address (TCOBASE = ACPIBASE+0x60) */
244 unsigned long ACPIBASE;
245 /* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2)*/
246 unsigned long __iomem *gcs;
247 /* the lock for io operations */
250 struct pci_dev *pdev;
253 /* the watchdog platform device */
254 static struct platform_device *iTCO_wdt_platform_device;
256 /* module parameters */
257 #define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */
258 static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
259 module_param(heartbeat, int, 0);
260 MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. "
261 "(2<heartbeat<39 (TCO v1) or 613 (TCO v2), default="
262 __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
264 static int nowayout = WATCHDOG_NOWAYOUT;
265 module_param(nowayout, int, 0);
266 MODULE_PARM_DESC(nowayout,
267 "Watchdog cannot be stopped once started (default="
268 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
271 * Some TCO specific functions
274 static inline unsigned int seconds_to_ticks(int seconds)
276 /* the internal timer is stored as ticks which decrement
277 * every 0.6 seconds */
278 return (seconds * 10) / 6;
281 static void iTCO_wdt_set_NO_REBOOT_bit(void)
285 /* Set the NO_REBOOT bit: this disables reboots */
286 if (iTCO_wdt_private.iTCO_version == 2) {
287 val32 = readl(iTCO_wdt_private.gcs);
289 writel(val32, iTCO_wdt_private.gcs);
290 } else if (iTCO_wdt_private.iTCO_version == 1) {
291 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
293 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
297 static int iTCO_wdt_unset_NO_REBOOT_bit(void)
302 /* Unset the NO_REBOOT bit: this enables reboots */
303 if (iTCO_wdt_private.iTCO_version == 2) {
304 val32 = readl(iTCO_wdt_private.gcs);
306 writel(val32, iTCO_wdt_private.gcs);
308 val32 = readl(iTCO_wdt_private.gcs);
309 if (val32 & 0x00000020)
311 } else if (iTCO_wdt_private.iTCO_version == 1) {
312 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
314 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
316 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
317 if (val32 & 0x00000002)
321 return ret; /* returns: 0 = OK, -EIO = Error */
324 static int iTCO_wdt_start(void)
328 spin_lock(&iTCO_wdt_private.io_lock);
330 iTCO_vendor_pre_start(iTCO_wdt_private.ACPIBASE, heartbeat);
332 /* disable chipset's NO_REBOOT bit */
333 if (iTCO_wdt_unset_NO_REBOOT_bit()) {
334 spin_unlock(&iTCO_wdt_private.io_lock);
335 printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, "
336 "reboot disabled by hardware\n");
340 /* Force the timer to its reload value by writing to the TCO_RLD
342 if (iTCO_wdt_private.iTCO_version == 2)
344 else if (iTCO_wdt_private.iTCO_version == 1)
347 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
352 spin_unlock(&iTCO_wdt_private.io_lock);
359 static int iTCO_wdt_stop(void)
363 spin_lock(&iTCO_wdt_private.io_lock);
365 iTCO_vendor_pre_stop(iTCO_wdt_private.ACPIBASE);
367 /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
373 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
374 iTCO_wdt_set_NO_REBOOT_bit();
376 spin_unlock(&iTCO_wdt_private.io_lock);
378 if ((val & 0x0800) == 0)
383 static int iTCO_wdt_keepalive(void)
385 spin_lock(&iTCO_wdt_private.io_lock);
387 iTCO_vendor_pre_keepalive(iTCO_wdt_private.ACPIBASE, heartbeat);
389 /* Reload the timer by writing to the TCO Timer Counter register */
390 if (iTCO_wdt_private.iTCO_version == 2)
392 else if (iTCO_wdt_private.iTCO_version == 1)
395 spin_unlock(&iTCO_wdt_private.io_lock);
399 static int iTCO_wdt_set_heartbeat(int t)
405 tmrval = seconds_to_ticks(t);
406 /* from the specs: */
407 /* "Values of 0h-3h are ignored and should not be attempted" */
410 if (((iTCO_wdt_private.iTCO_version == 2) && (tmrval > 0x3ff)) ||
411 ((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f)))
414 iTCO_vendor_pre_set_heartbeat(tmrval);
416 /* Write new heartbeat to watchdog */
417 if (iTCO_wdt_private.iTCO_version == 2) {
418 spin_lock(&iTCO_wdt_private.io_lock);
419 val16 = inw(TCOv2_TMR);
422 outw(val16, TCOv2_TMR);
423 val16 = inw(TCOv2_TMR);
424 spin_unlock(&iTCO_wdt_private.io_lock);
426 if ((val16 & 0x3ff) != tmrval)
428 } else if (iTCO_wdt_private.iTCO_version == 1) {
429 spin_lock(&iTCO_wdt_private.io_lock);
430 val8 = inb(TCOv1_TMR);
432 val8 |= (tmrval & 0xff);
433 outb(val8, TCOv1_TMR);
434 val8 = inb(TCOv1_TMR);
435 spin_unlock(&iTCO_wdt_private.io_lock);
437 if ((val8 & 0x3f) != tmrval)
445 static int iTCO_wdt_get_timeleft(int *time_left)
450 /* read the TCO Timer */
451 if (iTCO_wdt_private.iTCO_version == 2) {
452 spin_lock(&iTCO_wdt_private.io_lock);
453 val16 = inw(TCO_RLD);
455 spin_unlock(&iTCO_wdt_private.io_lock);
457 *time_left = (val16 * 6) / 10;
458 } else if (iTCO_wdt_private.iTCO_version == 1) {
459 spin_lock(&iTCO_wdt_private.io_lock);
462 spin_unlock(&iTCO_wdt_private.io_lock);
464 *time_left = (val8 * 6) / 10;
471 * /dev/watchdog handling
474 static int iTCO_wdt_open(struct inode *inode, struct file *file)
476 /* /dev/watchdog can only be opened once */
477 if (test_and_set_bit(0, &is_active))
481 * Reload and activate timer
484 return nonseekable_open(inode, file);
487 static int iTCO_wdt_release(struct inode *inode, struct file *file)
490 * Shut off the timer.
492 if (expect_release == 42) {
496 "Unexpected close, not stopping watchdog!\n");
497 iTCO_wdt_keepalive();
499 clear_bit(0, &is_active);
504 static ssize_t iTCO_wdt_write(struct file *file, const char __user *data,
505 size_t len, loff_t *ppos)
507 /* See if we got the magic character 'V' and reload the timer */
512 /* note: just in case someone wrote the magic
513 character five months ago... */
516 /* scan to see whether or not we got the
518 for (i = 0; i != len; i++) {
520 if (get_user(c, data + i))
527 /* someone wrote to us, we should reload the timer */
528 iTCO_wdt_keepalive();
533 static long iTCO_wdt_ioctl(struct file *file, unsigned int cmd,
536 int new_options, retval = -EINVAL;
538 void __user *argp = (void __user *)arg;
539 int __user *p = argp;
540 static struct watchdog_info ident = {
541 .options = WDIOF_SETTIMEOUT |
542 WDIOF_KEEPALIVEPING |
544 .firmware_version = 0,
545 .identity = DRV_NAME,
549 case WDIOC_GETSUPPORT:
550 return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
551 case WDIOC_GETSTATUS:
552 case WDIOC_GETBOOTSTATUS:
553 return put_user(0, p);
555 case WDIOC_SETOPTIONS:
557 if (get_user(new_options, p))
560 if (new_options & WDIOS_DISABLECARD) {
564 if (new_options & WDIOS_ENABLECARD) {
565 iTCO_wdt_keepalive();
571 case WDIOC_KEEPALIVE:
572 iTCO_wdt_keepalive();
575 case WDIOC_SETTIMEOUT:
577 if (get_user(new_heartbeat, p))
579 if (iTCO_wdt_set_heartbeat(new_heartbeat))
581 iTCO_wdt_keepalive();
584 case WDIOC_GETTIMEOUT:
585 return put_user(heartbeat, p);
586 case WDIOC_GETTIMELEFT:
589 if (iTCO_wdt_get_timeleft(&time_left))
591 return put_user(time_left, p);
602 static const struct file_operations iTCO_wdt_fops = {
603 .owner = THIS_MODULE,
605 .write = iTCO_wdt_write,
606 .unlocked_ioctl = iTCO_wdt_ioctl,
607 .open = iTCO_wdt_open,
608 .release = iTCO_wdt_release,
611 static struct miscdevice iTCO_wdt_miscdev = {
612 .minor = WATCHDOG_MINOR,
614 .fops = &iTCO_wdt_fops,
618 * Init & exit routines
621 static int __devinit iTCO_wdt_init(struct pci_dev *pdev,
622 const struct pci_device_id *ent, struct platform_device *dev)
630 * Find the ACPI/PM base I/O address which is the base
631 * for the TCO registers (TCOBASE=ACPIBASE + 0x60)
632 * ACPIBASE is bits [15:7] from 0x40-0x43
634 pci_read_config_dword(pdev, 0x40, &base_address);
635 base_address &= 0x0000ff80;
636 if (base_address == 0x00000000) {
637 /* Something's wrong here, ACPIBASE has to be set */
638 printk(KERN_ERR PFX "failed to get TCOBASE address\n");
642 iTCO_wdt_private.iTCO_version =
643 iTCO_chipset_info[ent->driver_data].iTCO_version;
644 iTCO_wdt_private.ACPIBASE = base_address;
645 iTCO_wdt_private.pdev = pdev;
647 /* Get the Memory-Mapped GCS register, we need it for the
648 NO_REBOOT flag (TCO v2). To get access to it you have to
649 read RCBA from PCI Config space 0xf0 and use it as base.
650 GCS = RCBA + ICH6_GCS(0x3410). */
651 if (iTCO_wdt_private.iTCO_version == 2) {
652 pci_read_config_dword(pdev, 0xf0, &base_address);
653 if ((base_address & 1) == 0) {
654 printk(KERN_ERR PFX "RCBA is disabled by harddware\n");
658 RCBA = base_address & 0xffffc000;
659 iTCO_wdt_private.gcs = ioremap((RCBA + 0x3410), 4);
662 /* Check chipset's NO_REBOOT bit */
663 if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) {
664 printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, "
665 "reboot disabled by hardware\n");
666 ret = -ENODEV; /* Cannot reset NO_REBOOT bit */
670 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
671 iTCO_wdt_set_NO_REBOOT_bit();
673 /* The TCO logic uses the TCO_EN bit in the SMI_EN register */
674 if (!request_region(SMI_EN, 4, "iTCO_wdt")) {
676 "I/O address 0x%04lx already in use\n", SMI_EN);
680 /* Bit 13: TCO_EN -> 0 = Disables TCO logic generating an SMI# */
682 val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
685 /* The TCO I/O registers reside in a 32-byte range pointed to
686 by the TCOBASE value */
687 if (!request_region(TCOBASE, 0x20, "iTCO_wdt")) {
688 printk(KERN_ERR PFX "I/O address 0x%04lx already in use\n",
695 "Found a %s TCO device (Version=%d, TCOBASE=0x%04lx)\n",
696 iTCO_chipset_info[ent->driver_data].name,
697 iTCO_chipset_info[ent->driver_data].iTCO_version,
700 /* Clear out the (probably old) status */
701 outb(8, TCO1_STS); /* Clear the Time Out Status bit */
702 outb(2, TCO2_STS); /* Clear SECOND_TO_STS bit */
703 outb(4, TCO2_STS); /* Clear BOOT_STS bit */
705 /* Make sure the watchdog is not running */
708 /* Check that the heartbeat value is within it's range;
709 if not reset to the default */
710 if (iTCO_wdt_set_heartbeat(heartbeat)) {
711 iTCO_wdt_set_heartbeat(WATCHDOG_HEARTBEAT);
713 "heartbeat value must be 2 < heartbeat < 39 (TCO v1) "
714 "or 613 (TCO v2), using %d\n", heartbeat);
717 ret = misc_register(&iTCO_wdt_miscdev);
720 "cannot register miscdev on minor=%d (err=%d)\n",
721 WATCHDOG_MINOR, ret);
725 printk(KERN_INFO PFX "initialized. heartbeat=%d sec (nowayout=%d)\n",
726 heartbeat, nowayout);
731 release_region(TCOBASE, 0x20);
733 release_region(SMI_EN, 4);
735 if (iTCO_wdt_private.iTCO_version == 2)
736 iounmap(iTCO_wdt_private.gcs);
738 pci_dev_put(iTCO_wdt_private.pdev);
739 iTCO_wdt_private.ACPIBASE = 0;
743 static void __devexit iTCO_wdt_cleanup(void)
745 /* Stop the timer before we leave */
750 misc_deregister(&iTCO_wdt_miscdev);
751 release_region(TCOBASE, 0x20);
752 release_region(SMI_EN, 4);
753 if (iTCO_wdt_private.iTCO_version == 2)
754 iounmap(iTCO_wdt_private.gcs);
755 pci_dev_put(iTCO_wdt_private.pdev);
756 iTCO_wdt_private.ACPIBASE = 0;
759 static int __devinit iTCO_wdt_probe(struct platform_device *dev)
762 struct pci_dev *pdev = NULL;
763 const struct pci_device_id *ent;
765 spin_lock_init(&iTCO_wdt_private.io_lock);
767 for_each_pci_dev(pdev) {
768 ent = pci_match_id(iTCO_wdt_pci_tbl, pdev);
770 if (!(iTCO_wdt_init(pdev, ent, dev))) {
778 printk(KERN_INFO PFX "No card detected\n");
785 static int __devexit iTCO_wdt_remove(struct platform_device *dev)
787 if (iTCO_wdt_private.ACPIBASE)
793 static void iTCO_wdt_shutdown(struct platform_device *dev)
798 #define iTCO_wdt_suspend NULL
799 #define iTCO_wdt_resume NULL
801 static struct platform_driver iTCO_wdt_driver = {
802 .probe = iTCO_wdt_probe,
803 .remove = __devexit_p(iTCO_wdt_remove),
804 .shutdown = iTCO_wdt_shutdown,
805 .suspend = iTCO_wdt_suspend,
806 .resume = iTCO_wdt_resume,
808 .owner = THIS_MODULE,
813 static int __init iTCO_wdt_init_module(void)
817 printk(KERN_INFO PFX "Intel TCO WatchDog Timer Driver v%s\n",
820 err = platform_driver_register(&iTCO_wdt_driver);
824 iTCO_wdt_platform_device = platform_device_register_simple(DRV_NAME,
826 if (IS_ERR(iTCO_wdt_platform_device)) {
827 err = PTR_ERR(iTCO_wdt_platform_device);
828 goto unreg_platform_driver;
833 unreg_platform_driver:
834 platform_driver_unregister(&iTCO_wdt_driver);
838 static void __exit iTCO_wdt_cleanup_module(void)
840 platform_device_unregister(iTCO_wdt_platform_device);
841 platform_driver_unregister(&iTCO_wdt_driver);
842 printk(KERN_INFO PFX "Watchdog Module Unloaded.\n");
845 module_init(iTCO_wdt_init_module);
846 module_exit(iTCO_wdt_cleanup_module);
848 MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
849 MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
850 MODULE_VERSION(DRV_VERSION);
851 MODULE_LICENSE("GPL");
852 MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);