2 * intel TCO Watchdog Driver (Used in i82801 and i6300ESB chipsets)
4 * (c) Copyright 2006-2008 Wim Van Sebroeck <wim@iguana.be>.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
12 * provide warranty for any of this software. This material is
13 * provided "AS-IS" and at no charge.
15 * The TCO watchdog is implemented in the following I/O controller hubs:
16 * (See the intel documentation on http://developer.intel.com.)
17 * 82801AA (ICH) : document number 290655-003, 290677-014,
18 * 82801AB (ICHO) : document number 290655-003, 290677-014,
19 * 82801BA (ICH2) : document number 290687-002, 298242-027,
20 * 82801BAM (ICH2-M) : document number 290687-002, 298242-027,
21 * 82801CA (ICH3-S) : document number 290733-003, 290739-013,
22 * 82801CAM (ICH3-M) : document number 290716-001, 290718-007,
23 * 82801DB (ICH4) : document number 290744-001, 290745-020,
24 * 82801DBM (ICH4-M) : document number 252337-001, 252663-005,
25 * 82801E (C-ICH) : document number 273599-001, 273645-002,
26 * 82801EB (ICH5) : document number 252516-001, 252517-003,
27 * 82801ER (ICH5R) : document number 252516-001, 252517-003,
28 * 82801FB (ICH6) : document number 301473-002, 301474-007,
29 * 82801FR (ICH6R) : document number 301473-002, 301474-007,
30 * 82801FBM (ICH6-M) : document number 301473-002, 301474-007,
31 * 82801FW (ICH6W) : document number 301473-001, 301474-007,
32 * 82801FRW (ICH6RW) : document number 301473-001, 301474-007,
33 * 82801GB (ICH7) : document number 307013-002, 307014-009,
34 * 82801GR (ICH7R) : document number 307013-002, 307014-009,
35 * 82801GDH (ICH7DH) : document number 307013-002, 307014-009,
36 * 82801GBM (ICH7-M) : document number 307013-002, 307014-009,
37 * 82801GHM (ICH7-M DH) : document number 307013-002, 307014-009,
38 * 82801HB (ICH8) : document number 313056-003, 313057-009,
39 * 82801HR (ICH8R) : document number 313056-003, 313057-009,
40 * 82801HBM (ICH8M) : document number 313056-003, 313057-009,
41 * 82801HH (ICH8DH) : document number 313056-003, 313057-009,
42 * 82801HO (ICH8DO) : document number 313056-003, 313057-009,
43 * 82801HEM (ICH8M-E) : document number 313056-003, 313057-009,
44 * 82801IB (ICH9) : document number 316972-001, 316973-006,
45 * 82801IR (ICH9R) : document number 316972-001, 316973-006,
46 * 82801IH (ICH9DH) : document number 316972-001, 316973-006,
47 * 82801IO (ICH9DO) : document number 316972-001, 316973-006,
48 * 6300ESB (6300ESB) : document number 300641-003, 300884-010,
49 * 631xESB (631xESB) : document number 313082-001, 313075-005,
50 * 632xESB (632xESB) : document number 313082-001, 313075-005
54 * Includes, defines, variables, module parameters, ...
57 /* Module and version information */
58 #define DRV_NAME "iTCO_wdt"
59 #define DRV_VERSION "1.04"
60 #define PFX DRV_NAME ": "
63 #include <linux/module.h> /* For module specific items */
64 #include <linux/moduleparam.h> /* For new moduleparam's */
65 #include <linux/types.h> /* For standard types (like size_t) */
66 #include <linux/errno.h> /* For the -ENODEV/... values */
67 #include <linux/kernel.h> /* For printk/panic/... */
68 #include <linux/miscdevice.h> /* For MODULE_ALIAS_MISCDEV
70 #include <linux/watchdog.h> /* For the watchdog specific items */
71 #include <linux/init.h> /* For __init/__exit/... */
72 #include <linux/fs.h> /* For file operations */
73 #include <linux/platform_device.h> /* For platform_driver framework */
74 #include <linux/pci.h> /* For pci functions */
75 #include <linux/ioport.h> /* For io-port access */
76 #include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
77 #include <linux/uaccess.h> /* For copy_to_user/put_user/... */
78 #include <linux/io.h> /* For inb/outb/... */
80 #include "iTCO_vendor.h"
82 /* TCO related info */
84 TCO_ICH = 0, /* ICH */
87 TCO_ICH2M, /* ICH2-M */
88 TCO_ICH3, /* ICH3-S */
89 TCO_ICH3M, /* ICH3-M */
91 TCO_ICH4M, /* ICH4-M */
93 TCO_ICH5, /* ICH5 & ICH5R */
94 TCO_6300ESB, /* 6300ESB */
95 TCO_ICH6, /* ICH6 & ICH6R */
96 TCO_ICH6M, /* ICH6-M */
97 TCO_ICH6W, /* ICH6W & ICH6RW */
98 TCO_ICH7, /* ICH7 & ICH7R */
99 TCO_ICH7M, /* ICH7-M */
100 TCO_ICH7MDH, /* ICH7-M DH */
101 TCO_ICH8, /* ICH8 & ICH8R */
102 TCO_ICH8ME, /* ICH8M-E */
103 TCO_ICH8DH, /* ICH8DH */
104 TCO_ICH8DO, /* ICH8DO */
105 TCO_ICH8M, /* ICH8M */
107 TCO_ICH9R, /* ICH9R */
108 TCO_ICH9DH, /* ICH9DH */
109 TCO_ICH9DO, /* ICH9DO */
110 TCO_631XESB, /* 631xESB/632xESB */
115 unsigned int iTCO_version;
116 } iTCO_chipset_info[] __devinitdata = {
126 {"ICH5 or ICH5R", 1},
128 {"ICH6 or ICH6R", 2},
130 {"ICH6W or ICH6RW", 2},
131 {"ICH7 or ICH7R", 2},
134 {"ICH8 or ICH8R", 2},
143 {"631xESB/632xESB", 2},
147 #define ITCO_PCI_DEVICE(dev, data) \
148 .vendor = PCI_VENDOR_ID_INTEL, \
150 .subvendor = PCI_ANY_ID, \
151 .subdevice = PCI_ANY_ID, \
157 * This data only exists for exporting the supported PCI ids
158 * via MODULE_DEVICE_TABLE. We do not actually register a
159 * pci_driver, because the I/O Controller Hub has also other
160 * functions that probably will be registered by other drivers.
162 static struct pci_device_id iTCO_wdt_pci_tbl[] = {
163 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AA_0, TCO_ICH)},
164 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AB_0, TCO_ICH0)},
165 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_0, TCO_ICH2)},
166 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_10, TCO_ICH2M)},
167 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_0, TCO_ICH3)},
168 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_12, TCO_ICH3M)},
169 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_0, TCO_ICH4)},
170 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_12, TCO_ICH4M)},
171 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801E_0, TCO_CICH)},
172 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801EB_0, TCO_ICH5)},
173 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB_1, TCO_6300ESB)},
174 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_0, TCO_ICH6)},
175 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_1, TCO_ICH6M)},
176 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_2, TCO_ICH6W)},
177 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_0, TCO_ICH7)},
178 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_1, TCO_ICH7M)},
179 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_31, TCO_ICH7MDH)},
180 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_0, TCO_ICH8)},
181 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_1, TCO_ICH8ME)},
182 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_2, TCO_ICH8DH)},
183 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_3, TCO_ICH8DO)},
184 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_4, TCO_ICH8M)},
185 { ITCO_PCI_DEVICE(0x2918, TCO_ICH9)},
186 { ITCO_PCI_DEVICE(0x2916, TCO_ICH9R)},
187 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_2, TCO_ICH9DH)},
188 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_4, TCO_ICH9DO)},
189 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB2_0, TCO_631XESB)},
190 { ITCO_PCI_DEVICE(0x2671, TCO_631XESB)},
191 { ITCO_PCI_DEVICE(0x2672, TCO_631XESB)},
192 { ITCO_PCI_DEVICE(0x2673, TCO_631XESB)},
193 { ITCO_PCI_DEVICE(0x2674, TCO_631XESB)},
194 { ITCO_PCI_DEVICE(0x2675, TCO_631XESB)},
195 { ITCO_PCI_DEVICE(0x2676, TCO_631XESB)},
196 { ITCO_PCI_DEVICE(0x2677, TCO_631XESB)},
197 { ITCO_PCI_DEVICE(0x2678, TCO_631XESB)},
198 { ITCO_PCI_DEVICE(0x2679, TCO_631XESB)},
199 { ITCO_PCI_DEVICE(0x267a, TCO_631XESB)},
200 { ITCO_PCI_DEVICE(0x267b, TCO_631XESB)},
201 { ITCO_PCI_DEVICE(0x267c, TCO_631XESB)},
202 { ITCO_PCI_DEVICE(0x267d, TCO_631XESB)},
203 { ITCO_PCI_DEVICE(0x267e, TCO_631XESB)},
204 { ITCO_PCI_DEVICE(0x267f, TCO_631XESB)},
205 { 0, }, /* End of list */
207 MODULE_DEVICE_TABLE(pci, iTCO_wdt_pci_tbl);
209 /* Address definitions for the TCO */
210 /* TCO base address */
211 #define TCOBASE iTCO_wdt_private.ACPIBASE + 0x60
212 /* SMI Control and Enable Register */
213 #define SMI_EN iTCO_wdt_private.ACPIBASE + 0x30
215 #define TCO_RLD TCOBASE + 0x00 /* TCO Timer Reload and Curr. Value */
216 #define TCOv1_TMR TCOBASE + 0x01 /* TCOv1 Timer Initial Value */
217 #define TCO_DAT_IN TCOBASE + 0x02 /* TCO Data In Register */
218 #define TCO_DAT_OUT TCOBASE + 0x03 /* TCO Data Out Register */
219 #define TCO1_STS TCOBASE + 0x04 /* TCO1 Status Register */
220 #define TCO2_STS TCOBASE + 0x06 /* TCO2 Status Register */
221 #define TCO1_CNT TCOBASE + 0x08 /* TCO1 Control Register */
222 #define TCO2_CNT TCOBASE + 0x0a /* TCO2 Control Register */
223 #define TCOv2_TMR TCOBASE + 0x12 /* TCOv2 Timer Initial Value */
225 /* internal variables */
226 static unsigned long is_active;
227 static char expect_release;
228 static struct { /* this is private data for the iTCO_wdt device */
229 /* TCO version/generation */
230 unsigned int iTCO_version;
231 /* The cards ACPIBASE address (TCOBASE = ACPIBASE+0x60) */
232 unsigned long ACPIBASE;
233 /* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2)*/
234 unsigned long __iomem *gcs;
235 /* the lock for io operations */
238 struct pci_dev *pdev;
241 /* the watchdog platform device */
242 static struct platform_device *iTCO_wdt_platform_device;
244 /* module parameters */
245 #define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */
246 static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
247 module_param(heartbeat, int, 0);
248 MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (2<heartbeat<39 (TCO v1) or 613 (TCO v2), default=" __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
250 static int nowayout = WATCHDOG_NOWAYOUT;
251 module_param(nowayout, int, 0);
252 MODULE_PARM_DESC(nowayout,
253 "Watchdog cannot be stopped once started (default="
254 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
257 * Some TCO specific functions
260 static inline unsigned int seconds_to_ticks(int seconds)
262 /* the internal timer is stored as ticks which decrement
263 * every 0.6 seconds */
264 return (seconds * 10) / 6;
267 static void iTCO_wdt_set_NO_REBOOT_bit(void)
271 /* Set the NO_REBOOT bit: this disables reboots */
272 if (iTCO_wdt_private.iTCO_version == 2) {
273 val32 = readl(iTCO_wdt_private.gcs);
275 writel(val32, iTCO_wdt_private.gcs);
276 } else if (iTCO_wdt_private.iTCO_version == 1) {
277 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
279 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
283 static int iTCO_wdt_unset_NO_REBOOT_bit(void)
288 /* Unset the NO_REBOOT bit: this enables reboots */
289 if (iTCO_wdt_private.iTCO_version == 2) {
290 val32 = readl(iTCO_wdt_private.gcs);
292 writel(val32, iTCO_wdt_private.gcs);
294 val32 = readl(iTCO_wdt_private.gcs);
295 if (val32 & 0x00000020)
297 } else if (iTCO_wdt_private.iTCO_version == 1) {
298 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
300 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
302 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
303 if (val32 & 0x00000002)
307 return ret; /* returns: 0 = OK, -EIO = Error */
310 static int iTCO_wdt_start(void)
315 spin_lock(&iTCO_wdt_private.io_lock);
317 iTCO_vendor_pre_start(iTCO_wdt_private.ACPIBASE, heartbeat);
319 /* disable chipset's NO_REBOOT bit */
320 if (iTCO_wdt_unset_NO_REBOOT_bit()) {
321 spin_unlock(&iTCO_wdt_private.io_lock);
322 printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, reboot disabled by hardware\n");
326 /* Bit 13: TCO_EN -> 0 = Disables TCO logic generating an SMI# */
328 val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
331 /* Force the timer to its reload value by writing to the TCO_RLD
333 if (iTCO_wdt_private.iTCO_version == 2)
335 else if (iTCO_wdt_private.iTCO_version == 1)
338 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
343 spin_unlock(&iTCO_wdt_private.io_lock);
350 static int iTCO_wdt_stop(void)
355 spin_lock(&iTCO_wdt_private.io_lock);
357 iTCO_vendor_pre_stop(iTCO_wdt_private.ACPIBASE);
359 /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
365 /* Bit 13: TCO_EN -> 1 = Enables the TCO logic to generate SMI# */
370 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
371 iTCO_wdt_set_NO_REBOOT_bit();
373 spin_unlock(&iTCO_wdt_private.io_lock);
375 if ((val & 0x0800) == 0)
380 static int iTCO_wdt_keepalive(void)
382 spin_lock(&iTCO_wdt_private.io_lock);
384 iTCO_vendor_pre_keepalive(iTCO_wdt_private.ACPIBASE, heartbeat);
386 /* Reload the timer by writing to the TCO Timer Counter register */
387 if (iTCO_wdt_private.iTCO_version == 2)
389 else if (iTCO_wdt_private.iTCO_version == 1)
392 spin_unlock(&iTCO_wdt_private.io_lock);
396 static int iTCO_wdt_set_heartbeat(int t)
402 tmrval = seconds_to_ticks(t);
403 /* from the specs: */
404 /* "Values of 0h-3h are ignored and should not be attempted" */
407 if (((iTCO_wdt_private.iTCO_version == 2) && (tmrval > 0x3ff)) ||
408 ((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f)))
411 iTCO_vendor_pre_set_heartbeat(tmrval);
413 /* Write new heartbeat to watchdog */
414 if (iTCO_wdt_private.iTCO_version == 2) {
415 spin_lock(&iTCO_wdt_private.io_lock);
416 val16 = inw(TCOv2_TMR);
419 outw(val16, TCOv2_TMR);
420 val16 = inw(TCOv2_TMR);
421 spin_unlock(&iTCO_wdt_private.io_lock);
423 if ((val16 & 0x3ff) != tmrval)
425 } else if (iTCO_wdt_private.iTCO_version == 1) {
426 spin_lock(&iTCO_wdt_private.io_lock);
427 val8 = inb(TCOv1_TMR);
429 val8 |= (tmrval & 0xff);
430 outb(val8, TCOv1_TMR);
431 val8 = inb(TCOv1_TMR);
432 spin_unlock(&iTCO_wdt_private.io_lock);
434 if ((val8 & 0x3f) != tmrval)
442 static int iTCO_wdt_get_timeleft(int *time_left)
447 /* read the TCO Timer */
448 if (iTCO_wdt_private.iTCO_version == 2) {
449 spin_lock(&iTCO_wdt_private.io_lock);
450 val16 = inw(TCO_RLD);
452 spin_unlock(&iTCO_wdt_private.io_lock);
454 *time_left = (val16 * 6) / 10;
455 } else if (iTCO_wdt_private.iTCO_version == 1) {
456 spin_lock(&iTCO_wdt_private.io_lock);
459 spin_unlock(&iTCO_wdt_private.io_lock);
461 *time_left = (val8 * 6) / 10;
468 * /dev/watchdog handling
471 static int iTCO_wdt_open(struct inode *inode, struct file *file)
473 /* /dev/watchdog can only be opened once */
474 if (test_and_set_bit(0, &is_active))
478 * Reload and activate timer
481 return nonseekable_open(inode, file);
484 static int iTCO_wdt_release(struct inode *inode, struct file *file)
487 * Shut off the timer.
489 if (expect_release == 42) {
493 "Unexpected close, not stopping watchdog!\n");
494 iTCO_wdt_keepalive();
496 clear_bit(0, &is_active);
501 static ssize_t iTCO_wdt_write(struct file *file, const char __user *data,
502 size_t len, loff_t *ppos)
504 /* See if we got the magic character 'V' and reload the timer */
509 /* note: just in case someone wrote the magic
510 character five months ago... */
513 /* scan to see whether or not we got the
515 for (i = 0; i != len; i++) {
517 if (get_user(c, data + i))
524 /* someone wrote to us, we should reload the timer */
525 iTCO_wdt_keepalive();
530 static long iTCO_wdt_ioctl(struct file *file, unsigned int cmd,
533 int new_options, retval = -EINVAL;
535 void __user *argp = (void __user *)arg;
536 int __user *p = argp;
537 static struct watchdog_info ident = {
538 .options = WDIOF_SETTIMEOUT |
539 WDIOF_KEEPALIVEPING |
541 .firmware_version = 0,
542 .identity = DRV_NAME,
546 case WDIOC_GETSUPPORT:
547 return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
548 case WDIOC_GETSTATUS:
549 case WDIOC_GETBOOTSTATUS:
550 return put_user(0, p);
552 case WDIOC_SETOPTIONS:
554 if (get_user(new_options, p))
557 if (new_options & WDIOS_DISABLECARD) {
561 if (new_options & WDIOS_ENABLECARD) {
562 iTCO_wdt_keepalive();
568 case WDIOC_KEEPALIVE:
569 iTCO_wdt_keepalive();
572 case WDIOC_SETTIMEOUT:
574 if (get_user(new_heartbeat, p))
576 if (iTCO_wdt_set_heartbeat(new_heartbeat))
578 iTCO_wdt_keepalive();
581 case WDIOC_GETTIMEOUT:
582 return put_user(heartbeat, p);
583 case WDIOC_GETTIMELEFT:
586 if (iTCO_wdt_get_timeleft(&time_left))
588 return put_user(time_left, p);
599 static const struct file_operations iTCO_wdt_fops = {
600 .owner = THIS_MODULE,
602 .write = iTCO_wdt_write,
603 .unlocked_ioctl = iTCO_wdt_ioctl,
604 .open = iTCO_wdt_open,
605 .release = iTCO_wdt_release,
608 static struct miscdevice iTCO_wdt_miscdev = {
609 .minor = WATCHDOG_MINOR,
611 .fops = &iTCO_wdt_fops,
615 * Init & exit routines
618 static int __devinit iTCO_wdt_init(struct pci_dev *pdev,
619 const struct pci_device_id *ent, struct platform_device *dev)
626 * Find the ACPI/PM base I/O address which is the base
627 * for the TCO registers (TCOBASE=ACPIBASE + 0x60)
628 * ACPIBASE is bits [15:7] from 0x40-0x43
630 pci_read_config_dword(pdev, 0x40, &base_address);
631 base_address &= 0x0000ff80;
632 if (base_address == 0x00000000) {
633 /* Something's wrong here, ACPIBASE has to be set */
634 printk(KERN_ERR PFX "failed to get TCOBASE address\n");
638 iTCO_wdt_private.iTCO_version =
639 iTCO_chipset_info[ent->driver_data].iTCO_version;
640 iTCO_wdt_private.ACPIBASE = base_address;
641 iTCO_wdt_private.pdev = pdev;
643 /* Get the Memory-Mapped GCS register, we need it for the
644 NO_REBOOT flag (TCO v2). To get access to it you have to
645 read RCBA from PCI Config space 0xf0 and use it as base.
646 GCS = RCBA + ICH6_GCS(0x3410). */
647 if (iTCO_wdt_private.iTCO_version == 2) {
648 pci_read_config_dword(pdev, 0xf0, &base_address);
649 RCBA = base_address & 0xffffc000;
650 iTCO_wdt_private.gcs = ioremap((RCBA + 0x3410), 4);
653 /* Check chipset's NO_REBOOT bit */
654 if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) {
655 printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, reboot disabled by hardware\n");
656 ret = -ENODEV; /* Cannot reset NO_REBOOT bit */
660 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
661 iTCO_wdt_set_NO_REBOOT_bit();
663 /* The TCO logic uses the TCO_EN bit in the SMI_EN register */
664 if (!request_region(SMI_EN, 4, "iTCO_wdt")) {
666 "I/O address 0x%04lx already in use\n", SMI_EN);
671 /* The TCO I/O registers reside in a 32-byte range pointed to
672 by the TCOBASE value */
673 if (!request_region(TCOBASE, 0x20, "iTCO_wdt")) {
674 printk(KERN_ERR PFX "I/O address 0x%04lx already in use\n",
681 "Found a %s TCO device (Version=%d, TCOBASE=0x%04lx)\n",
682 iTCO_chipset_info[ent->driver_data].name,
683 iTCO_chipset_info[ent->driver_data].iTCO_version,
686 /* Clear out the (probably old) status */
690 /* Make sure the watchdog is not running */
693 /* Check that the heartbeat value is within it's range;
694 if not reset to the default */
695 if (iTCO_wdt_set_heartbeat(heartbeat)) {
696 iTCO_wdt_set_heartbeat(WATCHDOG_HEARTBEAT);
697 printk(KERN_INFO PFX "heartbeat value must be 2 < heartbeat < 39 (TCO v1) or 613 (TCO v2), using %d\n",
701 ret = misc_register(&iTCO_wdt_miscdev);
704 "cannot register miscdev on minor=%d (err=%d)\n",
705 WATCHDOG_MINOR, ret);
709 printk(KERN_INFO PFX "initialized. heartbeat=%d sec (nowayout=%d)\n",
710 heartbeat, nowayout);
715 release_region(TCOBASE, 0x20);
717 release_region(SMI_EN, 4);
719 if (iTCO_wdt_private.iTCO_version == 2)
720 iounmap(iTCO_wdt_private.gcs);
721 pci_dev_put(iTCO_wdt_private.pdev);
722 iTCO_wdt_private.ACPIBASE = 0;
726 static void __devexit iTCO_wdt_cleanup(void)
728 /* Stop the timer before we leave */
733 misc_deregister(&iTCO_wdt_miscdev);
734 release_region(TCOBASE, 0x20);
735 release_region(SMI_EN, 4);
736 if (iTCO_wdt_private.iTCO_version == 2)
737 iounmap(iTCO_wdt_private.gcs);
738 pci_dev_put(iTCO_wdt_private.pdev);
739 iTCO_wdt_private.ACPIBASE = 0;
742 static int __devinit iTCO_wdt_probe(struct platform_device *dev)
745 struct pci_dev *pdev = NULL;
746 const struct pci_device_id *ent;
748 spin_lock_init(&iTCO_wdt_private.io_lock);
750 for_each_pci_dev(pdev) {
751 ent = pci_match_id(iTCO_wdt_pci_tbl, pdev);
753 if (!(iTCO_wdt_init(pdev, ent, dev))) {
761 printk(KERN_INFO PFX "No card detected\n");
768 static int __devexit iTCO_wdt_remove(struct platform_device *dev)
770 if (iTCO_wdt_private.ACPIBASE)
776 static void iTCO_wdt_shutdown(struct platform_device *dev)
781 #define iTCO_wdt_suspend NULL
782 #define iTCO_wdt_resume NULL
784 static struct platform_driver iTCO_wdt_driver = {
785 .probe = iTCO_wdt_probe,
786 .remove = __devexit_p(iTCO_wdt_remove),
787 .shutdown = iTCO_wdt_shutdown,
788 .suspend = iTCO_wdt_suspend,
789 .resume = iTCO_wdt_resume,
791 .owner = THIS_MODULE,
796 static int __init iTCO_wdt_init_module(void)
800 printk(KERN_INFO PFX "Intel TCO WatchDog Timer Driver v%s\n",
803 err = platform_driver_register(&iTCO_wdt_driver);
807 iTCO_wdt_platform_device = platform_device_register_simple(DRV_NAME,
809 if (IS_ERR(iTCO_wdt_platform_device)) {
810 err = PTR_ERR(iTCO_wdt_platform_device);
811 goto unreg_platform_driver;
816 unreg_platform_driver:
817 platform_driver_unregister(&iTCO_wdt_driver);
821 static void __exit iTCO_wdt_cleanup_module(void)
823 platform_device_unregister(iTCO_wdt_platform_device);
824 platform_driver_unregister(&iTCO_wdt_driver);
825 printk(KERN_INFO PFX "Watchdog Module Unloaded.\n");
828 module_init(iTCO_wdt_init_module);
829 module_exit(iTCO_wdt_cleanup_module);
831 MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
832 MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
833 MODULE_VERSION(DRV_VERSION);
834 MODULE_LICENSE("GPL");
835 MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);