drivers/watchdog/s3c2410_wdt.c

   1 /* linux/drivers/char/watchdog/s3c2410_wdt.c
   2  *
   3  * Copyright (c) 2004 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2410 Watchdog Timer Support
   7  *
   8  * Based on, softdog.c by Alan Cox,
   9  *     (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  24 */
  25
  26 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  27
  28 #include <linux/module.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/types.h>
  31 #include <linux/timer.h>
  32 #include <linux/miscdevice.h> /* for MODULE_ALIAS_MISCDEV */
  33 #include <linux/watchdog.h>
  34 #include <linux/init.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/clk.h>
  38 #include <linux/uaccess.h>
  39 #include <linux/io.h>
  40 #include <linux/cpufreq.h>
  41 #include <linux/slab.h>
  42 #include <linux/err.h>
  43 #include <linux/of.h>
  44
  45 #define S3C2410_WTCON           0x00
  46 #define S3C2410_WTDAT           0x04
  47 #define S3C2410_WTCNT           0x08
  48
  49 #define S3C2410_WTCON_RSTEN     (1 << 0)
  50 #define S3C2410_WTCON_INTEN     (1 << 2)
  51 #define S3C2410_WTCON_ENABLE    (1 << 5)
  52
  53 #define S3C2410_WTCON_DIV16     (0 << 3)
  54 #define S3C2410_WTCON_DIV32     (1 << 3)
  55 #define S3C2410_WTCON_DIV64     (2 << 3)
  56 #define S3C2410_WTCON_DIV128    (3 << 3)
  57
  58 #define S3C2410_WTCON_PRESCALE(x)       ((x) << 8)
  59 #define S3C2410_WTCON_PRESCALE_MASK     (0xff << 8)
  60
  61 #define CONFIG_S3C2410_WATCHDOG_ATBOOT          (0)
  62 #define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME    (15)
  63
  64 static bool nowayout    = WATCHDOG_NOWAYOUT;
  65 static int tmr_margin;
  66 static int tmr_atboot   = CONFIG_S3C2410_WATCHDOG_ATBOOT;
  67 static int soft_noboot;
  68 static int debug;
  69
  70 module_param(tmr_margin,  int, 0);
  71 module_param(tmr_atboot,  int, 0);
  72 module_param(nowayout,   bool, 0);
  73 module_param(soft_noboot, int, 0);
  74 module_param(debug,       int, 0);
  75
  76 MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default="
  77                 __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")");
  78 MODULE_PARM_DESC(tmr_atboot,
  79                 "Watchdog is started at boot time if set to 1, default="
  80                         __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT));
  81 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  82                         __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  83 MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, "
  84                         "0 to reboot (default 0)");
  85 MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug (default 0)");
  86
  87 static struct device    *wdt_dev;       /* platform device attached to */
  88 static struct resource  *wdt_mem;
  89 static struct resource  *wdt_irq;
  90 static struct clk       *wdt_clock;
  91 static void __iomem     *wdt_base;
  92 static unsigned int      wdt_count;
  93 static DEFINE_SPINLOCK(wdt_lock);
  94
  95 /* watchdog control routines */
  96
  97 #define DBG(fmt, ...)                                   \
  98 do {                                                    \
  99         if (debug)                                      \
 100                 pr_info(fmt, ##__VA_ARGS__);            \
 101 } while (0)
 102
 103 /* functions */
 104
 105 static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
 106 {
 107         spin_lock(&wdt_lock);
 108         writel(wdt_count, wdt_base + S3C2410_WTCNT);
 109         spin_unlock(&wdt_lock);
 110
 111         return 0;
 112 }
 113
 114 static void __s3c2410wdt_stop(void)
 115 {
 116         unsigned long wtcon;
 117
 118         wtcon = readl(wdt_base + S3C2410_WTCON);
 119         wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN);
 120         writel(wtcon, wdt_base + S3C2410_WTCON);
 121 }
 122
 123 static int s3c2410wdt_stop(struct watchdog_device *wdd)
 124 {
 125         spin_lock(&wdt_lock);
 126         __s3c2410wdt_stop();
 127         spin_unlock(&wdt_lock);
 128
 129         return 0;
 130 }
 131
 132 static int s3c2410wdt_start(struct watchdog_device *wdd)
 133 {
 134         unsigned long wtcon;
 135
 136         spin_lock(&wdt_lock);
 137
 138         __s3c2410wdt_stop();
 139
 140         wtcon = readl(wdt_base + S3C2410_WTCON);
 141         wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128;
 142
 143         if (soft_noboot) {
 144                 wtcon |= S3C2410_WTCON_INTEN;
 145                 wtcon &= ~S3C2410_WTCON_RSTEN;
 146         } else {
 147                 wtcon &= ~S3C2410_WTCON_INTEN;
 148                 wtcon |= S3C2410_WTCON_RSTEN;
 149         }
 150
 151         DBG("%s: wdt_count=0x%08x, wtcon=%08lx\n",
 152             __func__, wdt_count, wtcon);
 153
 154         writel(wdt_count, wdt_base + S3C2410_WTDAT);
 155         writel(wdt_count, wdt_base + S3C2410_WTCNT);
 156         writel(wtcon, wdt_base + S3C2410_WTCON);
 157         spin_unlock(&wdt_lock);
 158
 159         return 0;
 160 }
 161
 162 static inline int s3c2410wdt_is_running(void)
 163 {
 164         return readl(wdt_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE;
 165 }
 166
 167 static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd, unsigned timeout)
 168 {
 169         unsigned long freq = clk_get_rate(wdt_clock);
 170         unsigned int count;
 171         unsigned int divisor = 1;
 172         unsigned long wtcon;
 173
 174         if (timeout < 1)
 175                 return -EINVAL;
 176
 177         freq /= 128;
 178         count = timeout * freq;
 179
 180         DBG("%s: count=%d, timeout=%d, freq=%lu\n",
 181             __func__, count, timeout, freq);
 182
 183         /* if the count is bigger than the watchdog register,
 184            then work out what we need to do (and if) we can
 185            actually make this value
 186         */
 187
 188         if (count >= 0x10000) {
 189                 for (divisor = 1; divisor <= 0x100; divisor++) {
 190                         if ((count / divisor) < 0x10000)
 191                                 break;
 192                 }
 193
 194                 if ((count / divisor) >= 0x10000) {
 195                         dev_err(wdt_dev, "timeout %d too big\n", timeout);
 196                         return -EINVAL;
 197                 }
 198         }
 199
 200         DBG("%s: timeout=%d, divisor=%d, count=%d (%08x)\n",
 201             __func__, timeout, divisor, count, count/divisor);
 202
 203         count /= divisor;
 204         wdt_count = count;
 205
 206         /* update the pre-scaler */
 207         wtcon = readl(wdt_base + S3C2410_WTCON);
 208         wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
 209         wtcon |= S3C2410_WTCON_PRESCALE(divisor-1);
 210
 211         writel(count, wdt_base + S3C2410_WTDAT);
 212         writel(wtcon, wdt_base + S3C2410_WTCON);
 213
 214         wdd->timeout = (count * divisor) / freq;
 215
 216         return 0;
 217 }
 218
 219 #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
 220
 221 static const struct watchdog_info s3c2410_wdt_ident = {
 222         .options          =     OPTIONS,
 223         .firmware_version =     0,
 224         .identity         =     "S3C2410 Watchdog",
 225 };
 226
 227 static struct watchdog_ops s3c2410wdt_ops = {
 228         .owner = THIS_MODULE,
 229         .start = s3c2410wdt_start,
 230         .stop = s3c2410wdt_stop,
 231         .ping = s3c2410wdt_keepalive,
 232         .set_timeout = s3c2410wdt_set_heartbeat,
 233 };
 234
 235 static struct watchdog_device s3c2410_wdd = {
 236         .info = &s3c2410_wdt_ident,
 237         .ops = &s3c2410wdt_ops,
 238         .timeout = CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME,
 239 };
 240
 241 /* interrupt handler code */
 242
 243 static irqreturn_t s3c2410wdt_irq(int irqno, void *param)
 244 {
 245         dev_info(wdt_dev, "watchdog timer expired (irq)\n");
 246
 247         s3c2410wdt_keepalive(&s3c2410_wdd);
 248         return IRQ_HANDLED;
 249 }
 250
 251
 252 #ifdef CONFIG_CPU_FREQ
 253
 254 static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb,
 255                                           unsigned long val, void *data)
 256 {
 257         int ret;
 258
 259         if (!s3c2410wdt_is_running())
 260                 goto done;
 261
 262         if (val == CPUFREQ_PRECHANGE) {
 263                 /* To ensure that over the change we don't cause the
 264                  * watchdog to trigger, we perform an keep-alive if
 265                  * the watchdog is running.
 266                  */
 267
 268                 s3c2410wdt_keepalive(&s3c2410_wdd);
 269         } else if (val == CPUFREQ_POSTCHANGE) {
 270                 s3c2410wdt_stop(&s3c2410_wdd);
 271
 272                 ret = s3c2410wdt_set_heartbeat(&s3c2410_wdd, s3c2410_wdd.timeout);
 273
 274                 if (ret >= 0)
 275                         s3c2410wdt_start(&s3c2410_wdd);
 276                 else
 277                         goto err;
 278         }
 279
 280 done:
 281         return 0;
 282
 283  err:
 284         dev_err(wdt_dev, "cannot set new value for timeout %d\n",
 285                                 s3c2410_wdd.timeout);
 286         return ret;
 287 }
 288
 289 static struct notifier_block s3c2410wdt_cpufreq_transition_nb = {
 290         .notifier_call  = s3c2410wdt_cpufreq_transition,
 291 };
 292
 293 static inline int s3c2410wdt_cpufreq_register(void)
 294 {
 295         return cpufreq_register_notifier(&s3c2410wdt_cpufreq_transition_nb,
 296                                          CPUFREQ_TRANSITION_NOTIFIER);
 297 }
 298
 299 static inline void s3c2410wdt_cpufreq_deregister(void)
 300 {
 301         cpufreq_unregister_notifier(&s3c2410wdt_cpufreq_transition_nb,
 302                                     CPUFREQ_TRANSITION_NOTIFIER);
 303 }
 304
 305 #else
 306 static inline int s3c2410wdt_cpufreq_register(void)
 307 {
 308         return 0;
 309 }
 310
 311 static inline void s3c2410wdt_cpufreq_deregister(void)
 312 {
 313 }
 314 #endif
 315
 316 static int s3c2410wdt_probe(struct platform_device *pdev)
 317 {
 318         struct device *dev;
 319         unsigned int wtcon;
 320         int started = 0;
 321         int ret;
 322
 323         DBG("%s: probe=%p\n", __func__, pdev);
 324
 325         dev = &pdev->dev;
 326         wdt_dev = &pdev->dev;
 327
 328         wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 329         if (wdt_mem == NULL) {
 330                 dev_err(dev, "no memory resource specified\n");
 331                 return -ENOENT;
 332         }
 333
 334         wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 335         if (wdt_irq == NULL) {
 336                 dev_err(dev, "no irq resource specified\n");
 337                 ret = -ENOENT;
 338                 goto err;
 339         }
 340
 341         /* get the memory region for the watchdog timer */
 342         wdt_base = devm_ioremap_resource(dev, wdt_mem);
 343         if (IS_ERR(wdt_base)) {
 344                 ret = PTR_ERR(wdt_base);
 345                 goto err;
 346         }
 347
 348         DBG("probe: mapped wdt_base=%p\n", wdt_base);
 349
 350         wdt_clock = devm_clk_get(dev, "watchdog");
 351         if (IS_ERR(wdt_clock)) {
 352                 dev_err(dev, "failed to find watchdog clock source\n");
 353                 ret = PTR_ERR(wdt_clock);
 354                 goto err;
 355         }
 356
 357         clk_prepare_enable(wdt_clock);
 358
 359         ret = s3c2410wdt_cpufreq_register();
 360         if (ret < 0) {
 361                 dev_err(dev, "failed to register cpufreq\n");
 362                 goto err_clk;
 363         }
 364
 365         /* see if we can actually set the requested timer margin, and if
 366          * not, try the default value */
 367
 368         watchdog_init_timeout(&s3c2410_wdd, tmr_margin,  &pdev->dev);
 369         if (s3c2410wdt_set_heartbeat(&s3c2410_wdd, s3c2410_wdd.timeout)) {
 370                 started = s3c2410wdt_set_heartbeat(&s3c2410_wdd,
 371                                         CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
 372
 373                 if (started == 0)
 374                         dev_info(dev,
 375                            "tmr_margin value out of range, default %d used\n",
 376                                CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
 377                 else
 378                         dev_info(dev, "default timer value is out of range, "
 379                                                         "cannot start\n");
 380         }
 381
 382         ret = devm_request_irq(dev, wdt_irq->start, s3c2410wdt_irq, 0,
 383                                 pdev->name, pdev);
 384         if (ret != 0) {
 385                 dev_err(dev, "failed to install irq (%d)\n", ret);
 386                 goto err_cpufreq;
 387         }
 388
 389         watchdog_set_nowayout(&s3c2410_wdd, nowayout);
 390
 391         ret = watchdog_register_device(&s3c2410_wdd);
 392         if (ret) {
 393                 dev_err(dev, "cannot register watchdog (%d)\n", ret);
 394                 goto err_cpufreq;
 395         }
 396
 397         if (tmr_atboot && started == 0) {
 398                 dev_info(dev, "starting watchdog timer\n");
 399                 s3c2410wdt_start(&s3c2410_wdd);
 400         } else if (!tmr_atboot) {
 401                 /* if we're not enabling the watchdog, then ensure it is
 402                  * disabled if it has been left running from the bootloader
 403                  * or other source */
 404
 405                 s3c2410wdt_stop(&s3c2410_wdd);
 406         }
 407
 408         /* print out a statement of readiness */
 409
 410         wtcon = readl(wdt_base + S3C2410_WTCON);
 411
 412         dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n",
 413                  (wtcon & S3C2410_WTCON_ENABLE) ?  "" : "in",
 414                  (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis",
 415                  (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis");
 416
 417         return 0;
 418
 419  err_cpufreq:
 420         s3c2410wdt_cpufreq_deregister();
 421
 422  err_clk:
 423         clk_disable_unprepare(wdt_clock);
 424         wdt_clock = NULL;
 425
 426  err:
 427         wdt_irq = NULL;
 428         wdt_mem = NULL;
 429         return ret;
 430 }
 431
 432 static int s3c2410wdt_remove(struct platform_device *dev)
 433 {
 434         watchdog_unregister_device(&s3c2410_wdd);
 435
 436         s3c2410wdt_cpufreq_deregister();
 437
 438         clk_disable_unprepare(wdt_clock);
 439         wdt_clock = NULL;
 440
 441         wdt_irq = NULL;
 442         wdt_mem = NULL;
 443         return 0;
 444 }
 445
 446 static void s3c2410wdt_shutdown(struct platform_device *dev)
 447 {
 448         s3c2410wdt_stop(&s3c2410_wdd);
 449 }
 450
 451 #ifdef CONFIG_PM_SLEEP
 452
 453 static unsigned long wtcon_save;
 454 static unsigned long wtdat_save;
 455
 456 static int s3c2410wdt_suspend(struct device *dev)
 457 {
 458         /* Save watchdog state, and turn it off. */
 459         wtcon_save = readl(wdt_base + S3C2410_WTCON);
 460         wtdat_save = readl(wdt_base + S3C2410_WTDAT);
 461
 462         /* Note that WTCNT doesn't need to be saved. */
 463         s3c2410wdt_stop(&s3c2410_wdd);
 464
 465         return 0;
 466 }
 467
 468 static int s3c2410wdt_resume(struct device *dev)
 469 {
 470         /* Restore watchdog state. */
 471
 472         writel(wtdat_save, wdt_base + S3C2410_WTDAT);
 473         writel(wtdat_save, wdt_base + S3C2410_WTCNT); /* Reset count */
 474         writel(wtcon_save, wdt_base + S3C2410_WTCON);
 475
 476         dev_info(dev, "watchdog %sabled\n",
 477                 (wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");
 478
 479         return 0;
 480 }
 481 #endif
 482
 483 static SIMPLE_DEV_PM_OPS(s3c2410wdt_pm_ops, s3c2410wdt_suspend,
 484                         s3c2410wdt_resume);
 485
 486 #ifdef CONFIG_OF
 487 static const struct of_device_id s3c2410_wdt_match[] = {
 488         { .compatible = "samsung,s3c2410-wdt" },
 489         {},
 490 };
 491 MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
 492 #endif
 493
 494 static struct platform_driver s3c2410wdt_driver = {
 495         .probe          = s3c2410wdt_probe,
 496         .remove         = s3c2410wdt_remove,
 497         .shutdown       = s3c2410wdt_shutdown,
 498         .driver         = {
 499                 .owner  = THIS_MODULE,
 500                 .name   = "s3c2410-wdt",
 501                 .pm     = &s3c2410wdt_pm_ops,
 502                 .of_match_table = of_match_ptr(s3c2410_wdt_match),
 503         },
 504 };
 505
 506 module_platform_driver(s3c2410wdt_driver);
 507
 508 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, "
 509               "Dimitry Andric <dimitry.andric@tomtom.com>");
 510 MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver");
 511 MODULE_LICENSE("GPL");
 512 MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
 513 MODULE_ALIAS("platform:s3c2410-wdt");