2 * Copyright 2015 Savoir-faire Linux
4 * This device tree is based on imx51-babbage.dts
6 * Licensed under the X11 license or the GPL v2 (or later)
13 model = "Technologic Systems TS-4800";
14 compatible = "technologic,imx51-ts4800", "fsl,imx51";
21 reg = <0x90000000 0x10000000>;
26 clock-frequency = <22579200>;
30 clock-frequency = <24576000>;
34 backlight_reg: regulator-backlight {
35 compatible = "regulator-fixed";
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_enable_lcd>;
38 regulator-name = "enable_lcd_reg";
39 regulator-min-microvolt = <3300000>;
40 regulator-max-microvolt = <3300000>;
41 gpio = <&gpio4 9 GPIO_ACTIVE_HIGH>;
45 backlight: backlight {
46 compatible = "pwm-backlight";
47 pwms = <&pwm1 0 78770>;
48 brightness-levels = <0 150 200 255>;
49 default-brightness-level = <1>;
50 power-supply = <&backlight_reg>;
53 display0: display@di0 {
54 compatible = "fsl,imx-parallel-display";
55 interface-pix-fmt = "rgb24";
56 pinctrl-names = "default";
57 pinctrl-0 = <&pinctrl_lcd>;
62 clock-frequency = <30066000>;
75 display0_in: endpoint {
76 remote-endpoint = <&ipu_di0_disp0>;
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_esdhc1>;
85 cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
86 wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_fec>;
94 phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
95 phy-reset-duration = <1>;
100 pinctrl-names = "default";
101 pinctrl-0 = <&pinctrl_i2c2>;
105 compatible = "stm,m41t00";
111 remote-endpoint = <&display0_in>;
115 pinctrl-names = "default";
116 pinctrl-0 = <&pinctrl_pwm_backlight>;
121 pinctrl-names = "default";
122 pinctrl-0 = <&pinctrl_uart1>;
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_uart2>;
133 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_uart3>;
139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_weim>;
144 compatible = "simple-bus";
145 fsl,weim-cs-timing = <0x0061008F 0x00000002 0x1c022000
146 0x00000000 0x1c092480 0x00000000>;
147 reg = <0 0x0000000 0x1d000>;
148 #address-cells = <1>;
150 ranges = <0 0 0 0x1d000>;
152 syscon: syscon@b0010000 {
153 compatible = "syscon", "simple-mfd";
154 reg = <0x10000 0x3d>;
158 compatible = "technologic,ts4800-wdt";
159 syscon = <&syscon 0xe>;
164 compatible = "technologic,ts4800-ts";
165 reg = <0x12000 0x1000>;
166 syscon = <&syscon 0x10 6>;
172 pinctrl_ecspi1: ecspi1grp {
174 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
175 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
176 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
177 MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */
181 pinctrl_enable_lcd: enablelcdgrp {
183 MX51_PAD_CSI2_D12__GPIO4_9 0x1c5
187 pinctrl_esdhc1: esdhc1grp {
189 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
190 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
191 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
192 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
193 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
194 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
195 MX51_PAD_GPIO1_0__GPIO1_0 0x100
196 MX51_PAD_GPIO1_1__GPIO1_1 0x100
200 pinctrl_fec: fecgrp {
202 MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5
203 MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085
204 MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085
205 MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085
206 MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180
207 MX51_PAD_EIM_CS5__FEC_CRS 0x00000180
208 MX51_PAD_DISP2_DAT10__FEC_COL 0x00000180
209 MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x00000180
210 MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x00002180
211 MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x00002004
212 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004
213 MX51_PAD_DI2_PIN2__FEC_MDC 0x00002004
214 MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x00002004
215 MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x00002004
216 MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x00002004
217 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x00002004
218 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x00002180
219 MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x000020a4
220 MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */
224 pinctrl_i2c2: i2c2grp {
226 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
227 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
231 pinctrl_lcd: lcdgrp {
233 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
234 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
235 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
236 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
237 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
238 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
239 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
240 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
241 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
242 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
243 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
244 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
245 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
246 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
247 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
248 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
249 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
250 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
251 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
252 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
253 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
254 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
255 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
256 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
257 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
258 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
259 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
260 MX51_PAD_DI_GP4__DI2_PIN15 0x5
264 pinctrl_pwm_backlight: backlightgrp {
266 MX51_PAD_GPIO1_2__PWM1_PWMO 0x80000000
270 pinctrl_uart1: uart1grp {
272 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
273 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
277 pinctrl_uart2: uart2grp {
279 MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
280 MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
284 pinctrl_uart3: uart3grp {
286 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
287 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
291 pinctrl_weim: weimgrp {
293 MX51_PAD_EIM_DTACK__EIM_DTACK 0x85
294 MX51_PAD_EIM_CS0__EIM_CS0 0x0
295 MX51_PAD_EIM_CS1__EIM_CS1 0x0
296 MX51_PAD_EIM_EB0__EIM_EB0 0x85
297 MX51_PAD_EIM_EB1__EIM_EB1 0x85
298 MX51_PAD_EIM_OE__EIM_OE 0x85
299 MX51_PAD_EIM_LBA__EIM_LBA 0x85