2 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
3 * Terry Lv <r65388@freescale.com>
5 * Copyright (C) Freescale Semiconductor, Inc. 2006.
6 * Author: Jason Jin<Jason.jin@freescale.com>
7 * Zhang Wei<wei.zhang@freescale.com>
9 * SPDX-License-Identifier: GPL-2.0+
16 #define AHCI_PCI_BAR 0x24
17 #define AHCI_MAX_SG 56 /* hardware max is 64K */
18 #define AHCI_MAX_CMD_SLOT 32
19 #define AHCI_CMD_SLOT_SZ 32
20 #define AHCI_MAX_CMD_SLOT 32
21 #define AHCI_RX_FIS_SZ 256
22 #define AHCI_CMD_TBL_HDR 0x80
23 #define AHCI_CMD_TBL_CDB 0x40
24 #define AHCI_CMD_TBL_SZ (AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16))
25 #define AHCI_PORT_PRIV_DMA_SZ (AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT + \
26 AHCI_CMD_TBL_SZ + AHCI_RX_FIS_SZ)
27 #define AHCI_CMD_ATAPI (1 << 5)
28 #define AHCI_CMD_WRITE (1 << 6)
29 #define AHCI_CMD_PREFETCH (1 << 7)
30 #define AHCI_CMD_RESET (1 << 8)
31 #define AHCI_CMD_CLR_BUSY (1 << 10)
33 #define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */
35 /* Global controller registers */
36 #define HOST_CAP 0x00 /* host capabilities */
37 #define HOST_CTL 0x04 /* global host control */
38 #define HOST_IRQ_STAT 0x08 /* interrupt status */
39 #define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */
40 #define HOST_VERSION 0x10 /* AHCI spec. version compliancy */
41 #define HOST_CAP2 0x24 /* host capabilities, extended */
44 #define HOST_RESET (1 << 0) /* reset controller; self-clear */
45 #define HOST_IRQ_EN (1 << 1) /* global IRQ enable */
46 #define HOST_AHCI_EN (1 << 31) /* AHCI enabled */
48 /* Registers for each SATA port */
49 #define PORT_LST_ADDR 0x00 /* command list DMA addr */
50 #define PORT_LST_ADDR_HI 0x04 /* command list DMA addr hi */
51 #define PORT_FIS_ADDR 0x08 /* FIS rx buf addr */
52 #define PORT_FIS_ADDR_HI 0x0c /* FIS rx buf addr hi */
53 #define PORT_IRQ_STAT 0x10 /* interrupt status */
54 #define PORT_IRQ_MASK 0x14 /* interrupt enable/disable mask */
55 #define PORT_CMD 0x18 /* port command */
56 #define PORT_TFDATA 0x20 /* taskfile data */
57 #define PORT_SIG 0x24 /* device TF signature */
58 #define PORT_CMD_ISSUE 0x38 /* command issue */
59 #define PORT_SCR 0x28 /* SATA phy register block */
60 #define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */
61 #define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */
62 #define PORT_SCR_ERR 0x30 /* SATA phy register: SError */
63 #define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */
65 /* PORT_IRQ_{STAT,MASK} bits */
66 #define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */
67 #define PORT_IRQ_TF_ERR (1 << 30) /* task file error */
68 #define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */
69 #define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */
70 #define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */
71 #define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */
72 #define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */
73 #define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */
75 #define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */
76 #define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */
77 #define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */
78 #define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */
79 #define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */
80 #define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */
81 #define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */
82 #define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */
83 #define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */
85 #define PORT_IRQ_FATAL PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR \
86 | PORT_IRQ_HBUS_DATA_ERR | PORT_IRQ_IF_ERR
88 #define DEF_PORT_IRQ PORT_IRQ_FATAL | PORT_IRQ_PHYRDY \
89 | PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE \
90 | PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS \
91 | PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS \
92 | PORT_IRQ_D2H_REG_FIS
95 #define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */
96 #define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */
97 #define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */
98 #define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */
99 #define PORT_CMD_CLO (1 << 3) /* Command list override */
100 #define PORT_CMD_POWER_ON (1 << 2) /* Power up device */
101 #define PORT_CMD_SPIN_UP (1 << 1) /* Spin up device */
102 #define PORT_CMD_START (1 << 0) /* Enable port DMA engine */
104 #define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */
105 #define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */
106 #define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */
108 #define AHCI_MAX_PORTS 32
110 /* SETFEATURES stuff */
111 #define SETFEATURES_XFER 0x03
112 #define XFER_UDMA_7 0x47
113 #define XFER_UDMA_6 0x46
114 #define XFER_UDMA_5 0x45
115 #define XFER_UDMA_4 0x44
116 #define XFER_UDMA_3 0x43
117 #define XFER_UDMA_2 0x42
118 #define XFER_UDMA_1 0x41
119 #define XFER_UDMA_0 0x40
120 #define XFER_MW_DMA_2 0x22
121 #define XFER_MW_DMA_1 0x21
122 #define XFER_MW_DMA_0 0x20
123 #define XFER_SW_DMA_2 0x12
124 #define XFER_SW_DMA_1 0x11
125 #define XFER_SW_DMA_0 0x10
126 #define XFER_PIO_4 0x0C
127 #define XFER_PIO_3 0x0B
128 #define XFER_PIO_2 0x0A
129 #define XFER_PIO_1 0x09
130 #define XFER_PIO_0 0x08
131 #define XFER_PIO_SLOW 0x00
133 #define ATA_FLAG_SATA (1 << 3)
134 #define ATA_FLAG_NO_LEGACY (1 << 4) /* no legacy mode check */
135 #define ATA_FLAG_MMIO (1 << 6) /* use MMIO, not PIO */
136 #define ATA_FLAG_SATA_RESET (1 << 7) /* (obsolete) use COMRESET */
137 #define ATA_FLAG_PIO_DMA (1 << 8) /* PIO cmds via DMA */
138 #define ATA_FLAG_NO_ATAPI (1 << 11) /* No ATAPI support */
140 struct ahci_cmd_hdr {
155 struct ahci_ioports {
159 struct ahci_cmd_hdr *cmd_slot;
160 struct ahci_sg *cmd_tbl_sg;
165 struct ahci_probe_ent {
167 struct ahci_ioports port[AHCI_MAX_PORTS];
176 u32 cap; /* cache of HOST_CAP register */
177 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
178 u32 link_port_map; /*linkup port map*/
181 int ahci_init(u32 base);