2 * include/asm-armnommu/arch-netarm/netarm_dma_module.h
4 * Copyright (C) 2000 NETsilicon, Inc.
5 * Copyright (C) 2000 WireSpeed Communications Corporation
7 * This software is copyrighted by WireSpeed. LICENSEE agrees that
8 * it will not delete this copyright notice, trademarks or protective
9 * notices from any copy made by LICENSEE.
11 * This software is provided "AS-IS" and any express or implied
12 * warranties or conditions, including but not limited to any
13 * implied warranties of merchantability and fitness for a particular
14 * purpose regarding this software. In no event shall WireSpeed
15 * be liable for any indirect, consequential, or incidental damages,
16 * loss of profits or revenue, loss of use or data, or interruption
17 * of business, whether the alleged damages are labeled in contract,
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 * author(s) : Joe deBlaquiere
33 #ifndef __NETARM_DMA_MODULE_REGISTERS_H
34 #define __NETARM_DMA_MODULE_REGISTERS_H
36 /* GEN unit register offsets */
38 #define NETARM_DMA_MODULE_BASE (0xFF900000)
40 #define get_dma_reg_addr(c) ((volatile unsigned int *)(NETARM_DMA_MODULE_BASE + (c)))
42 #define NETARM_DMA1A_BFR_DESCRPTOR_PTR (0x00)
43 #define NETARM_DMA1A_CONTROL (0x10)
44 #define NETARM_DMA1A_STATUS (0x14)
45 #define NETARM_DMA1B_BFR_DESCRPTOR_PTR (0x20)
46 #define NETARM_DMA1B_CONTROL (0x30)
47 #define NETARM_DMA1B_STATUS (0x34)
48 #define NETARM_DMA1C_BFR_DESCRPTOR_PTR (0x40)
49 #define NETARM_DMA1C_CONTROL (0x50)
50 #define NETARM_DMA1C_STATUS (0x54)
51 #define NETARM_DMA1D_BFR_DESCRPTOR_PTR (0x60)
52 #define NETARM_DMA1D_CONTROL (0x70)
53 #define NETARM_DMA1D_STATUS (0x74)
55 #define NETARM_DMA2_BFR_DESCRPTOR_PTR (0x80)
56 #define NETARM_DMA2_CONTROL (0x90)
57 #define NETARM_DMA2_STATUS (0x94)
59 #define NETARM_DMA3_BFR_DESCRPTOR_PTR (0xA0)
60 #define NETARM_DMA3_CONTROL (0xB0)
61 #define NETARM_DMA3_STATUS (0xB4)
63 #define NETARM_DMA4_BFR_DESCRPTOR_PTR (0xC0)
64 #define NETARM_DMA4_CONTROL (0xD0)
65 #define NETARM_DMA4_STATUS (0xD4)
67 #define NETARM_DMA5_BFR_DESCRPTOR_PTR (0xE0)
68 #define NETARM_DMA5_CONTROL (0xF0)
69 #define NETARM_DMA5_STATUS (0xF4)
71 #define NETARM_DMA6_BFR_DESCRPTOR_PTR (0x100)
72 #define NETARM_DMA6_CONTROL (0x110)
73 #define NETARM_DMA6_STATUS (0x114)
75 #define NETARM_DMA7_BFR_DESCRPTOR_PTR (0x120)
76 #define NETARM_DMA7_CONTROL (0x130)
77 #define NETARM_DMA7_STATUS (0x134)
79 #define NETARM_DMA8_BFR_DESCRPTOR_PTR (0x140)
80 #define NETARM_DMA8_CONTROL (0x150)
81 #define NETARM_DMA8_STATUS (0x154)
83 #define NETARM_DMA9_BFR_DESCRPTOR_PTR (0x160)
84 #define NETARM_DMA9_CONTROL (0x170)
85 #define NETARM_DMA9_STATUS (0x174)
87 #define NETARM_DMA10_BFR_DESCRPTOR_PTR (0x180)
88 #define NETARM_DMA10_CONTROL (0x190)
89 #define NETARM_DMA10_STATUS (0x194)
91 /* select bitfield defintions */
93 /* DMA Control Register ( 0xFF90_0XX0 ) */
95 #define NETARM_DMA_CTL_ENABLE (0x80000000)
97 #define NETARM_DMA_CTL_ABORT (0x40000000)
99 #define NETARM_DMA_CTL_BUS_100_PERCENT (0x00000000)
100 #define NETARM_DMA_CTL_BUS_75_PERCENT (0x10000000)
101 #define NETARM_DMA_CTL_BUS_50_PERCENT (0x20000000)
102 #define NETARM_DMA_CTL_BUS_25_PERCENT (0x30000000)
104 #define NETARM_DMA_CTL_BUS_MASK (0x30000000)
106 #define NETARM_DMA_CTL_MODE_FB_TO_MEM (0x00000000)
107 #define NETARM_DMA_CTL_MODE_FB_FROM_MEM (0x04000000)
108 #define NETARM_DMA_CTL_MODE_MEM_TO_MEM (0x08000000)
110 #define NETARM_DMA_CTL_BURST_NONE (0x00000000)
111 #define NETARM_DMA_CTL_BURST_8_BYTE (0x01000000)
112 #define NETARM_DMA_CTL_BURST_16_BYTE (0x02000000)
114 #define NETARM_DMA_CTL_BURST_MASK (0x03000000)
116 #define NETARM_DMA_CTL_SRC_INCREMENT (0x00200000)
118 #define NETARM_DMA_CTL_DST_INCREMENT (0x00100000)
120 /* these apply only to ext xfers on DMA 3 or 4 */
122 #define NETARM_DMA_CTL_CH_3_4_REQ_EXT (0x00800000)
124 #define NETARM_DMA_CTL_CH_3_4_DATA_32 (0x00000000)
125 #define NETARM_DMA_CTL_CH_3_4_DATA_16 (0x00010000)
126 #define NETARM_DMA_CTL_CH_3_4_DATA_8 (0x00020000)
128 #define NETARM_DMA_CTL_STATE(X) ((X) & 0xFC00)
129 #define NETARM_DMA_CTL_INDEX(X) ((X) & 0x03FF)
131 /* DMA Status Register ( 0xFF90_0XX4 ) */
133 #define NETARM_DMA_STAT_NC_INTPEN (0x80000000)
134 #define NETARM_DMA_STAT_EC_INTPEN (0x40000000)
135 #define NETARM_DMA_STAT_NR_INTPEN (0x20000000)
136 #define NETARM_DMA_STAT_CA_INTPEN (0x10000000)
137 #define NETARM_DMA_STAT_INTPEN_MASK (0xF0000000)
139 #define NETARM_DMA_STAT_NC_INT_EN (0x00800000)
140 #define NETARM_DMA_STAT_EC_INT_EN (0x00400000)
141 #define NETARM_DMA_STAT_NR_INT_EN (0x00200000)
142 #define NETARM_DMA_STAT_CA_INT_EN (0x00100000)
143 #define NETARM_DMA_STAT_INT_EN_MASK (0x00F00000)
145 #define NETARM_DMA_STAT_WRAP (0x00080000)
146 #define NETARM_DMA_STAT_IDONE (0x00040000)
147 #define NETARM_DMA_STAT_LAST (0x00020000)
148 #define NETARM_DMA_STAT_FULL (0x00010000)
150 #define NETARM_DMA_STAT_BUFLEN(X) ((X) & 0x7FFF)
152 /* DMA Buffer Descriptor Word 0 bitfields. */
154 #define NETARM_DMA_BD0_WRAP (0x80000000)
155 #define NETARM_DMA_BD0_IDONE (0x40000000)
156 #define NETARM_DMA_BD0_LAST (0x20000000)
157 #define NETARM_DMA_BD0_BUFPTR_MASK (0x1FFFFFFF)
159 /* DMA Buffer Descriptor Word 1 bitfields. */
161 #define NETARM_DMA_BD1_STATUS_MASK (0xFFFF0000)
162 #define NETARM_DMA_BD1_FULL (0x00008000)
163 #define NETARM_DMA_BD1_BUFLEN_MASK (0x00007FFF)
165 #ifndef __ASSEMBLER__
167 typedef struct __NETARM_DMA_Buff_Desc_FlyBy
171 } NETARM_DMA_Buff_Desc_FlyBy, *pNETARM_DMA_Buff_Desc_FlyBy ;
173 typedef struct __NETARM_DMA_Buff_Desc_M_to_M
179 } NETARM_DMA_Buff_Desc_M_to_M, *pNETARM_DMA_Buff_Desc_M_to_M ;