2 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
13 #ifndef __MACH_MX35_IOMUX_H__
14 #define __MACH_MX35_IOMUX_H__
16 #include <asm/arch/mx35.h>
19 * @file mach-mx35/iomux.h
21 * @brief I/O Muxing control definitions and functions
27 * various IOMUX functions
29 typedef enum iomux_pin_config {
30 MUX_CONFIG_FUNC = 0, /*!< used as function */
31 MUX_CONFIG_ALT1, /*!< used as alternate function 1 */
32 MUX_CONFIG_ALT2, /*!< used as alternate function 2 */
33 MUX_CONFIG_ALT3, /*!< used as alternate function 3 */
34 MUX_CONFIG_ALT4, /*!< used as alternate function 4 */
35 MUX_CONFIG_ALT5, /*!< used as alternate function 5 */
36 MUX_CONFIG_ALT6, /*!< used as alternate function 6 */
37 MUX_CONFIG_ALT7, /*!< used as alternate function 7 */
38 MUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */
39 MUX_CONFIG_GPIO = MUX_CONFIG_ALT5, /*!< used as GPIO */
43 * various IOMUX pad functions
45 typedef enum iomux_pad_config {
46 PAD_CTL_DRV_3_3V = 0x0 << 13,
47 PAD_CTL_DRV_1_8V = 0x1 << 13,
48 PAD_CTL_HYS_CMOS = 0x0 << 8,
49 PAD_CTL_HYS_SCHMITZ = 0x1 << 8,
50 PAD_CTL_PKE_NONE = 0x0 << 7,
51 PAD_CTL_PKE_ENABLE = 0x1 << 7,
52 PAD_CTL_PUE_KEEPER = 0x0 << 6,
53 PAD_CTL_PUE_PUD = 0x1 << 6,
54 PAD_CTL_100K_PD = 0x0 << 4,
55 PAD_CTL_47K_PU = 0x1 << 4,
56 PAD_CTL_100K_PU = 0x2 << 4,
57 PAD_CTL_22K_PU = 0x3 << 4,
58 PAD_CTL_ODE_CMOS = 0x0 << 3,
59 PAD_CTL_ODE_OpenDrain = 0x1 << 3,
60 PAD_CTL_DRV_NORMAL = 0x0 << 1,
61 PAD_CTL_DRV_HIGH = 0x1 << 1,
62 PAD_CTL_DRV_MAX = 0x2 << 1,
63 PAD_CTL_SRE_SLOW = 0x0 << 0,
64 PAD_CTL_SRE_FAST = 0x1 << 0
68 * various IOMUX general purpose functions
70 typedef enum iomux_gp_func {
71 MUX_SDCTL_CSD0_SEL = 0x1 << 0,
72 MUX_SDCTL_CSD1_SEL = 0x1 << 1,
73 MUX_TAMPER_DETECT_EN = 0x1 << 2,
77 * various IOMUX input select register index
79 typedef enum iomux_input_select {
80 MUX_IN_AMX_P5_RXCLK = 0,
95 MUX_IN_CSPI2_DATAREADY_B,
102 MUX_IN_EMI_WEIM_DTACK_B,
103 MUX_IN_ESDHC1_DAT4_IN,
104 MUX_IN_ESDHC1_DAT5_IN,
105 MUX_IN_ESDHC1_DAT6_IN,
106 MUX_IN_ESDHC1_DAT7_IN,
107 MUX_IN_ESDHC3_CARD_CLK_IN,
108 MUX_IN_ESDHC3_CMD_IN,
174 MUX_IN_IPU_DISPB_D0_VSYNC,
175 MUX_IN_IPU_DISPB_D12_VSYNC,
176 MUX_IN_IPU_DISPB_SD_D,
177 MUX_IN_IPU_SENSB_DATA_0,
178 MUX_IN_IPU_SENSB_DATA_1,
179 MUX_IN_IPU_SENSB_DATA_2,
180 MUX_IN_IPU_SENSB_DATA_3,
181 MUX_IN_IPU_SENSB_DATA_4,
182 MUX_IN_IPU_SENSB_DATA_5,
183 MUX_IN_IPU_SENSB_DATA_6,
184 MUX_IN_IPU_SENSB_DATA_7,
201 MUX_IN_OWIRE_BATTERY_LINE,
202 MUX_IN_SPDIF_HCKT_CLK2,
203 MUX_IN_SPDIF_SPDIF_IN1,
204 MUX_IN_UART3_UART_RTS_B,
205 MUX_IN_UART3_UART_RXD_MUX,
206 MUX_IN_USB_OTG_DATA_0,
207 MUX_IN_USB_OTG_DATA_1,
208 MUX_IN_USB_OTG_DATA_2,
209 MUX_IN_USB_OTG_DATA_3,
210 MUX_IN_USB_OTG_DATA_4,
211 MUX_IN_USB_OTG_DATA_5,
212 MUX_IN_USB_OTG_DATA_6,
213 MUX_IN_USB_OTG_DATA_7,
216 MUX_IN_USB_UH2_DATA_0,
217 MUX_IN_USB_UH2_DATA_1,
218 MUX_IN_USB_UH2_DATA_2,
219 MUX_IN_USB_UH2_DATA_3,
220 MUX_IN_USB_UH2_DATA_4,
221 MUX_IN_USB_UH2_DATA_5,
222 MUX_IN_USB_UH2_DATA_6,
223 MUX_IN_USB_UH2_DATA_7,
226 MUX_IN_USB_UH2_USB_OC,
227 } iomux_input_select_t;
230 * various IOMUX input functions
232 typedef enum iomux_input_config {
233 INPUT_CTL_PATH0 = 0x0,
244 * Request ownership for an IO pin. This function has to be the first one
245 * being called before that pin is used. The caller has to check the
246 * return value to make sure it returns 0.
248 * @param pin a name defined by \b iomux_pin_name_t
249 * @param cfg an input function as defined in \b #iomux_pin_cfg_t
251 * @return 0 if successful; Non-zero otherwise
253 int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg);
256 * Release ownership for an IO pin
258 * @param pin a name defined by \b iomux_pin_name_t
259 * @param cfg an input function as defined in \b #iomux_pin_cfg_t
261 void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg);
264 * This function enables/disables the general purpose function for a particular
267 * @param gp one signal as defined in \b #iomux_gp_func_t
268 * @param en \b #true to enable; \b #false to disable
270 void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en);
273 * This function configures the pad value for a IOMUX pin.
275 * @param pin a pin number as defined in \b #iomux_pin_name_t
276 * @param config the ORed value of elements defined in \b
277 * #iomux_pad_config_t
279 void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
282 * This function configures input path.
284 * @param input index of input select register as defined in \b
285 * #iomux_input_select_t
286 * @param config the binary value of elements defined in \b
289 void mxc_iomux_set_input(iomux_input_select_t input, u32 config);