1 /* linux/include/asm-arm/arch-bast/dma.h
3 * Copyright (C) 2003,2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * Samsung S3C2410X DMA support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * ??-May-2003 BJD Created file
14 * ??-Jun-2003 BJD Added more dma functionality to go with arch
15 * 10-Nov-2004 BJD Added sys_device support
18 #ifndef __ASM_ARCH_DMA_H
19 #define __ASM_ARCH_DMA_H __FILE__
21 #include <linux/sysdev.h>
26 * This is the maximum DMA address(physical address) that can be DMAd to.
29 #define MAX_DMA_ADDRESS 0x20000000
30 #define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
33 /* we have 4 dma channels */
34 #define S3C2410_DMA_CHANNELS (4)
38 enum s3c2410_dma_state {
45 /* enum s3c2410_dma_loadst
47 * This represents the state of the DMA engine, wrt to the loaded / running
48 * transfers. Since we don't have any way of knowing exactly the state of
49 * the DMA transfers, we need to know the state to make decisions on wether
54 * There are no buffers loaded (the channel should be inactive)
58 * There is one buffer loaded, however it has not been confirmed to be
59 * loaded by the DMA engine. This may be because the channel is not
60 * yet running, or the DMA driver decided that it was too costly to
61 * sit and wait for it to happen.
63 * S3C2410_DMA_1RUNNING
65 * The buffer has been confirmed running, and not finisged
67 * S3C2410_DMA_1LOADED_1RUNNING
69 * There is a buffer waiting to be loaded by the DMA engine, and one
73 enum s3c2410_dma_loadst {
75 S3C2410_DMALOAD_1LOADED,
76 S3C2410_DMALOAD_1RUNNING,
77 S3C2410_DMALOAD_1LOADED_1RUNNING,
80 enum s3c2410_dma_buffresult {
88 S3C2410_DMASRC_HW, /* source is memory */
89 S3C2410_DMASRC_MEM /* source is hardware */
92 /* enum s3c2410_chan_op
94 * operation codes passed to the DMA code by the user, and also used
95 * to inform the current channel owner of any changes to the system state
98 enum s3c2410_chan_op {
102 S3C2410_DMAOP_RESUME,
104 S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */
105 S3C2410_DMAOP_STARTED, /* indicate channel started */
110 #define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about
111 * waiting for reloads */
112 #define S3C2410_DMAF_AUTOSTART (1<<1) /* auto-start if buffer queued */
116 struct s3c2410_dma_client {
122 * internally used buffer structure to describe a queued or running
126 struct s3c2410_dma_buf;
127 struct s3c2410_dma_buf {
128 struct s3c2410_dma_buf *next;
129 int magic; /* magic */
130 int size; /* buffer size in bytes */
131 dma_addr_t data; /* start of DMA data */
132 dma_addr_t ptr; /* where the DMA got to [1] */
133 void *id; /* client's id */
136 /* [1] is this updated for both recv/send modes? */
138 struct s3c2410_dma_chan;
140 /* s3c2410_dma_cbfn_t
142 * buffer callback routine type
145 typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
147 enum s3c2410_dma_buffresult result);
149 typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
150 enum s3c2410_chan_op );
152 struct s3c2410_dma_stats {
154 unsigned long timeout_longest;
155 unsigned long timeout_shortest;
156 unsigned long timeout_avg;
157 unsigned long timeout_failed;
160 /* struct s3c2410_dma_chan
162 * full state information for each DMA channel
165 struct s3c2410_dma_chan {
166 /* channel state flags and information */
167 unsigned char number; /* number of this dma channel */
168 unsigned char in_use; /* channel allocated */
169 unsigned char irq_claimed; /* irq claimed for channel */
170 unsigned char irq_enabled; /* irq enabled for channel */
171 unsigned char xfer_unit; /* size of an transfer */
175 enum s3c2410_dma_state state;
176 enum s3c2410_dma_loadst load_state;
177 struct s3c2410_dma_client *client;
179 /* channel configuration */
180 enum s3c2410_dmasrc source;
181 unsigned long dev_addr;
182 unsigned long load_timeout;
183 unsigned int flags; /* channel flags */
185 /* channel's hardware position and configuration */
186 void __iomem *regs; /* channels registers */
187 void __iomem *addr_reg; /* data address register */
188 unsigned int irq; /* channel irq */
189 unsigned long dcon; /* default value of DCON */
192 s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */
193 s3c2410_dma_opfn_t op_fn; /* channel operation callback */
195 /* stats gathering */
196 struct s3c2410_dma_stats *stats;
197 struct s3c2410_dma_stats stats_store;
199 /* buffer list and information */
200 struct s3c2410_dma_buf *curr; /* current dma buffer */
201 struct s3c2410_dma_buf *next; /* next buffer to load */
202 struct s3c2410_dma_buf *end; /* end of queue */
205 struct sys_device dev;
208 /* the currently allocated channel information */
209 extern struct s3c2410_dma_chan s3c2410_chans[];
211 /* note, we don't really use dma_device_t at the moment */
212 typedef unsigned long dma_device_t;
214 /* functions --------------------------------------------------------------- */
216 /* s3c2410_dma_request
218 * request a dma channel exclusivley
221 extern int s3c2410_dma_request(dmach_t channel,
222 struct s3c2410_dma_client *, void *dev);
227 * change the state of the dma channel
230 extern int s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op);
232 /* s3c2410_dma_setflags
234 * set the channel's flags to a given state
237 extern int s3c2410_dma_setflags(dmach_t channel,
242 * free the dma channel (will also abort any outstanding operations)
245 extern int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *);
247 /* s3c2410_dma_enqueue
249 * place the given buffer onto the queue of operations for the channel.
250 * The buffer must be allocated from dma coherent memory, or the Dcache/WB
251 * drained before the buffer is given to the DMA system.
254 extern int s3c2410_dma_enqueue(dmach_t channel, void *id,
255 dma_addr_t data, int size);
257 /* s3c2410_dma_config
259 * configure the dma channel
262 extern int s3c2410_dma_config(dmach_t channel, int xferunit, int dcon);
264 /* s3c2410_dma_devconfig
266 * configure the device we're talking to
269 extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
270 int hwcfg, unsigned long devaddr);
272 /* s3c2410_dma_getposition
274 * get the position that the dma transfer is currently at
277 extern int s3c2410_dma_getposition(dmach_t channel,
278 dma_addr_t *src, dma_addr_t *dest);
280 extern int s3c2410_dma_set_opfn(dmach_t, s3c2410_dma_opfn_t rtn);
281 extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn);
283 /* DMA Register definitions */
285 #define S3C2410_DMA_DISRC (0x00)
286 #define S3C2410_DMA_DISRCC (0x04)
287 #define S3C2410_DMA_DIDST (0x08)
288 #define S3C2410_DMA_DIDSTC (0x0C)
289 #define S3C2410_DMA_DCON (0x10)
290 #define S3C2410_DMA_DSTAT (0x14)
291 #define S3C2410_DMA_DCSRC (0x18)
292 #define S3C2410_DMA_DCDST (0x1C)
293 #define S3C2410_DMA_DMASKTRIG (0x20)
295 #define S3C2410_DISRCC_INC (1<<0)
296 #define S3C2410_DISRCC_APB (1<<1)
298 #define S3C2410_DMASKTRIG_STOP (1<<2)
299 #define S3C2410_DMASKTRIG_ON (1<<1)
300 #define S3C2410_DMASKTRIG_SWTRIG (1<<0)
302 #define S3C2410_DCON_DEMAND (0<<31)
303 #define S3C2410_DCON_HANDSHAKE (1<<31)
304 #define S3C2410_DCON_SYNC_PCLK (0<<30)
305 #define S3C2410_DCON_SYNC_HCLK (1<<30)
307 #define S3C2410_DCON_INTREQ (1<<29)
309 #define S3C2410_DCON_CH0_XDREQ0 (0<<24)
310 #define S3C2410_DCON_CH0_UART0 (1<<24)
311 #define S3C2410_DCON_CH0_SDI (2<<24)
312 #define S3C2410_DCON_CH0_TIMER (3<<24)
313 #define S3C2410_DCON_CH0_USBEP1 (4<<24)
315 #define S3C2410_DCON_CH1_XDREQ1 (0<<24)
316 #define S3C2410_DCON_CH1_UART1 (1<<24)
317 #define S3C2410_DCON_CH1_I2SSDI (2<<24)
318 #define S3C2410_DCON_CH1_SPI (3<<24)
319 #define S3C2410_DCON_CH1_USBEP2 (4<<24)
321 #define S3C2410_DCON_CH2_I2SSDO (0<<24)
322 #define S3C2410_DCON_CH2_I2SSDI (1<<24)
323 #define S3C2410_DCON_CH2_SDI (2<<24)
324 #define S3C2410_DCON_CH2_TIMER (3<<24)
325 #define S3C2410_DCON_CH2_USBEP3 (4<<24)
327 #define S3C2410_DCON_CH3_UART2 (0<<24)
328 #define S3C2410_DCON_CH3_SDI (1<<24)
329 #define S3C2410_DCON_CH3_SPI (2<<24)
330 #define S3C2410_DCON_CH3_TIMER (3<<24)
331 #define S3C2410_DCON_CH3_USBEP4 (4<<24)
333 #define S3C2410_DCON_SRCSHIFT (24)
334 #define S3C2410_DCON_SRCMASK (7<<24)
336 #define S3C2410_DCON_BYTE (0<<20)
337 #define S3C2410_DCON_HALFWORD (1<<20)
338 #define S3C2410_DCON_WORD (2<<20)
340 #define S3C2410_DCON_AUTORELOAD (0<<22)
341 #define S3C2410_DCON_NORELOAD (1<<22)
342 #define S3C2410_DCON_HWTRIG (1<<23)
344 #ifdef CONFIG_CPU_S3C2440
345 #define S3C2440_DIDSTC_CHKINT (1<<2)
347 #define S3C2440_DCON_CH0_I2SSDO (5<<24)
348 #define S3C2440_DCON_CH0_PCMIN (6<<24)
350 #define S3C2440_DCON_CH1_PCMOUT (5<<24)
351 #define S3C2440_DCON_CH1_SDI (6<<24)
353 #define S3C2440_DCON_CH2_PCMIN (5<<24)
354 #define S3C2440_DCON_CH2_MICIN (6<<24)
356 #define S3C2440_DCON_CH3_MICIN (5<<24)
357 #define S3C2440_DCON_CH3_PCMOUT (6<<24)
360 #endif /* __ASM_ARCH_DMA_H */