2 * linux/include/asm-arm/atomic.h
4 * Copyright (C) 1996 Russell King.
5 * Copyright (C) 2002 Deep Blue Solutions Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #ifndef __ASM_ARM_ATOMIC_H
12 #define __ASM_ARM_ATOMIC_H
14 #include <linux/config.h>
16 typedef struct { volatile int counter; } atomic_t;
18 #define ATOMIC_INIT(i) { (i) }
22 #define atomic_read(v) ((v)->counter)
24 #if __LINUX_ARM_ARCH__ >= 6
27 * ARMv6 UP and SMP safe atomic ops. We use load exclusive and
28 * store exclusive to ensure that these are atomic. We may loop
29 * to ensure that the update happens. Writing to 'v->counter'
30 * without using the following operations WILL break the atomic
31 * nature of these ops.
33 static inline void atomic_set(atomic_t *v, int i)
37 __asm__ __volatile__("@ atomic_set\n"
39 " strex %0, %2, [%1]\n"
43 : "r" (&v->counter), "r" (i)
47 static inline int atomic_add_return(int i, atomic_t *v)
52 __asm__ __volatile__("@ atomic_add_return\n"
55 " strex %1, %0, [%2]\n"
58 : "=&r" (result), "=&r" (tmp)
59 : "r" (&v->counter), "Ir" (i)
65 static inline int atomic_sub_return(int i, atomic_t *v)
70 __asm__ __volatile__("@ atomic_sub_return\n"
73 " strex %1, %0, [%2]\n"
76 : "=&r" (result), "=&r" (tmp)
77 : "r" (&v->counter), "Ir" (i)
83 static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
88 __asm__ __volatile__("@ atomic_cmpxchg\n"
91 "strexeq %0, %4, [%2]\n"
92 : "=&r" (res), "=&r" (oldval)
93 : "r" (&ptr->counter), "Ir" (old), "r" (new)
100 static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
102 unsigned long tmp, tmp2;
104 __asm__ __volatile__("@ atomic_clear_mask\n"
107 " strex %1, %0, %2\n"
110 : "=&r" (tmp), "=&r" (tmp2)
111 : "r" (addr), "Ir" (mask)
115 #else /* ARM_ARCH_6 */
117 #include <asm/system.h>
120 #error SMP not supported on pre-ARMv6 CPUs
123 #define atomic_set(v,i) (((v)->counter) = (i))
125 static inline int atomic_add_return(int i, atomic_t *v)
130 local_irq_save(flags);
132 v->counter = val += i;
133 local_irq_restore(flags);
138 static inline int atomic_sub_return(int i, atomic_t *v)
143 local_irq_save(flags);
145 v->counter = val -= i;
146 local_irq_restore(flags);
151 static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
156 local_irq_save(flags);
158 if (likely(ret == old))
160 local_irq_restore(flags);
165 static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
169 local_irq_save(flags);
171 local_irq_restore(flags);
174 #endif /* __LINUX_ARM_ARCH__ */
176 static inline int atomic_add_unless(atomic_t *v, int a, int u)
181 while (c != u && (old = atomic_cmpxchg((v), c, c + a)) != c)
185 #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
187 #define atomic_add(i, v) (void) atomic_add_return(i, v)
188 #define atomic_inc(v) (void) atomic_add_return(1, v)
189 #define atomic_sub(i, v) (void) atomic_sub_return(i, v)
190 #define atomic_dec(v) (void) atomic_sub_return(1, v)
192 #define atomic_inc_and_test(v) (atomic_add_return(1, v) == 0)
193 #define atomic_dec_and_test(v) (atomic_sub_return(1, v) == 0)
194 #define atomic_inc_return(v) (atomic_add_return(1, v))
195 #define atomic_dec_return(v) (atomic_sub_return(1, v))
196 #define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)
198 #define atomic_add_negative(i,v) (atomic_add_return(i, v) < 0)
200 /* Atomic operations are already serializing on ARM */
201 #define smp_mb__before_atomic_dec() barrier()
202 #define smp_mb__after_atomic_dec() barrier()
203 #define smp_mb__before_atomic_inc() barrier()
204 #define smp_mb__after_atomic_inc() barrier()