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1 /************************************************************************
2  *
3  * cplb.h
4  *
5  * (c) Copyright 2002-2003 Analog Devices, Inc.  All rights reserved.
6  *
7  ************************************************************************/
8
9 /* Defines necessary for cplb initialisation routines. */
10
11 #ifndef _CPLB_H
12 #define _CPLB_H
13
14 #define CPLB_ENABLE_ICACHE_P    0
15 #define CPLB_ENABLE_DCACHE_P    1
16 #define CPLB_ENABLE_DCACHE2_P   2
17 #define CPLB_ENABLE_CPLBS_P     3       /* Deprecated!*/
18 #define CPLB_ENABLE_ICPLBS_P    4
19 #define CPLB_ENABLE_DCPLBS_P    5
20
21 #define CPLB_ENABLE_ICACHE      (1<<CPLB_ENABLE_ICACHE_P)
22 #define CPLB_ENABLE_DCACHE      (1<<CPLB_ENABLE_DCACHE_P)
23 #define CPLB_ENABLE_DCACHE2     (1<<CPLB_ENABLE_DCACHE2_P)
24 #define CPLB_ENABLE_CPLBS       (1<<CPLB_ENABLE_CPLBS_P)
25 #define CPLB_ENABLE_ICPLBS      (1<<CPLB_ENABLE_ICPLBS_P)
26 #define CPLB_ENABLE_DCPLBS      (1<<CPLB_ENABLE_DCPLBS_P)
27 #define CPLB_ENABLE_ANY_CPLBS   CPLB_ENABLE_CPLBS | \
28                                 CPLB_ENABLE_ICPLBS | \
29                                 CPLB_ENABLE_DCPLBS
30
31 #define CPLB_RELOADED           0x0000
32 #define CPLB_NO_UNLOCKED        0x0001
33 #define CPLB_NO_ADDR_MATCH      0x0002
34 #define CPLB_PROT_VIOL          0x0003
35
36 #define CPLB_DEF_CACHE          CPLB_L1_CHBL | CPLB_WT
37 #define CPLB_CACHE_ENABLED      CPLB_L1_CHBL | CPLB_DIRTY
38
39 #define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
40
41 #define CPLB_I_PAGE_MGMT        CPLB_LOCK | CPLB_VALID
42 #define CPLB_D_PAGE_MGMT        CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
43 #define CPLB_DNOCACHE           CPLB_ALL_ACCESS | CPLB_VALID
44 #define CPLB_DDOCACHE           CPLB_DNOCACHE | CPLB_DEF_CACHE
45 #define CPLB_INOCACHE           CPLB_USER_RD | CPLB_VALID
46 #define CPLB_IDOCACHE           CPLB_INOCACHE | CPLB_L1_CHBL
47
48 #endif /* _CPLB_H */