5 * Access to machine-specific registers (available on 586 and better only)
6 * Note: the rd* operations modify the parameters directly (without using
7 * pointer indirection), this allows gcc to optimize better
10 #define rdmsr(msr,val1,val2) \
11 __asm__ __volatile__("rdmsr" \
12 : "=a" (val1), "=d" (val2) \
15 #define wrmsr(msr,val1,val2) \
16 __asm__ __volatile__("wrmsr" \
18 : "c" (msr), "a" (val1), "d" (val2))
20 #define rdmsrl(msr,val) do { \
21 unsigned long l__,h__; \
22 rdmsr (msr, l__, h__); \
24 val |= ((u64)h__<<32); \
27 static inline void wrmsrl (unsigned long msr, unsigned long long val)
30 lo = (unsigned long) val;
35 /* wrmsr with exception handling */
36 #define wrmsr_safe(msr,a,b) ({ int ret__; \
37 asm volatile("2: wrmsr ; xorl %0,%0\n" \
39 ".section .fixup,\"ax\"\n\t" \
40 "3: movl %4,%0 ; jmp 1b\n\t" \
42 ".section __ex_table,\"a\"\n" \
47 : "c" (msr), "0" (a), "d" (b), "i" (-EFAULT));\
50 /* rdmsr with exception handling */
51 #define rdmsr_safe(msr,a,b) ({ int ret__; \
52 asm volatile("2: rdmsr ; xorl %0,%0\n" \
54 ".section .fixup,\"ax\"\n\t" \
55 "3: movl %4,%0 ; jmp 1b\n\t" \
57 ".section __ex_table,\"a\"\n" \
61 : "=r" (ret__), "=a" (*(a)), "=d" (*(b)) \
62 : "c" (msr), "i" (-EFAULT));\
65 #define rdtsc(low,high) \
66 __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
69 __asm__ __volatile__("rdtsc" : "=a" (low) : : "edx")
71 #define rdtscll(val) \
72 __asm__ __volatile__("rdtsc" : "=A" (val))
74 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
76 #define rdpmc(counter,low,high) \
77 __asm__ __volatile__("rdpmc" \
78 : "=a" (low), "=d" (high) \
81 /* symbolic names for some interesting MSRs */
82 /* Intel defined MSRs. */
83 #define MSR_IA32_P5_MC_ADDR 0
84 #define MSR_IA32_P5_MC_TYPE 1
85 #define MSR_IA32_PLATFORM_ID 0x17
86 #define MSR_IA32_EBL_CR_POWERON 0x2a
88 #define MSR_IA32_APICBASE 0x1b
89 #define MSR_IA32_APICBASE_BSP (1<<8)
90 #define MSR_IA32_APICBASE_ENABLE (1<<11)
91 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
93 #define MSR_IA32_UCODE_WRITE 0x79
94 #define MSR_IA32_UCODE_REV 0x8b
96 #define MSR_P6_PERFCTR0 0xc1
97 #define MSR_P6_PERFCTR1 0xc2
98 #define MSR_FSB_FREQ 0xcd
101 #define MSR_IA32_BBL_CR_CTL 0x119
103 #define MSR_IA32_SYSENTER_CS 0x174
104 #define MSR_IA32_SYSENTER_ESP 0x175
105 #define MSR_IA32_SYSENTER_EIP 0x176
107 #define MSR_IA32_MCG_CAP 0x179
108 #define MSR_IA32_MCG_STATUS 0x17a
109 #define MSR_IA32_MCG_CTL 0x17b
111 /* P4/Xeon+ specific */
112 #define MSR_IA32_MCG_EAX 0x180
113 #define MSR_IA32_MCG_EBX 0x181
114 #define MSR_IA32_MCG_ECX 0x182
115 #define MSR_IA32_MCG_EDX 0x183
116 #define MSR_IA32_MCG_ESI 0x184
117 #define MSR_IA32_MCG_EDI 0x185
118 #define MSR_IA32_MCG_EBP 0x186
119 #define MSR_IA32_MCG_ESP 0x187
120 #define MSR_IA32_MCG_EFLAGS 0x188
121 #define MSR_IA32_MCG_EIP 0x189
122 #define MSR_IA32_MCG_RESERVED 0x18A
124 #define MSR_P6_EVNTSEL0 0x186
125 #define MSR_P6_EVNTSEL1 0x187
127 #define MSR_IA32_PERF_STATUS 0x198
128 #define MSR_IA32_PERF_CTL 0x199
130 #define MSR_IA32_MPERF 0xE7
131 #define MSR_IA32_APERF 0xE8
133 #define MSR_IA32_THERM_CONTROL 0x19a
134 #define MSR_IA32_THERM_INTERRUPT 0x19b
135 #define MSR_IA32_THERM_STATUS 0x19c
136 #define MSR_IA32_MISC_ENABLE 0x1a0
138 #define MSR_IA32_DEBUGCTLMSR 0x1d9
139 #define MSR_IA32_LASTBRANCHFROMIP 0x1db
140 #define MSR_IA32_LASTBRANCHTOIP 0x1dc
141 #define MSR_IA32_LASTINTFROMIP 0x1dd
142 #define MSR_IA32_LASTINTTOIP 0x1de
144 #define MSR_IA32_MC0_CTL 0x400
145 #define MSR_IA32_MC0_STATUS 0x401
146 #define MSR_IA32_MC0_ADDR 0x402
147 #define MSR_IA32_MC0_MISC 0x403
149 /* Pentium IV performance counter MSRs */
150 #define MSR_P4_BPU_PERFCTR0 0x300
151 #define MSR_P4_BPU_PERFCTR1 0x301
152 #define MSR_P4_BPU_PERFCTR2 0x302
153 #define MSR_P4_BPU_PERFCTR3 0x303
154 #define MSR_P4_MS_PERFCTR0 0x304
155 #define MSR_P4_MS_PERFCTR1 0x305
156 #define MSR_P4_MS_PERFCTR2 0x306
157 #define MSR_P4_MS_PERFCTR3 0x307
158 #define MSR_P4_FLAME_PERFCTR0 0x308
159 #define MSR_P4_FLAME_PERFCTR1 0x309
160 #define MSR_P4_FLAME_PERFCTR2 0x30a
161 #define MSR_P4_FLAME_PERFCTR3 0x30b
162 #define MSR_P4_IQ_PERFCTR0 0x30c
163 #define MSR_P4_IQ_PERFCTR1 0x30d
164 #define MSR_P4_IQ_PERFCTR2 0x30e
165 #define MSR_P4_IQ_PERFCTR3 0x30f
166 #define MSR_P4_IQ_PERFCTR4 0x310
167 #define MSR_P4_IQ_PERFCTR5 0x311
168 #define MSR_P4_BPU_CCCR0 0x360
169 #define MSR_P4_BPU_CCCR1 0x361
170 #define MSR_P4_BPU_CCCR2 0x362
171 #define MSR_P4_BPU_CCCR3 0x363
172 #define MSR_P4_MS_CCCR0 0x364
173 #define MSR_P4_MS_CCCR1 0x365
174 #define MSR_P4_MS_CCCR2 0x366
175 #define MSR_P4_MS_CCCR3 0x367
176 #define MSR_P4_FLAME_CCCR0 0x368
177 #define MSR_P4_FLAME_CCCR1 0x369
178 #define MSR_P4_FLAME_CCCR2 0x36a
179 #define MSR_P4_FLAME_CCCR3 0x36b
180 #define MSR_P4_IQ_CCCR0 0x36c
181 #define MSR_P4_IQ_CCCR1 0x36d
182 #define MSR_P4_IQ_CCCR2 0x36e
183 #define MSR_P4_IQ_CCCR3 0x36f
184 #define MSR_P4_IQ_CCCR4 0x370
185 #define MSR_P4_IQ_CCCR5 0x371
186 #define MSR_P4_ALF_ESCR0 0x3ca
187 #define MSR_P4_ALF_ESCR1 0x3cb
188 #define MSR_P4_BPU_ESCR0 0x3b2
189 #define MSR_P4_BPU_ESCR1 0x3b3
190 #define MSR_P4_BSU_ESCR0 0x3a0
191 #define MSR_P4_BSU_ESCR1 0x3a1
192 #define MSR_P4_CRU_ESCR0 0x3b8
193 #define MSR_P4_CRU_ESCR1 0x3b9
194 #define MSR_P4_CRU_ESCR2 0x3cc
195 #define MSR_P4_CRU_ESCR3 0x3cd
196 #define MSR_P4_CRU_ESCR4 0x3e0
197 #define MSR_P4_CRU_ESCR5 0x3e1
198 #define MSR_P4_DAC_ESCR0 0x3a8
199 #define MSR_P4_DAC_ESCR1 0x3a9
200 #define MSR_P4_FIRM_ESCR0 0x3a4
201 #define MSR_P4_FIRM_ESCR1 0x3a5
202 #define MSR_P4_FLAME_ESCR0 0x3a6
203 #define MSR_P4_FLAME_ESCR1 0x3a7
204 #define MSR_P4_FSB_ESCR0 0x3a2
205 #define MSR_P4_FSB_ESCR1 0x3a3
206 #define MSR_P4_IQ_ESCR0 0x3ba
207 #define MSR_P4_IQ_ESCR1 0x3bb
208 #define MSR_P4_IS_ESCR0 0x3b4
209 #define MSR_P4_IS_ESCR1 0x3b5
210 #define MSR_P4_ITLB_ESCR0 0x3b6
211 #define MSR_P4_ITLB_ESCR1 0x3b7
212 #define MSR_P4_IX_ESCR0 0x3c8
213 #define MSR_P4_IX_ESCR1 0x3c9
214 #define MSR_P4_MOB_ESCR0 0x3aa
215 #define MSR_P4_MOB_ESCR1 0x3ab
216 #define MSR_P4_MS_ESCR0 0x3c0
217 #define MSR_P4_MS_ESCR1 0x3c1
218 #define MSR_P4_PMH_ESCR0 0x3ac
219 #define MSR_P4_PMH_ESCR1 0x3ad
220 #define MSR_P4_RAT_ESCR0 0x3bc
221 #define MSR_P4_RAT_ESCR1 0x3bd
222 #define MSR_P4_SAAT_ESCR0 0x3ae
223 #define MSR_P4_SAAT_ESCR1 0x3af
224 #define MSR_P4_SSU_ESCR0 0x3be
225 #define MSR_P4_SSU_ESCR1 0x3bf /* guess: not defined in manual */
226 #define MSR_P4_TBPU_ESCR0 0x3c2
227 #define MSR_P4_TBPU_ESCR1 0x3c3
228 #define MSR_P4_TC_ESCR0 0x3c4
229 #define MSR_P4_TC_ESCR1 0x3c5
230 #define MSR_P4_U2L_ESCR0 0x3b0
231 #define MSR_P4_U2L_ESCR1 0x3b1
233 /* AMD Defined MSRs */
234 #define MSR_K6_EFER 0xC0000080
235 #define MSR_K6_STAR 0xC0000081
236 #define MSR_K6_WHCR 0xC0000082
237 #define MSR_K6_UWCCR 0xC0000085
238 #define MSR_K6_EPMR 0xC0000086
239 #define MSR_K6_PSOR 0xC0000087
240 #define MSR_K6_PFIR 0xC0000088
242 #define MSR_K7_EVNTSEL0 0xC0010000
243 #define MSR_K7_EVNTSEL1 0xC0010001
244 #define MSR_K7_EVNTSEL2 0xC0010002
245 #define MSR_K7_EVNTSEL3 0xC0010003
246 #define MSR_K7_PERFCTR0 0xC0010004
247 #define MSR_K7_PERFCTR1 0xC0010005
248 #define MSR_K7_PERFCTR2 0xC0010006
249 #define MSR_K7_PERFCTR3 0xC0010007
250 #define MSR_K7_HWCR 0xC0010015
251 #define MSR_K7_CLK_CTL 0xC001001b
252 #define MSR_K7_FID_VID_CTL 0xC0010041
253 #define MSR_K7_FID_VID_STATUS 0xC0010042
255 /* extended feature register */
256 #define MSR_EFER 0xc0000080
260 /* Execute Disable enable */
262 #define EFER_NX (1<<_EFER_NX)
264 /* Centaur-Hauls/IDT defined MSRs. */
265 #define MSR_IDT_FCR1 0x107
266 #define MSR_IDT_FCR2 0x108
267 #define MSR_IDT_FCR3 0x109
268 #define MSR_IDT_FCR4 0x10a
270 #define MSR_IDT_MCR0 0x110
271 #define MSR_IDT_MCR1 0x111
272 #define MSR_IDT_MCR2 0x112
273 #define MSR_IDT_MCR3 0x113
274 #define MSR_IDT_MCR4 0x114
275 #define MSR_IDT_MCR5 0x115
276 #define MSR_IDT_MCR6 0x116
277 #define MSR_IDT_MCR7 0x117
278 #define MSR_IDT_MCR_CTRL 0x120
280 /* VIA Cyrix defined MSRs*/
281 #define MSR_VIA_FCR 0x1107
282 #define MSR_VIA_LONGHAUL 0x110a
283 #define MSR_VIA_RNG 0x110b
284 #define MSR_VIA_BCR2 0x1147
286 /* Transmeta defined MSRs */
287 #define MSR_TMTA_LONGRUN_CTRL 0x80868010
288 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011
289 #define MSR_TMTA_LRTI_READOUT 0x80868018
290 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
292 #endif /* __ASM_MSR_H */