2 * MT regs definitions, follows on from mipsregs.h
3 * Copyright (C) 2004 - 2005 MIPS Technologies, Inc. All rights reserved.
4 * Elizabeth Clarke et. al.
7 #ifndef _ASM_MIPSMTREGS_H
8 #define _ASM_MIPSMTREGS_H
18 #define read_c0_mvpcontrol() __read_32bit_c0_register($0, 1)
19 #define write_c0_mvpcontrol(val) __write_32bit_c0_register($0, 1, val)
21 #define read_c0_mvpconf0() __read_32bit_c0_register($0, 2)
22 #define read_c0_mvpconf1() __read_32bit_c0_register($0, 3)
24 #define read_c0_vpecontrol() __read_32bit_c0_register($1, 1)
25 #define write_c0_vpecontrol(val) __write_32bit_c0_register($1, 1, val)
27 #define read_c0_vpeconf0() __read_32bit_c0_register($1, 2)
28 #define write_c0_vpeconf0(val) __write_32bit_c0_register($1, 2, val)
30 #define read_c0_tcstatus() __read_32bit_c0_register($2, 1)
31 #define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val)
33 #define read_c0_tcbind() __read_32bit_c0_register($2, 2)
35 #define read_c0_tccontext() __read_32bit_c0_register($2, 5)
36 #define write_c0_tccontext(val) __write_32bit_c0_register($2, 5, val)
40 * Macros for use in assembly language code
43 #define CP0_MVPCONTROL $0,1
44 #define CP0_MVPCONF0 $0,2
45 #define CP0_MVPCONF1 $0,3
46 #define CP0_VPECONTROL $1,1
47 #define CP0_VPECONF0 $1,2
48 #define CP0_VPECONF1 $1,3
49 #define CP0_YQMASK $1,4
50 #define CP0_VPESCHEDULE $1,5
51 #define CP0_VPESCHEFBK $1,6
52 #define CP0_TCSTATUS $2,1
53 #define CP0_TCBIND $2,2
54 #define CP0_TCRESTART $2,3
55 #define CP0_TCHALT $2,4
56 #define CP0_TCCONTEXT $2,5
57 #define CP0_TCSCHEDULE $2,6
58 #define CP0_TCSCHEFBK $2,7
59 #define CP0_SRSCONF0 $6,1
60 #define CP0_SRSCONF1 $6,2
61 #define CP0_SRSCONF2 $6,3
62 #define CP0_SRSCONF3 $6,4
63 #define CP0_SRSCONF4 $6,5
67 /* MVPControl fields */
68 #define MVPCONTROL_EVP (_ULCAST_(1))
70 #define MVPCONTROL_VPC_SHIFT 1
71 #define MVPCONTROL_VPC (_ULCAST_(1) << MVPCONTROL_VPC_SHIFT)
73 #define MVPCONTROL_STLB_SHIFT 2
74 #define MVPCONTROL_STLB (_ULCAST_(1) << MVPCONTROL_STLB_SHIFT)
78 #define MVPCONF0_PTC_SHIFT 0
79 #define MVPCONF0_PTC ( _ULCAST_(0xff))
80 #define MVPCONF0_PVPE_SHIFT 10
81 #define MVPCONF0_PVPE ( _ULCAST_(0xf) << MVPCONF0_PVPE_SHIFT)
82 #define MVPCONF0_TCA_SHIFT 15
83 #define MVPCONF0_TCA ( _ULCAST_(1) << MVPCONF0_TCA_SHIFT)
84 #define MVPCONF0_PTLBE_SHIFT 16
85 #define MVPCONF0_PTLBE (_ULCAST_(0x3ff) << MVPCONF0_PTLBE_SHIFT)
86 #define MVPCONF0_TLBS_SHIFT 29
87 #define MVPCONF0_TLBS (_ULCAST_(1) << MVPCONF0_TLBS_SHIFT)
88 #define MVPCONF0_M_SHIFT 31
89 #define MVPCONF0_M (_ULCAST_(0x1) << MVPCONF0_M_SHIFT)
93 #define CONFIG3_MT_SHIFT 2
94 #define CONFIG3_MT (_ULCAST_(1) << CONFIG3_MT_SHIFT)
97 /* VPEControl fields (per VPE) */
98 #define VPECONTROL_TARGTC (_ULCAST_(0xff))
100 #define VPECONTROL_TE_SHIFT 15
101 #define VPECONTROL_TE (_ULCAST_(1) << VPECONTROL_TE_SHIFT)
102 #define VPECONTROL_EXCPT_SHIFT 16
103 #define VPECONTROL_EXCPT (_ULCAST_(0x7) << VPECONTROL_EXCPT_SHIFT)
105 /* Thread Exception Codes for EXCPT field */
111 #define THREX_GSSCH 5
113 #define VPECONTROL_GSI_SHIFT 20
114 #define VPECONTROL_GSI (_ULCAST_(1) << VPECONTROL_GSI_SHIFT)
115 #define VPECONTROL_YSI_SHIFT 21
116 #define VPECONTROL_YSI (_ULCAST_(1) << VPECONTROL_YSI_SHIFT)
118 /* VPEConf0 fields (per VPE) */
119 #define VPECONF0_VPA_SHIFT 0
120 #define VPECONF0_VPA (_ULCAST_(1) << VPECONF0_VPA_SHIFT)
121 #define VPECONF0_MVP_SHIFT 1
122 #define VPECONF0_MVP (_ULCAST_(1) << VPECONF0_MVP_SHIFT)
123 #define VPECONF0_XTC_SHIFT 21
124 #define VPECONF0_XTC (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT)
126 /* TCStatus fields (per TC) */
127 #define TCSTATUS_TASID (_ULCAST_(0xff))
128 #define TCSTATUS_IXMT_SHIFT 10
129 #define TCSTATUS_IXMT (_ULCAST_(1) << TCSTATUS_IXMT_SHIFT)
130 #define TCSTATUS_TKSU_SHIFT 11
131 #define TCSTATUS_TKSU (_ULCAST_(3) << TCSTATUS_TKSU_SHIFT)
132 #define TCSTATUS_A_SHIFT 13
133 #define TCSTATUS_A (_ULCAST_(1) << TCSTATUS_A_SHIFT)
134 #define TCSTATUS_DA_SHIFT 15
135 #define TCSTATUS_DA (_ULCAST_(1) << TCSTATUS_DA_SHIFT)
136 #define TCSTATUS_DT_SHIFT 20
137 #define TCSTATUS_DT (_ULCAST_(1) << TCSTATUS_DT_SHIFT)
138 #define TCSTATUS_TDS_SHIFT 21
139 #define TCSTATUS_TDS (_ULCAST_(1) << TCSTATUS_TDS_SHIFT)
140 #define TCSTATUS_TSST_SHIFT 22
141 #define TCSTATUS_TSST (_ULCAST_(1) << TCSTATUS_TSST_SHIFT)
142 #define TCSTATUS_RNST_SHIFT 23
143 #define TCSTATUS_RNST (_ULCAST_(3) << TCSTATUS_RNST_SHIFT)
147 #define TC_YIELDING 2
150 #define TCSTATUS_TMX_SHIFT 27
151 #define TCSTATUS_TMX (_ULCAST_(1) << TCSTATUS_TMX_SHIFT)
152 /* TCStatus TCU bits can use same definitions/offsets as CU bits in Status */
155 #define TCBIND_CURVPE_SHIFT 0
156 #define TCBIND_CURVPE (_ULCAST_(0xf))
158 #define TCBIND_CURTC_SHIFT 21
160 #define TCBIND_CURTC (_ULCAST_(0xff) << TCBIND_CURTC_SHIFT)
163 #define TCHALT_H (_ULCAST_(1))
167 extern void mips_mt_regdump(void);
169 static inline unsigned int dvpe(void)
173 __asm__ __volatile__(
178 " .word 0x41610001 # dvpe $1 \n"
184 instruction_hazard();
189 static inline void __raw_evpe(void)
191 __asm__ __volatile__(
196 " .word 0x41600021 # evpe \n"
201 /* Enable multiMT if previous suggested it should be.
202 EMT_ENABLE to force */
204 #define EVPE_ENABLE MVPCONTROL_EVP
206 static inline void evpe(int previous)
208 if ((previous & MVPCONTROL_EVP))
212 static inline unsigned int dmt(void)
216 __asm__ __volatile__(
220 " .word 0x41610BC1 # dmt $1 \n"
226 instruction_hazard();
231 static inline void __raw_emt(void)
233 __asm__ __volatile__(
242 /* enable multiVPE if previous suggested it should be.
243 EVPE_ENABLE to force */
245 #define EMT_ENABLE VPECONTROL_TE
247 static inline void emt(int previous)
249 if ((previous & EMT_ENABLE))
253 static inline void ehb(void)
255 __asm__ __volatile__(
261 #define mftc0(rt,sel) \
263 unsigned long __res; \
265 __asm__ __volatile__( \
267 " .set mips32r2 \n" \
269 " # mftc0 $1, $" #rt ", " #sel " \n" \
270 " .word 0x41000800 | (" #rt " << 16) | " #sel " \n" \
280 unsigned long __res; \
282 __asm__ __volatile__( \
284 " .set mips32r2 \n" \
285 " mftgpr %0," #rt " \n" \
292 #define mftr(rt,u,sel) \
294 unsigned long __res; \
296 __asm__ __volatile__( \
298 "mftr\t%0, " #rt ", " #u ", " #sel "\n\t" \
305 #define mttgpr(rd,v) \
307 __asm__ __volatile__( \
309 " .set mips32r2 \n" \
312 " # mttgpr $1, " #rd " \n" \
313 " .word 0x41810020 | (" #rd " << 11) \n" \
318 #define mttc0(rd,sel,v) \
320 __asm__ __volatile__( \
322 " .set mips32r2 \n" \
325 " # mttc0 %0," #rd ", " #sel " \n" \
326 " .word 0x41810000 | (" #rd " << 11) | " #sel " \n" \
333 #define mttr(rd,u,sel,v) \
335 __asm__ __volatile__( \
336 "mttr %0," #rd ", " #u ", " #sel \
343 write_c0_vpecontrol((read_c0_vpecontrol()&~VPECONTROL_TARGTC) | (tc)); \
348 /* you *must* set the target tc (settc) before trying to use these */
349 #define read_vpe_c0_vpecontrol() mftc0(1, 1)
350 #define write_vpe_c0_vpecontrol(val) mttc0(1, 1, val)
351 #define read_vpe_c0_vpeconf0() mftc0(1, 2)
352 #define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val)
353 #define read_vpe_c0_status() mftc0(12, 0)
354 #define write_vpe_c0_status(val) mttc0(12, 0, val)
355 #define read_vpe_c0_cause() mftc0(13, 0)
356 #define write_vpe_c0_cause(val) mttc0(13, 0, val)
357 #define read_vpe_c0_config() mftc0(16, 0)
358 #define write_vpe_c0_config(val) mttc0(16, 0, val)
359 #define read_vpe_c0_config1() mftc0(16, 1)
360 #define write_vpe_c0_config1(val) mttc0(16, 1, val)
361 #define read_vpe_c0_config7() mftc0(16, 7)
362 #define write_vpe_c0_config7(val) mttc0(16, 7, val)
363 #define read_vpe_c0_ebase() mftc0(15,1)
364 #define write_vpe_c0_ebase(val) mttc0(15, 1, val)
365 #define write_vpe_c0_compare(val) mttc0(11, 0, val)
369 #define read_tc_c0_tcstatus() mftc0(2, 1)
370 #define write_tc_c0_tcstatus(val) mttc0(2,1,val)
371 #define read_tc_c0_tcbind() mftc0(2, 2)
372 #define write_tc_c0_tcbind(val) mttc0(2,2,val)
373 #define read_tc_c0_tcrestart() mftc0(2, 3)
374 #define write_tc_c0_tcrestart(val) mttc0(2,3,val)
375 #define read_tc_c0_tchalt() mftc0(2, 4)
376 #define write_tc_c0_tchalt(val) mttc0(2,4,val)
377 #define read_tc_c0_tccontext() mftc0(2, 5)
378 #define write_tc_c0_tccontext(val) mttc0(2,5,val)
381 #define read_tc_gpr_sp() mftgpr(29)
382 #define write_tc_gpr_sp(val) mttgpr(29, val)
383 #define read_tc_gpr_gp() mftgpr(28)
384 #define write_tc_gpr_gp(val) mttgpr(28, val)
387 #endif /* Not __ASSEMBLY__ */