2 * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
4 * Based on alpha version.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 #ifndef _ASM_POWERPC_OPROFILE_IMPL_H
13 #define _ASM_POWERPC_OPROFILE_IMPL_H
16 #define OP_MAX_COUNTER 8
18 /* Per-counter configuration as set via oprofilefs. */
19 struct op_counter_config {
20 unsigned long enabled;
23 /* Classic doesn't support per-counter user/kernel selection */
26 unsigned long unit_mask;
29 /* System-wide configuration as set via oprofilefs. */
30 struct op_system_config {
36 unsigned long enable_kernel;
37 unsigned long enable_user;
40 /* Per-arch configuration */
41 struct op_powerpc_model {
42 void (*reg_setup) (struct op_counter_config *,
43 struct op_system_config *,
45 void (*cpu_setup) (struct op_counter_config *);
46 void (*start) (struct op_counter_config *);
47 void (*global_start) (struct op_counter_config *);
49 void (*global_stop) (void);
50 void (*handle_interrupt) (struct pt_regs *,
51 struct op_counter_config *);
55 extern struct op_powerpc_model op_model_fsl_booke;
56 extern struct op_powerpc_model op_model_rs64;
57 extern struct op_powerpc_model op_model_power4;
58 extern struct op_powerpc_model op_model_7450;
59 extern struct op_powerpc_model op_model_cell;
61 #ifndef CONFIG_FSL_BOOKE
63 /* All the classic PPC parts use these */
64 static inline unsigned int ctr_read(unsigned int i)
68 return mfspr(SPRN_PMC1);
70 return mfspr(SPRN_PMC2);
72 return mfspr(SPRN_PMC3);
74 return mfspr(SPRN_PMC4);
76 return mfspr(SPRN_PMC5);
78 return mfspr(SPRN_PMC6);
80 /* No PPC32 chip has more than 6 so far */
83 return mfspr(SPRN_PMC7);
85 return mfspr(SPRN_PMC8);
92 static inline void ctr_write(unsigned int i, unsigned int val)
96 mtspr(SPRN_PMC1, val);
99 mtspr(SPRN_PMC2, val);
102 mtspr(SPRN_PMC3, val);
105 mtspr(SPRN_PMC4, val);
108 mtspr(SPRN_PMC5, val);
111 mtspr(SPRN_PMC6, val);
114 /* No PPC32 chip has more than 6, yet */
117 mtspr(SPRN_PMC7, val);
120 mtspr(SPRN_PMC8, val);
127 #else /* CONFIG_FSL_BOOKE */
128 static inline u32 get_pmlca(int ctr)
134 pmlca = mfpmr(PMRN_PMLCA0);
137 pmlca = mfpmr(PMRN_PMLCA1);
140 pmlca = mfpmr(PMRN_PMLCA2);
143 pmlca = mfpmr(PMRN_PMLCA3);
146 panic("Bad ctr number\n");
152 static inline void set_pmlca(int ctr, u32 pmlca)
156 mtpmr(PMRN_PMLCA0, pmlca);
159 mtpmr(PMRN_PMLCA1, pmlca);
162 mtpmr(PMRN_PMLCA2, pmlca);
165 mtpmr(PMRN_PMLCA3, pmlca);
168 panic("Bad ctr number\n");
172 static inline unsigned int ctr_read(unsigned int i)
176 return mfpmr(PMRN_PMC0);
178 return mfpmr(PMRN_PMC1);
180 return mfpmr(PMRN_PMC2);
182 return mfpmr(PMRN_PMC3);
188 static inline void ctr_write(unsigned int i, unsigned int val)
192 mtpmr(PMRN_PMC0, val);
195 mtpmr(PMRN_PMC1, val);
198 mtpmr(PMRN_PMC2, val);
201 mtpmr(PMRN_PMC3, val);
209 #endif /* CONFIG_FSL_BOOKE */
212 extern void op_powerpc_backtrace(struct pt_regs * const regs, unsigned int depth);
214 #endif /* __KERNEL__ */
215 #endif /* _ASM_POWERPC_OPROFILE_IMPL_H */