2 * SPU core / file system interface and HW structures
4 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
6 * Author: Arnd Bergmann <arndb@de.ibm.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 #include <linux/workqueue.h>
28 #include <linux/sysdev.h>
30 #define LS_SIZE (256 * 1024)
31 #define LS_ADDR_MASK (LS_SIZE - 1)
33 #define MFC_PUT_CMD 0x20
34 #define MFC_PUTS_CMD 0x28
35 #define MFC_PUTR_CMD 0x30
36 #define MFC_PUTF_CMD 0x22
37 #define MFC_PUTB_CMD 0x21
38 #define MFC_PUTFS_CMD 0x2A
39 #define MFC_PUTBS_CMD 0x29
40 #define MFC_PUTRF_CMD 0x32
41 #define MFC_PUTRB_CMD 0x31
42 #define MFC_PUTL_CMD 0x24
43 #define MFC_PUTRL_CMD 0x34
44 #define MFC_PUTLF_CMD 0x26
45 #define MFC_PUTLB_CMD 0x25
46 #define MFC_PUTRLF_CMD 0x36
47 #define MFC_PUTRLB_CMD 0x35
49 #define MFC_GET_CMD 0x40
50 #define MFC_GETS_CMD 0x48
51 #define MFC_GETF_CMD 0x42
52 #define MFC_GETB_CMD 0x41
53 #define MFC_GETFS_CMD 0x4A
54 #define MFC_GETBS_CMD 0x49
55 #define MFC_GETL_CMD 0x44
56 #define MFC_GETLF_CMD 0x46
57 #define MFC_GETLB_CMD 0x45
59 #define MFC_SDCRT_CMD 0x80
60 #define MFC_SDCRTST_CMD 0x81
61 #define MFC_SDCRZ_CMD 0x89
62 #define MFC_SDCRS_CMD 0x8D
63 #define MFC_SDCRF_CMD 0x8F
65 #define MFC_GETLLAR_CMD 0xD0
66 #define MFC_PUTLLC_CMD 0xB4
67 #define MFC_PUTLLUC_CMD 0xB0
68 #define MFC_PUTQLLUC_CMD 0xB8
69 #define MFC_SNDSIG_CMD 0xA0
70 #define MFC_SNDSIGB_CMD 0xA1
71 #define MFC_SNDSIGF_CMD 0xA2
72 #define MFC_BARRIER_CMD 0xC0
73 #define MFC_EIEIO_CMD 0xC8
74 #define MFC_SYNC_CMD 0xCC
76 #define MFC_MIN_DMA_SIZE_SHIFT 4 /* 16 bytes */
77 #define MFC_MAX_DMA_SIZE_SHIFT 14 /* 16384 bytes */
78 #define MFC_MIN_DMA_SIZE (1 << MFC_MIN_DMA_SIZE_SHIFT)
79 #define MFC_MAX_DMA_SIZE (1 << MFC_MAX_DMA_SIZE_SHIFT)
80 #define MFC_MIN_DMA_SIZE_MASK (MFC_MIN_DMA_SIZE - 1)
81 #define MFC_MAX_DMA_SIZE_MASK (MFC_MAX_DMA_SIZE - 1)
82 #define MFC_MIN_DMA_LIST_SIZE 0x0008 /* 8 bytes */
83 #define MFC_MAX_DMA_LIST_SIZE 0x4000 /* 16K bytes */
85 #define MFC_TAGID_TO_TAGMASK(tag_id) (1 << (tag_id & 0x1F))
87 /* Events for Channels 0-2 */
88 #define MFC_DMA_TAG_STATUS_UPDATE_EVENT 0x00000001
89 #define MFC_DMA_TAG_CMD_STALL_NOTIFY_EVENT 0x00000002
90 #define MFC_DMA_QUEUE_AVAILABLE_EVENT 0x00000008
91 #define MFC_SPU_MAILBOX_WRITTEN_EVENT 0x00000010
92 #define MFC_DECREMENTER_EVENT 0x00000020
93 #define MFC_PU_INT_MAILBOX_AVAILABLE_EVENT 0x00000040
94 #define MFC_PU_MAILBOX_AVAILABLE_EVENT 0x00000080
95 #define MFC_SIGNAL_2_EVENT 0x00000100
96 #define MFC_SIGNAL_1_EVENT 0x00000200
97 #define MFC_LLR_LOST_EVENT 0x00000400
98 #define MFC_PRIV_ATTN_EVENT 0x00000800
99 #define MFC_MULTI_SRC_EVENT 0x00001000
101 /* Flags indicating progress during context switch. */
102 #define SPU_CONTEXT_SWITCH_PENDING 0UL
103 #define SPU_CONTEXT_SWITCH_ACTIVE 1UL
110 unsigned long local_store_phys;
112 unsigned long problem_phys;
113 struct spu_problem __iomem *problem;
114 struct spu_priv1 __iomem *priv1;
115 struct spu_priv2 __iomem *priv2;
116 struct list_head list;
117 struct list_head sched_list;
118 struct list_head full_list;
121 unsigned int irqs[3];
127 unsigned int slb_replace;
128 struct mm_struct *mm;
129 struct spu_context *ctx;
130 struct spu_runqueue *rq;
131 unsigned long long timestamp;
135 spinlock_t register_lock;
137 void (* wbox_callback)(struct spu *spu);
138 void (* ibox_callback)(struct spu *spu);
139 void (* stop_callback)(struct spu *spu);
140 void (* mfc_callback)(struct spu *spu);
141 void (* dma_callback)(struct spu *spu, int type);
147 struct device_node *devnode;
149 struct sys_device sysdev;
152 struct spu *spu_alloc(void);
153 struct spu *spu_alloc_node(int node);
154 void spu_free(struct spu *spu);
155 int spu_irq_class_0_bottom(struct spu *spu);
156 int spu_irq_class_1_bottom(struct spu *spu);
157 void spu_irq_setaffinity(struct spu *spu, int cpu);
159 /* system callbacks from the SPU */
160 struct spu_syscall_block {
164 extern long spu_sys_callback(struct spu_syscall_block *s);
166 /* syscalls implemented in spufs */
167 extern struct spufs_calls {
168 asmlinkage long (*create_thread)(const char __user *name,
169 unsigned int flags, mode_t mode);
170 asmlinkage long (*spu_run)(struct file *filp, __u32 __user *unpc,
171 __u32 __user *ustatus);
172 struct module *owner;
175 /* return status from spu_run, same as in libspe */
176 #define SPE_EVENT_DMA_ALIGNMENT 0x0008 /*A DMA alignment error */
177 #define SPE_EVENT_SPE_ERROR 0x0010 /*An illegal instruction error*/
178 #define SPE_EVENT_SPE_DATA_SEGMENT 0x0020 /*A DMA segmentation error */
179 #define SPE_EVENT_SPE_DATA_STORAGE 0x0040 /*A DMA storage error */
180 #define SPE_EVENT_INVALID_DMA 0x0800 /* Invalid MFC DMA */
183 * Flags for sys_spu_create.
185 #define SPU_CREATE_EVENTS_ENABLED 0x0001
186 #define SPU_CREATE_GANG 0x0002
187 #define SPU_CREATE_NOSCHED 0x0004
188 #define SPU_CREATE_ISOLATE 0x0008
190 #define SPU_CREATE_FLAG_ALL 0x000f /* mask of all valid flags */
193 #ifdef CONFIG_SPU_FS_MODULE
194 int register_spu_syscalls(struct spufs_calls *calls);
195 void unregister_spu_syscalls(struct spufs_calls *calls);
197 static inline int register_spu_syscalls(struct spufs_calls *calls)
201 static inline void unregister_spu_syscalls(struct spufs_calls *calls)
206 int spu_add_sysdev_attr(struct sysdev_attribute *attr);
207 void spu_remove_sysdev_attr(struct sysdev_attribute *attr);
209 int spu_add_sysdev_attr_group(struct attribute_group *attrs);
210 void spu_remove_sysdev_attr_group(struct attribute_group *attrs);
216 * oprofile can get notified when a context switch is performed
217 * on an spe. The notifer function that gets called is passed
218 * a pointer to the SPU structure as well as the object-id that
219 * identifies the binary running on that SPU now.
221 * For a context save, the object-id that is passed is zero,
222 * identifying that the kernel will run from that moment on.
224 * For a context restore, the object-id is the value written
225 * to object-id spufs file from user space and the notifer
226 * function can assume that spu->ctx is valid.
228 int spu_switch_event_register(struct notifier_block * n);
229 int spu_switch_event_unregister(struct notifier_block * n);
232 * This defines the Local Store, Problem Area and Privlege Area of an SPU.
235 union mfc_tag_size_class_cmd {
258 #define MS_SYNC_PENDING 1L
259 u64 spc_mssync_RW; /* 0x0000 */
260 u8 pad_0x0008_0x3000[0x3000 - 0x0008];
263 u8 pad_0x3000_0x3004[0x4]; /* 0x3000 */
264 u32 mfc_lsa_W; /* 0x3004 */
265 u64 mfc_ea_W; /* 0x3008 */
266 union mfc_tag_size_class_cmd mfc_union_W; /* 0x3010 */
267 u8 pad_0x3018_0x3104[0xec]; /* 0x3018 */
268 u32 dma_qstatus_R; /* 0x3104 */
269 u8 pad_0x3108_0x3204[0xfc]; /* 0x3108 */
270 u32 dma_querytype_RW; /* 0x3204 */
271 u8 pad_0x3208_0x321c[0x14]; /* 0x3208 */
272 u32 dma_querymask_RW; /* 0x321c */
273 u8 pad_0x3220_0x322c[0xc]; /* 0x3220 */
274 u32 dma_tagstatus_R; /* 0x322c */
275 #define DMA_TAGSTATUS_INTR_ANY 1u
276 #define DMA_TAGSTATUS_INTR_ALL 2u
277 u8 pad_0x3230_0x4000[0x4000 - 0x3230]; /* 0x3230 */
279 /* SPU Control Area */
280 u8 pad_0x4000_0x4004[0x4]; /* 0x4000 */
281 u32 pu_mb_R; /* 0x4004 */
282 u8 pad_0x4008_0x400c[0x4]; /* 0x4008 */
283 u32 spu_mb_W; /* 0x400c */
284 u8 pad_0x4010_0x4014[0x4]; /* 0x4010 */
285 u32 mb_stat_R; /* 0x4014 */
286 u8 pad_0x4018_0x401c[0x4]; /* 0x4018 */
287 u32 spu_runcntl_RW; /* 0x401c */
288 #define SPU_RUNCNTL_STOP 0L
289 #define SPU_RUNCNTL_RUNNABLE 1L
290 #define SPU_RUNCNTL_ISOLATE 2L
291 u8 pad_0x4020_0x4024[0x4]; /* 0x4020 */
292 u32 spu_status_R; /* 0x4024 */
293 #define SPU_STOP_STATUS_SHIFT 16
294 #define SPU_STATUS_STOPPED 0x0
295 #define SPU_STATUS_RUNNING 0x1
296 #define SPU_STATUS_STOPPED_BY_STOP 0x2
297 #define SPU_STATUS_STOPPED_BY_HALT 0x4
298 #define SPU_STATUS_WAITING_FOR_CHANNEL 0x8
299 #define SPU_STATUS_SINGLE_STEP 0x10
300 #define SPU_STATUS_INVALID_INSTR 0x20
301 #define SPU_STATUS_INVALID_CH 0x40
302 #define SPU_STATUS_ISOLATED_STATE 0x80
303 #define SPU_STATUS_ISOLATED_LOAD_STATUS 0x200
304 #define SPU_STATUS_ISOLATED_EXIT_STATUS 0x400
305 u8 pad_0x4028_0x402c[0x4]; /* 0x4028 */
306 u32 spu_spe_R; /* 0x402c */
307 u8 pad_0x4030_0x4034[0x4]; /* 0x4030 */
308 u32 spu_npc_RW; /* 0x4034 */
309 u8 pad_0x4038_0x14000[0x14000 - 0x4038]; /* 0x4038 */
311 /* Signal Notification Area */
312 u8 pad_0x14000_0x1400c[0xc]; /* 0x14000 */
313 u32 signal_notify1; /* 0x1400c */
314 u8 pad_0x14010_0x1c00c[0x7ffc]; /* 0x14010 */
315 u32 signal_notify2; /* 0x1c00c */
316 } __attribute__ ((aligned(0x20000)));
318 /* SPU Privilege 2 State Area */
321 u8 pad_0x0000_0x1100[0x1100 - 0x0000]; /* 0x0000 */
323 /* SLB Management Registers */
324 u8 pad_0x1100_0x1108[0x8]; /* 0x1100 */
325 u64 slb_index_W; /* 0x1108 */
326 #define SLB_INDEX_MASK 0x7L
327 u64 slb_esid_RW; /* 0x1110 */
328 u64 slb_vsid_RW; /* 0x1118 */
329 #define SLB_VSID_SUPERVISOR_STATE (0x1ull << 11)
330 #define SLB_VSID_SUPERVISOR_STATE_MASK (0x1ull << 11)
331 #define SLB_VSID_PROBLEM_STATE (0x1ull << 10)
332 #define SLB_VSID_PROBLEM_STATE_MASK (0x1ull << 10)
333 #define SLB_VSID_EXECUTE_SEGMENT (0x1ull << 9)
334 #define SLB_VSID_NO_EXECUTE_SEGMENT (0x1ull << 9)
335 #define SLB_VSID_EXECUTE_SEGMENT_MASK (0x1ull << 9)
336 #define SLB_VSID_4K_PAGE (0x0 << 8)
337 #define SLB_VSID_LARGE_PAGE (0x1ull << 8)
338 #define SLB_VSID_PAGE_SIZE_MASK (0x1ull << 8)
339 #define SLB_VSID_CLASS_MASK (0x1ull << 7)
340 #define SLB_VSID_VIRTUAL_PAGE_SIZE_MASK (0x1ull << 6)
341 u64 slb_invalidate_entry_W; /* 0x1120 */
342 u64 slb_invalidate_all_W; /* 0x1128 */
343 u8 pad_0x1130_0x2000[0x2000 - 0x1130]; /* 0x1130 */
345 /* Context Save / Restore Area */
346 struct mfc_cq_sr spuq[16]; /* 0x2000 */
347 struct mfc_cq_sr puq[8]; /* 0x2200 */
348 u8 pad_0x2300_0x3000[0x3000 - 0x2300]; /* 0x2300 */
351 u64 mfc_control_RW; /* 0x3000 */
352 #define MFC_CNTL_RESUME_DMA_QUEUE (0ull << 0)
353 #define MFC_CNTL_SUSPEND_DMA_QUEUE (1ull << 0)
354 #define MFC_CNTL_SUSPEND_DMA_QUEUE_MASK (1ull << 0)
355 #define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION (0ull << 8)
356 #define MFC_CNTL_SUSPEND_IN_PROGRESS (1ull << 8)
357 #define MFC_CNTL_SUSPEND_COMPLETE (3ull << 8)
358 #define MFC_CNTL_SUSPEND_DMA_STATUS_MASK (3ull << 8)
359 #define MFC_CNTL_DMA_QUEUES_EMPTY (1ull << 14)
360 #define MFC_CNTL_DMA_QUEUES_EMPTY_MASK (1ull << 14)
361 #define MFC_CNTL_PURGE_DMA_REQUEST (1ull << 15)
362 #define MFC_CNTL_PURGE_DMA_IN_PROGRESS (1ull << 24)
363 #define MFC_CNTL_PURGE_DMA_COMPLETE (3ull << 24)
364 #define MFC_CNTL_PURGE_DMA_STATUS_MASK (3ull << 24)
365 #define MFC_CNTL_RESTART_DMA_COMMAND (1ull << 32)
366 #define MFC_CNTL_DMA_COMMAND_REISSUE_PENDING (1ull << 32)
367 #define MFC_CNTL_DMA_COMMAND_REISSUE_STATUS_MASK (1ull << 32)
368 #define MFC_CNTL_MFC_PRIVILEGE_STATE (2ull << 33)
369 #define MFC_CNTL_MFC_PROBLEM_STATE (3ull << 33)
370 #define MFC_CNTL_MFC_KEY_PROTECTION_STATE_MASK (3ull << 33)
371 #define MFC_CNTL_DECREMENTER_HALTED (1ull << 35)
372 #define MFC_CNTL_DECREMENTER_RUNNING (1ull << 40)
373 #define MFC_CNTL_DECREMENTER_STATUS_MASK (1ull << 40)
374 u8 pad_0x3008_0x4000[0x4000 - 0x3008]; /* 0x3008 */
376 /* Interrupt Mailbox */
377 u64 puint_mb_R; /* 0x4000 */
378 u8 pad_0x4008_0x4040[0x4040 - 0x4008]; /* 0x4008 */
381 u64 spu_privcntl_RW; /* 0x4040 */
382 #define SPU_PRIVCNTL_MODE_NORMAL (0x0ull << 0)
383 #define SPU_PRIVCNTL_MODE_SINGLE_STEP (0x1ull << 0)
384 #define SPU_PRIVCNTL_MODE_MASK (0x1ull << 0)
385 #define SPU_PRIVCNTL_NO_ATTENTION_EVENT (0x0ull << 1)
386 #define SPU_PRIVCNTL_ATTENTION_EVENT (0x1ull << 1)
387 #define SPU_PRIVCNTL_ATTENTION_EVENT_MASK (0x1ull << 1)
388 #define SPU_PRIVCNT_LOAD_REQUEST_NORMAL (0x0ull << 2)
389 #define SPU_PRIVCNT_LOAD_REQUEST_ENABLE_MASK (0x1ull << 2)
390 u8 pad_0x4048_0x4058[0x10]; /* 0x4048 */
391 u64 spu_lslr_RW; /* 0x4058 */
392 u64 spu_chnlcntptr_RW; /* 0x4060 */
393 u64 spu_chnlcnt_RW; /* 0x4068 */
394 u64 spu_chnldata_RW; /* 0x4070 */
395 u64 spu_cfg_RW; /* 0x4078 */
396 u8 pad_0x4080_0x5000[0x5000 - 0x4080]; /* 0x4080 */
398 /* PV2_ImplRegs: Implementation-specific privileged-state 2 regs */
399 u64 spu_pm_trace_tag_status_RW; /* 0x5000 */
400 u64 spu_tag_status_query_RW; /* 0x5008 */
401 #define TAG_STATUS_QUERY_CONDITION_BITS (0x3ull << 32)
402 #define TAG_STATUS_QUERY_MASK_BITS (0xffffffffull)
403 u64 spu_cmd_buf1_RW; /* 0x5010 */
404 #define SPU_COMMAND_BUFFER_1_LSA_BITS (0x7ffffull << 32)
405 #define SPU_COMMAND_BUFFER_1_EAH_BITS (0xffffffffull)
406 u64 spu_cmd_buf2_RW; /* 0x5018 */
407 #define SPU_COMMAND_BUFFER_2_EAL_BITS ((0xffffffffull) << 32)
408 #define SPU_COMMAND_BUFFER_2_TS_BITS (0xffffull << 16)
409 #define SPU_COMMAND_BUFFER_2_TAG_BITS (0x3full)
410 u64 spu_atomic_status_RW; /* 0x5020 */
411 } __attribute__ ((aligned(0x20000)));
413 /* SPU Privilege 1 State Area */
415 /* Control and Configuration Area */
416 u64 mfc_sr1_RW; /* 0x000 */
417 #define MFC_STATE1_LOCAL_STORAGE_DECODE_MASK 0x01ull
418 #define MFC_STATE1_BUS_TLBIE_MASK 0x02ull
419 #define MFC_STATE1_REAL_MODE_OFFSET_ENABLE_MASK 0x04ull
420 #define MFC_STATE1_PROBLEM_STATE_MASK 0x08ull
421 #define MFC_STATE1_RELOCATE_MASK 0x10ull
422 #define MFC_STATE1_MASTER_RUN_CONTROL_MASK 0x20ull
423 u64 mfc_lpid_RW; /* 0x008 */
424 u64 spu_idr_RW; /* 0x010 */
425 u64 mfc_vr_RO; /* 0x018 */
426 #define MFC_VERSION_BITS (0xffff << 16)
427 #define MFC_REVISION_BITS (0xffff)
428 #define MFC_GET_VERSION_BITS(vr) (((vr) & MFC_VERSION_BITS) >> 16)
429 #define MFC_GET_REVISION_BITS(vr) ((vr) & MFC_REVISION_BITS)
430 u64 spu_vr_RO; /* 0x020 */
431 #define SPU_VERSION_BITS (0xffff << 16)
432 #define SPU_REVISION_BITS (0xffff)
433 #define SPU_GET_VERSION_BITS(vr) (vr & SPU_VERSION_BITS) >> 16
434 #define SPU_GET_REVISION_BITS(vr) (vr & SPU_REVISION_BITS)
435 u8 pad_0x28_0x100[0x100 - 0x28]; /* 0x28 */
438 u64 int_mask_RW[3]; /* 0x100 */
439 #define CLASS0_ENABLE_DMA_ALIGNMENT_INTR 0x1L
440 #define CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR 0x2L
441 #define CLASS0_ENABLE_SPU_ERROR_INTR 0x4L
442 #define CLASS0_ENABLE_MFC_FIR_INTR 0x8L
443 #define CLASS1_ENABLE_SEGMENT_FAULT_INTR 0x1L
444 #define CLASS1_ENABLE_STORAGE_FAULT_INTR 0x2L
445 #define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_GET_INTR 0x4L
446 #define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_PUT_INTR 0x8L
447 #define CLASS2_ENABLE_MAILBOX_INTR 0x1L
448 #define CLASS2_ENABLE_SPU_STOP_INTR 0x2L
449 #define CLASS2_ENABLE_SPU_HALT_INTR 0x4L
450 #define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L
451 u8 pad_0x118_0x140[0x28]; /* 0x118 */
452 u64 int_stat_RW[3]; /* 0x140 */
453 u8 pad_0x158_0x180[0x28]; /* 0x158 */
454 u64 int_route_RW; /* 0x180 */
456 /* Interrupt Routing */
457 u8 pad_0x188_0x200[0x200 - 0x188]; /* 0x188 */
459 /* Atomic Unit Control Area */
460 u64 mfc_atomic_flush_RW; /* 0x200 */
461 #define mfc_atomic_flush_enable 0x1L
462 u8 pad_0x208_0x280[0x78]; /* 0x208 */
463 u64 resource_allocation_groupID_RW; /* 0x280 */
464 u64 resource_allocation_enable_RW; /* 0x288 */
465 u8 pad_0x290_0x3c8[0x3c8 - 0x290]; /* 0x290 */
467 /* SPU_Cache_ImplRegs: Implementation-dependent cache registers */
469 u64 smf_sbi_signal_sel; /* 0x3c8 */
470 #define smf_sbi_mask_lsb 56
471 #define smf_sbi_shift (63 - smf_sbi_mask_lsb)
472 #define smf_sbi_mask (0x301LL << smf_sbi_shift)
473 #define smf_sbi_bus0_bits (0x001LL << smf_sbi_shift)
474 #define smf_sbi_bus2_bits (0x100LL << smf_sbi_shift)
475 #define smf_sbi2_bus0_bits (0x201LL << smf_sbi_shift)
476 #define smf_sbi2_bus2_bits (0x300LL << smf_sbi_shift)
477 u64 smf_ato_signal_sel; /* 0x3d0 */
478 #define smf_ato_mask_lsb 35
479 #define smf_ato_shift (63 - smf_ato_mask_lsb)
480 #define smf_ato_mask (0x3LL << smf_ato_shift)
481 #define smf_ato_bus0_bits (0x2LL << smf_ato_shift)
482 #define smf_ato_bus2_bits (0x1LL << smf_ato_shift)
483 u8 pad_0x3d8_0x400[0x400 - 0x3d8]; /* 0x3d8 */
485 /* TLB Management Registers */
486 u64 mfc_sdr_RW; /* 0x400 */
487 u8 pad_0x408_0x500[0xf8]; /* 0x408 */
488 u64 tlb_index_hint_RO; /* 0x500 */
489 u64 tlb_index_W; /* 0x508 */
490 u64 tlb_vpn_RW; /* 0x510 */
491 u64 tlb_rpn_RW; /* 0x518 */
492 u8 pad_0x520_0x540[0x20]; /* 0x520 */
493 u64 tlb_invalidate_entry_W; /* 0x540 */
494 u64 tlb_invalidate_all_W; /* 0x548 */
495 u8 pad_0x550_0x580[0x580 - 0x550]; /* 0x550 */
497 /* SPU_MMU_ImplRegs: Implementation-dependent MMU registers */
498 u64 smm_hid; /* 0x580 */
499 #define PAGE_SIZE_MASK 0xf000000000000000ull
500 #define PAGE_SIZE_16MB_64KB 0x2000000000000000ull
501 u8 pad_0x588_0x600[0x600 - 0x588]; /* 0x588 */
503 /* MFC Status/Control Area */
504 u64 mfc_accr_RW; /* 0x600 */
505 #define MFC_ACCR_EA_ACCESS_GET (1 << 0)
506 #define MFC_ACCR_EA_ACCESS_PUT (1 << 1)
507 #define MFC_ACCR_LS_ACCESS_GET (1 << 3)
508 #define MFC_ACCR_LS_ACCESS_PUT (1 << 4)
509 u8 pad_0x608_0x610[0x8]; /* 0x608 */
510 u64 mfc_dsisr_RW; /* 0x610 */
511 #define MFC_DSISR_PTE_NOT_FOUND (1 << 30)
512 #define MFC_DSISR_ACCESS_DENIED (1 << 27)
513 #define MFC_DSISR_ATOMIC (1 << 26)
514 #define MFC_DSISR_ACCESS_PUT (1 << 25)
515 #define MFC_DSISR_ADDR_MATCH (1 << 22)
516 #define MFC_DSISR_LS (1 << 17)
517 #define MFC_DSISR_L (1 << 16)
518 #define MFC_DSISR_ADDRESS_OVERFLOW (1 << 0)
519 u8 pad_0x618_0x620[0x8]; /* 0x618 */
520 u64 mfc_dar_RW; /* 0x620 */
521 u8 pad_0x628_0x700[0x700 - 0x628]; /* 0x628 */
523 /* Replacement Management Table (RMT) Area */
524 u64 rmt_index_RW; /* 0x700 */
525 u8 pad_0x708_0x710[0x8]; /* 0x708 */
526 u64 rmt_data1_RW; /* 0x710 */
527 u8 pad_0x718_0x800[0x800 - 0x718]; /* 0x718 */
529 /* Control/Configuration Registers */
530 u64 mfc_dsir_R; /* 0x800 */
531 #define MFC_DSIR_Q (1 << 31)
532 #define MFC_DSIR_SPU_QUEUE MFC_DSIR_Q
533 u64 mfc_lsacr_RW; /* 0x808 */
534 #define MFC_LSACR_COMPARE_MASK ((~0ull) << 32)
535 #define MFC_LSACR_COMPARE_ADDR ((~0ull) >> 32)
536 u64 mfc_lscrr_R; /* 0x810 */
537 #define MFC_LSCRR_Q (1 << 31)
538 #define MFC_LSCRR_SPU_QUEUE MFC_LSCRR_Q
539 #define MFC_LSCRR_QI_SHIFT 32
540 #define MFC_LSCRR_QI_MASK ((~0ull) << MFC_LSCRR_QI_SHIFT)
541 u8 pad_0x818_0x820[0x8]; /* 0x818 */
542 u64 mfc_tclass_id_RW; /* 0x820 */
543 #define MFC_TCLASS_ID_ENABLE (1L << 0L)
544 #define MFC_TCLASS_SLOT2_ENABLE (1L << 5L)
545 #define MFC_TCLASS_SLOT1_ENABLE (1L << 6L)
546 #define MFC_TCLASS_SLOT0_ENABLE (1L << 7L)
547 #define MFC_TCLASS_QUOTA_2_SHIFT 8L
548 #define MFC_TCLASS_QUOTA_1_SHIFT 16L
549 #define MFC_TCLASS_QUOTA_0_SHIFT 24L
550 #define MFC_TCLASS_QUOTA_2_MASK (0x1FL << MFC_TCLASS_QUOTA_2_SHIFT)
551 #define MFC_TCLASS_QUOTA_1_MASK (0x1FL << MFC_TCLASS_QUOTA_1_SHIFT)
552 #define MFC_TCLASS_QUOTA_0_MASK (0x1FL << MFC_TCLASS_QUOTA_0_SHIFT)
553 u8 pad_0x828_0x900[0x900 - 0x828]; /* 0x828 */
555 /* Real Mode Support Registers */
556 u64 mfc_rm_boundary; /* 0x900 */
557 u8 pad_0x908_0x938[0x30]; /* 0x908 */
558 u64 smf_dma_signal_sel; /* 0x938 */
559 #define mfc_dma1_mask_lsb 41
560 #define mfc_dma1_shift (63 - mfc_dma1_mask_lsb)
561 #define mfc_dma1_mask (0x3LL << mfc_dma1_shift)
562 #define mfc_dma1_bits (0x1LL << mfc_dma1_shift)
563 #define mfc_dma2_mask_lsb 43
564 #define mfc_dma2_shift (63 - mfc_dma2_mask_lsb)
565 #define mfc_dma2_mask (0x3LL << mfc_dma2_shift)
566 #define mfc_dma2_bits (0x1LL << mfc_dma2_shift)
567 u8 pad_0x940_0xa38[0xf8]; /* 0x940 */
568 u64 smm_signal_sel; /* 0xa38 */
569 #define smm_sig_mask_lsb 12
570 #define smm_sig_shift (63 - smm_sig_mask_lsb)
571 #define smm_sig_mask (0x3LL << smm_sig_shift)
572 #define smm_sig_bus0_bits (0x2LL << smm_sig_shift)
573 #define smm_sig_bus2_bits (0x1LL << smm_sig_shift)
574 u8 pad_0xa40_0xc00[0xc00 - 0xa40]; /* 0xa40 */
576 /* DMA Command Error Area */
577 u64 mfc_cer_R; /* 0xc00 */
578 #define MFC_CER_Q (1 << 31)
579 #define MFC_CER_SPU_QUEUE MFC_CER_Q
580 u8 pad_0xc08_0x1000[0x1000 - 0xc08]; /* 0xc08 */
582 /* PV1_ImplRegs: Implementation-dependent privileged-state 1 regs */
583 /* DMA Command Error Area */
584 u64 spu_ecc_cntl_RW; /* 0x1000 */
585 #define SPU_ECC_CNTL_E (1ull << 0ull)
586 #define SPU_ECC_CNTL_ENABLE SPU_ECC_CNTL_E
587 #define SPU_ECC_CNTL_DISABLE (~SPU_ECC_CNTL_E & 1L)
588 #define SPU_ECC_CNTL_S (1ull << 1ull)
589 #define SPU_ECC_STOP_AFTER_ERROR SPU_ECC_CNTL_S
590 #define SPU_ECC_CONTINUE_AFTER_ERROR (~SPU_ECC_CNTL_S & 2L)
591 #define SPU_ECC_CNTL_B (1ull << 2ull)
592 #define SPU_ECC_BACKGROUND_ENABLE SPU_ECC_CNTL_B
593 #define SPU_ECC_BACKGROUND_DISABLE (~SPU_ECC_CNTL_B & 4L)
594 #define SPU_ECC_CNTL_I_SHIFT 3ull
595 #define SPU_ECC_CNTL_I_MASK (3ull << SPU_ECC_CNTL_I_SHIFT)
596 #define SPU_ECC_WRITE_ALWAYS (~SPU_ECC_CNTL_I & 12L)
597 #define SPU_ECC_WRITE_CORRECTABLE (1ull << SPU_ECC_CNTL_I_SHIFT)
598 #define SPU_ECC_WRITE_UNCORRECTABLE (3ull << SPU_ECC_CNTL_I_SHIFT)
599 #define SPU_ECC_CNTL_D (1ull << 5ull)
600 #define SPU_ECC_DETECTION_ENABLE SPU_ECC_CNTL_D
601 #define SPU_ECC_DETECTION_DISABLE (~SPU_ECC_CNTL_D & 32L)
602 u64 spu_ecc_stat_RW; /* 0x1008 */
603 #define SPU_ECC_CORRECTED_ERROR (1ull << 0ul)
604 #define SPU_ECC_UNCORRECTED_ERROR (1ull << 1ul)
605 #define SPU_ECC_SCRUB_COMPLETE (1ull << 2ul)
606 #define SPU_ECC_SCRUB_IN_PROGRESS (1ull << 3ul)
607 #define SPU_ECC_INSTRUCTION_ERROR (1ull << 4ul)
608 #define SPU_ECC_DATA_ERROR (1ull << 5ul)
609 #define SPU_ECC_DMA_ERROR (1ull << 6ul)
610 #define SPU_ECC_STATUS_CNT_MASK (256ull << 8)
611 u64 spu_ecc_addr_RW; /* 0x1010 */
612 u64 spu_err_mask_RW; /* 0x1018 */
613 #define SPU_ERR_ILLEGAL_INSTR (1ull << 0ul)
614 #define SPU_ERR_ILLEGAL_CHANNEL (1ull << 1ul)
615 u8 pad_0x1020_0x1028[0x1028 - 0x1020]; /* 0x1020 */
617 /* SPU Debug-Trace Bus (DTB) Selection Registers */
618 u64 spu_trig0_sel; /* 0x1028 */
619 u64 spu_trig1_sel; /* 0x1030 */
620 u64 spu_trig2_sel; /* 0x1038 */
621 u64 spu_trig3_sel; /* 0x1040 */
622 u64 spu_trace_sel; /* 0x1048 */
623 #define spu_trace_sel_mask 0x1f1fLL
624 #define spu_trace_sel_bus0_bits 0x1000LL
625 #define spu_trace_sel_bus2_bits 0x0010LL
626 u64 spu_event0_sel; /* 0x1050 */
627 u64 spu_event1_sel; /* 0x1058 */
628 u64 spu_event2_sel; /* 0x1060 */
629 u64 spu_event3_sel; /* 0x1068 */
630 u64 spu_trace_cntl; /* 0x1070 */
631 } __attribute__ ((aligned(0x2000)));
633 #endif /* __KERNEL__ */