6 * linux/include/asm-sh/irq.h
8 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
9 * Copyright (C) 2000 Kazumoto Kojima
10 * Copyright (C) 2003 Paul Mundt
14 #include <asm/machvec.h>
15 #include <asm/ptrace.h> /* for pt_regs */
17 #ifndef CONFIG_CPU_SUBTYPE_SH7780
19 #define INTC_DMAC0_MSK 0
21 #if defined(CONFIG_CPU_SH3)
22 #define INTC_IPRA 0xfffffee2UL
23 #define INTC_IPRB 0xfffffee4UL
24 #elif defined(CONFIG_CPU_SH4)
25 #define INTC_IPRA 0xffd00004UL
26 #define INTC_IPRB 0xffd00008UL
27 #define INTC_IPRC 0xffd0000cUL
28 #define INTC_IPRD 0xffd00010UL
32 #define TIMER_IPR_ADDR INTC_IPRA
33 #define TIMER_IPR_POS 3
34 #define TIMER_PRIORITY 2
37 #define TIMER1_IPR_ADDR INTC_IPRA
38 #define TIMER1_IPR_POS 2
39 #define TIMER1_PRIORITY 4
42 #define RTC_IPR_ADDR INTC_IPRA
44 #define RTC_PRIORITY TIMER_PRIORITY
46 #if defined(CONFIG_CPU_SH3)
51 #define DMA_IPR_ADDR INTC_IPRE
53 #define DMA_PRIORITY 7
54 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
57 #define TIMER2_IPR_ADDR INTC_IPRA
58 #define TIMER2_IPR_POS 1
59 #define TIMER2_PRIORITY 2
63 #define WDT_IPR_ADDR INTC_IPRB
65 #define WDT_PRIORITY 2
67 /* SIM (SIM Card Module) */
68 #define SIM_ERI_IRQ 23
69 #define SIM_RXI_IRQ 24
70 #define SIM_TXI_IRQ 25
71 #define SIM_TEND_IRQ 26
72 #define SIM_IPR_ADDR INTC_IPRB
74 #define SIM_PRIORITY 2
78 #define VIO_IPR_ADDR INTC_IPRE
80 #define VIO_PRIORITY 2
82 /* MFI (Multi Functional Interface) */
84 #define MFI_IPR_ADDR INTC_IPRE
86 #define MFI_PRIORITY 2
88 /* VPU (Video Processing Unit) */
90 #define VPU_IPR_ADDR INTC_IPRE
92 #define VPU_PRIORITY 2
94 /* KEY (Key Scan Interface) */
96 #define KEY_IPR_ADDR INTC_IPRF
98 #define KEY_PRIORITY 2
100 /* CMT (Compare Match Timer) */
102 #define CMT_IPR_ADDR INTC_IPRF
103 #define CMT_IPR_POS 0
104 #define CMT_PRIORITY 2
111 #define DMA1_IPR_ADDR INTC_IPRE
112 #define DMA1_IPR_POS 3
113 #define DMA1_PRIORITY 7
118 #define DMA2_IPR_ADDR INTC_IPRF
119 #define DMA2_IPR_POS 2
120 #define DMA2_PRIORITY 7
124 #define SIOF0_IPR_ADDR INTC_IPRH
125 #define SIOF0_IPR_POS 3
126 #define SIOF0_PRIORITY 3
128 /* FLCTL (Flash Memory Controller) */
130 #define FLTEND_IRQ 93
131 #define FLTRQ0_IRQ 94
132 #define FLTRQ1_IRQ 95
133 #define FLCTL_IPR_ADDR INTC_IPRH
134 #define FLCTL_IPR_POS 1
135 #define FLCTL_PRIORITY 3
137 /* IIC (IIC Bus Interface) */
138 #define IIC_ALI_IRQ 96
139 #define IIC_TACKI_IRQ 97
140 #define IIC_WAITI_IRQ 98
141 #define IIC_DTEI_IRQ 99
142 #define IIC_IPR_ADDR INTC_IPRH
143 #define IIC_IPR_POS 0
144 #define IIC_PRIORITY 3
148 #define SIO0_IPR_ADDR INTC_IPRI
149 #define SIO0_IPR_POS 3
150 #define SIO0_PRIORITY 3
152 /* SIU (Sound Interface Unit) */
154 #define SIU_IPR_ADDR INTC_IPRJ
155 #define SIU_IPR_POS 1
156 #define SIU_PRIORITY 3
159 #elif defined(CONFIG_CPU_SH4)
164 #define DMTE4_IRQ 44 /* 7751R only */
165 #define DMTE5_IRQ 45 /* 7751R only */
166 #define DMTE6_IRQ 46 /* 7751R only */
167 #define DMTE7_IRQ 47 /* 7751R only */
169 #define DMA_IPR_ADDR INTC_IPRC
170 #define DMA_IPR_POS 2
171 #define DMA_PRIORITY 7
174 #if defined (CONFIG_CPU_SUBTYPE_SH7707) || defined (CONFIG_CPU_SUBTYPE_SH7708) || \
175 defined (CONFIG_CPU_SUBTYPE_SH7709) || defined (CONFIG_CPU_SUBTYPE_SH7750) || \
176 defined (CONFIG_CPU_SUBTYPE_SH7751) || defined (CONFIG_CPU_SUBTYPE_SH7706)
177 #define SCI_ERI_IRQ 23
178 #define SCI_RXI_IRQ 24
179 #define SCI_TXI_IRQ 25
180 #define SCI_IPR_ADDR INTC_IPRB
181 #define SCI_IPR_POS 1
182 #define SCI_PRIORITY 3
185 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
187 #define SCIF0_IPR_ADDR INTC_IPRG
188 #define SCIF0_IPR_POS 3
189 #define SCIF0_PRIORITY 3
190 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
191 defined(CONFIG_CPU_SUBTYPE_SH7706) || \
192 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
193 defined(CONFIG_CPU_SUBTYPE_SH7709)
194 #define SCIF_ERI_IRQ 56
195 #define SCIF_RXI_IRQ 57
196 #define SCIF_BRI_IRQ 58
197 #define SCIF_TXI_IRQ 59
198 #define SCIF_IPR_ADDR INTC_IPRE
199 #define SCIF_IPR_POS 1
200 #define SCIF_PRIORITY 3
202 #define IRDA_ERI_IRQ 52
203 #define IRDA_RXI_IRQ 53
204 #define IRDA_BRI_IRQ 54
205 #define IRDA_TXI_IRQ 55
206 #define IRDA_IPR_ADDR INTC_IPRE
207 #define IRDA_IPR_POS 2
208 #define IRDA_PRIORITY 3
209 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
210 defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
211 #define SCIF_ERI_IRQ 40
212 #define SCIF_RXI_IRQ 41
213 #define SCIF_BRI_IRQ 42
214 #define SCIF_TXI_IRQ 43
215 #define SCIF_IPR_ADDR INTC_IPRC
216 #define SCIF_IPR_POS 1
217 #define SCIF_PRIORITY 3
218 #if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
219 #define SCIF1_ERI_IRQ 23
220 #define SCIF1_RXI_IRQ 24
221 #define SCIF1_BRI_IRQ 25
222 #define SCIF1_TXI_IRQ 26
223 #define SCIF1_IPR_ADDR INTC_IPRB
224 #define SCIF1_IPR_POS 1
225 #define SCIF1_PRIORITY 3
226 #endif /* ST40STB1 */
228 #endif /* 775x / SH4-202 / ST40STB1 */
231 /* NR_IRQS is made from three components:
232 * 1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules
233 * 2. PINT_NR_IRQS - number of PINT interrupts
234 * 3. OFFCHIP_NR_IRQS - numbe of IRQs from off-chip peripherial modules
237 /* 1. ONCHIP_NR_IRQS */
238 #if defined(CONFIG_CPU_SUBTYPE_SH7604)
239 # define ONCHIP_NR_IRQS 24 // Actually 21
240 #elif defined(CONFIG_CPU_SUBTYPE_SH7707)
241 # define ONCHIP_NR_IRQS 64
242 # define PINT_NR_IRQS 16
243 #elif defined(CONFIG_CPU_SUBTYPE_SH7708)
244 # define ONCHIP_NR_IRQS 32
245 #elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \
246 defined(CONFIG_CPU_SUBTYPE_SH7706) || \
247 defined(CONFIG_CPU_SUBTYPE_SH7705)
248 # define ONCHIP_NR_IRQS 64 // Actually 61
249 # define PINT_NR_IRQS 16
250 #elif defined(CONFIG_CPU_SUBTYPE_SH7710)
251 # define ONCHIP_NR_IRQS 104
252 #elif defined(CONFIG_CPU_SUBTYPE_SH7750)
253 # define ONCHIP_NR_IRQS 48 // Actually 44
254 #elif defined(CONFIG_CPU_SUBTYPE_SH7751)
255 # define ONCHIP_NR_IRQS 72
256 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
257 # define ONCHIP_NR_IRQS 112 /* XXX */
258 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
259 # define ONCHIP_NR_IRQS 72
260 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
261 # define ONCHIP_NR_IRQS 144
262 #elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \
263 defined(CONFIG_CPU_SUBTYPE_SH73180) || \
264 defined(CONFIG_CPU_SUBTYPE_SH7343)
265 # define ONCHIP_NR_IRQS 109
266 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
267 # define ONCHIP_NR_IRQS 111
268 #elif defined(CONFIG_SH_UNKNOWN) /* Most be last */
269 # define ONCHIP_NR_IRQS 144
272 /* 2. PINT_NR_IRQS */
273 #ifdef CONFIG_SH_UNKNOWN
274 # define PINT_NR_IRQS 16
276 # ifndef PINT_NR_IRQS
277 # define PINT_NR_IRQS 0
282 # define PINT_IRQ_BASE ONCHIP_NR_IRQS
285 /* 3. OFFCHIP_NR_IRQS */
286 #if defined(CONFIG_HD64461)
287 # define OFFCHIP_NR_IRQS 18
288 #elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */
289 # define OFFCHIP_NR_IRQS 48
290 #elif defined(CONFIG_HD64465)
291 # define OFFCHIP_NR_IRQS 16
292 #elif defined (CONFIG_SH_EC3104)
293 # define OFFCHIP_NR_IRQS 16
294 #elif defined (CONFIG_SH_DREAMCAST)
295 # define OFFCHIP_NR_IRQS 96
296 #elif defined (CONFIG_SH_TITAN)
297 # define OFFCHIP_NR_IRQS 4
298 #elif defined(CONFIG_SH_R7780RP)
299 # define OFFCHIP_NR_IRQS 16
300 #elif defined(CONFIG_SH_7343_SOLUTION_ENGINE)
301 # define OFFCHIP_NR_IRQS 12
302 #elif defined(CONFIG_SH_UNKNOWN)
303 # define OFFCHIP_NR_IRQS 16 /* Must also be last */
305 # define OFFCHIP_NR_IRQS 0
308 #if OFFCHIP_NR_IRQS > 0
309 # define OFFCHIP_IRQ_BASE (ONCHIP_NR_IRQS + PINT_NR_IRQS)
313 #define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
315 extern void disable_irq(unsigned int);
316 extern void disable_irq_nosync(unsigned int);
317 extern void enable_irq(unsigned int);
320 * Simple Mask Register Support
322 extern void make_maskreg_irq(unsigned int irq);
323 extern unsigned short *irq_mask_register;
328 void init_IRQ_pint(void);
331 * Function for "on chip support modules".
333 extern void make_ipr_irq(unsigned int irq, unsigned int addr,
334 int pos, int priority);
335 extern void make_imask_irq(unsigned int irq);
337 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
340 #define INTC_IPRA 0xA414FEE2UL
341 #define INTC_IPRB 0xA414FEE4UL
342 #define INTC_IPRC 0xA4140016UL
343 #define INTC_IPRD 0xA4140018UL
344 #define INTC_IPRE 0xA414001AUL
345 #define INTC_IPRF 0xA4080000UL
346 #define INTC_IPRG 0xA4080002UL
347 #define INTC_IPRH 0xA4080004UL
348 #define INTC_IPRI 0xA4080006UL
349 #define INTC_IPRJ 0xA4080008UL
351 #define INTC_IMR0 0xA4080040UL
352 #define INTC_IMR1 0xA4080042UL
353 #define INTC_IMR2 0xA4080044UL
354 #define INTC_IMR3 0xA4080046UL
355 #define INTC_IMR4 0xA4080048UL
356 #define INTC_IMR5 0xA408004AUL
357 #define INTC_IMR6 0xA408004CUL
358 #define INTC_IMR7 0xA408004EUL
359 #define INTC_IMR8 0xA4080050UL
360 #define INTC_IMR9 0xA4080052UL
361 #define INTC_IMR10 0xA4080054UL
363 #define INTC_IMCR0 0xA4080060UL
364 #define INTC_IMCR1 0xA4080062UL
365 #define INTC_IMCR2 0xA4080064UL
366 #define INTC_IMCR3 0xA4080066UL
367 #define INTC_IMCR4 0xA4080068UL
368 #define INTC_IMCR5 0xA408006AUL
369 #define INTC_IMCR6 0xA408006CUL
370 #define INTC_IMCR7 0xA408006EUL
371 #define INTC_IMCR8 0xA4080070UL
372 #define INTC_IMCR9 0xA4080072UL
373 #define INTC_IMCR10 0xA4080074UL
375 #define INTC_ICR0 0xA414FEE0UL
376 #define INTC_ICR1 0xA4140010UL
378 #define INTC_IRR0 0xA4140004UL
380 #define PORT_PACR 0xA4050100UL
381 #define PORT_PBCR 0xA4050102UL
382 #define PORT_PCCR 0xA4050104UL
383 #define PORT_PDCR 0xA4050106UL
384 #define PORT_PECR 0xA4050108UL
385 #define PORT_PFCR 0xA405010AUL
386 #define PORT_PGCR 0xA405010CUL
387 #define PORT_PHCR 0xA405010EUL
388 #define PORT_PJCR 0xA4050110UL
389 #define PORT_PKCR 0xA4050112UL
390 #define PORT_PLCR 0xA4050114UL
391 #define PORT_SCPCR 0xA4050116UL
392 #define PORT_PMCR 0xA4050118UL
393 #define PORT_PNCR 0xA405011AUL
394 #define PORT_PQCR 0xA405011CUL
396 #define PORT_PSELA 0xA4050140UL
397 #define PORT_PSELB 0xA4050142UL
398 #define PORT_PSELC 0xA4050144UL
400 #define PORT_HIZCRA 0xA4050146UL
401 #define PORT_HIZCRB 0xA4050148UL
402 #define PORT_DRVCR 0xA4050150UL
404 #define PORT_PADR 0xA4050120UL
405 #define PORT_PBDR 0xA4050122UL
406 #define PORT_PCDR 0xA4050124UL
407 #define PORT_PDDR 0xA4050126UL
408 #define PORT_PEDR 0xA4050128UL
409 #define PORT_PFDR 0xA405012AUL
410 #define PORT_PGDR 0xA405012CUL
411 #define PORT_PHDR 0xA405012EUL
412 #define PORT_PJDR 0xA4050130UL
413 #define PORT_PKDR 0xA4050132UL
414 #define PORT_PLDR 0xA4050134UL
415 #define PORT_SCPDR 0xA4050136UL
416 #define PORT_PMDR 0xA4050138UL
417 #define PORT_PNDR 0xA405013AUL
418 #define PORT_PQDR 0xA405013CUL
427 #define IRQ0_IPR_ADDR INTC_IPRC
428 #define IRQ1_IPR_ADDR INTC_IPRC
429 #define IRQ2_IPR_ADDR INTC_IPRC
430 #define IRQ3_IPR_ADDR INTC_IPRC
431 #define IRQ4_IPR_ADDR INTC_IPRD
432 #define IRQ5_IPR_ADDR INTC_IPRD
434 #define IRQ0_IPR_POS 0
435 #define IRQ1_IPR_POS 1
436 #define IRQ2_IPR_POS 2
437 #define IRQ3_IPR_POS 3
438 #define IRQ4_IPR_POS 0
439 #define IRQ5_IPR_POS 1
441 #define IRQ0_PRIORITY 1
442 #define IRQ1_PRIORITY 1
443 #define IRQ2_PRIORITY 1
444 #define IRQ3_PRIORITY 1
445 #define IRQ4_PRIORITY 1
446 #define IRQ5_PRIORITY 1
448 extern int ipr_irq_demux(int irq);
449 #define __irq_demux(irq) ipr_irq_demux(irq)
451 #elif defined(CONFIG_CPU_SUBTYPE_SH7604)
452 #define INTC_IPRA 0xfffffee2UL
453 #define INTC_IPRB 0xfffffe60UL
455 #define INTC_VCRA 0xfffffe62UL
456 #define INTC_VCRB 0xfffffe64UL
457 #define INTC_VCRC 0xfffffe66UL
458 #define INTC_VCRD 0xfffffe68UL
460 #define INTC_VCRWDT 0xfffffee4UL
461 #define INTC_VCRDIV 0xffffff0cUL
462 #define INTC_VCRDMA0 0xffffffa0UL
463 #define INTC_VCRDMA1 0xffffffa8UL
465 #define INTC_ICR 0xfffffee0UL
466 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
467 defined(CONFIG_CPU_SUBTYPE_SH7706) || \
468 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
469 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
470 defined(CONFIG_CPU_SUBTYPE_SH7710)
471 #define INTC_IRR0 0xa4000004UL
472 #define INTC_IRR1 0xa4000006UL
473 #define INTC_IRR2 0xa4000008UL
475 #define INTC_ICR0 0xfffffee0UL
476 #define INTC_ICR1 0xa4000010UL
477 #define INTC_ICR2 0xa4000012UL
478 #define INTC_INTER 0xa4000014UL
480 #define INTC_IPRC 0xa4000016UL
481 #define INTC_IPRD 0xa4000018UL
482 #define INTC_IPRE 0xa400001aUL
483 #if defined(CONFIG_CPU_SUBTYPE_SH7707)
484 #define INTC_IPRF 0xa400001cUL
485 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
486 #define INTC_IPRF 0xa4080000UL
487 #define INTC_IPRG 0xa4080002UL
488 #define INTC_IPRH 0xa4080004UL
489 #elif defined(CONFIG_CPU_SUBTYPE_SH7710)
490 /* Interrupt Controller Registers */
493 #define INTC_IPRA 0xA414FEE2UL
494 #define INTC_IPRB 0xA414FEE4UL
495 #define INTC_IPRF 0xA4080000UL
496 #define INTC_IPRG 0xA4080002UL
497 #define INTC_IPRH 0xA4080004UL
498 #define INTC_IPRI 0xA4080006UL
502 #define INTC_ICR0 0xA414FEE0UL
503 #define INTC_ICR1 0xA4140010UL
505 #define INTC_IRR0 0xa4000004UL
506 #define INTC_IRR1 0xa4000006UL
507 #define INTC_IRR2 0xa4000008UL
508 #define INTC_IRR3 0xa400000AUL
509 #define INTC_IRR4 0xa400000CUL
510 #define INTC_IRR5 0xa4080020UL
511 #define INTC_IRR7 0xa4080024UL
512 #define INTC_IRR8 0xa4080026UL
514 /* Interrupt numbers */
515 #define TIMER2_IRQ 18
516 #define TIMER2_IPR_ADDR INTC_IPRA
517 #define TIMER2_IPR_POS 1
518 #define TIMER2_PRIORITY 2
522 #define WDT_IPR_ADDR INTC_IPRB
523 #define WDT_IPR_POS 3
524 #define WDT_PRIORITY 2
526 #define SCIF0_ERI_IRQ 52
527 #define SCIF0_RXI_IRQ 53
528 #define SCIF0_BRI_IRQ 54
529 #define SCIF0_TXI_IRQ 55
530 #define SCIF0_IPR_ADDR INTC_IPRE
531 #define SCIF0_IPR_POS 2
532 #define SCIF0_PRIORITY 3
536 #define DMA2_IPR_ADDR INTC_IPRF
537 #define DMA2_IPR_POS 2
538 #define DMA2_PRIORITY 7
541 #define IPSEC_IPR_ADDR INTC_IPRF
542 #define IPSEC_IPR_POS 3
543 #define IPSEC_PRIORITY 3
546 #define EDMAC0_IRQ 80
547 #define EDMAC0_IPR_ADDR INTC_IPRG
548 #define EDMAC0_IPR_POS 3
549 #define EDMAC0_PRIORITY 3
551 #define EDMAC1_IRQ 81
552 #define EDMAC1_IPR_ADDR INTC_IPRG
553 #define EDMAC1_IPR_POS 2
554 #define EDMAC1_PRIORITY 3
556 #define EDMAC2_IRQ 82
557 #define EDMAC2_IPR_ADDR INTC_IPRG
558 #define EDMAC2_IPR_POS 1
559 #define EDMAC2_PRIORITY 3
562 #define SIOF0_ERI_IRQ 96
563 #define SIOF0_TXI_IRQ 97
564 #define SIOF0_RXI_IRQ 98
565 #define SIOF0_CCI_IRQ 99
566 #define SIOF0_IPR_ADDR INTC_IPRH
567 #define SIOF0_IPR_POS 0
568 #define SIOF0_PRIORITY 7
570 #define SIOF1_ERI_IRQ 100
571 #define SIOF1_TXI_IRQ 101
572 #define SIOF1_RXI_IRQ 102
573 #define SIOF1_CCI_IRQ 103
574 #define SIOF1_IPR_ADDR INTC_IPRI
575 #define SIOF1_IPR_POS 1
576 #define SIOF1_PRIORITY 7
577 #endif /* CONFIG_CPU_SUBTYPE_SH7710 */
579 #if defined(CONFIG_CPU_SUBTYPE_SH7710)
580 #define PORT_PACR 0xa4050100UL
581 #define PORT_PBCR 0xa4050102UL
582 #define PORT_PCCR 0xa4050104UL
583 #define PORT_PETCR 0xa4050106UL
584 #define PORT_PADR 0xa4050120UL
585 #define PORT_PBDR 0xa4050122UL
586 #define PORT_PCDR 0xa4050124UL
588 #define PORT_PACR 0xa4000100UL
589 #define PORT_PBCR 0xa4000102UL
590 #define PORT_PCCR 0xa4000104UL
591 #define PORT_PFCR 0xa400010aUL
592 #define PORT_PADR 0xa4000120UL
593 #define PORT_PBDR 0xa4000122UL
594 #define PORT_PCDR 0xa4000124UL
595 #define PORT_PFDR 0xa400012aUL
605 #define IRQ0_IPR_ADDR INTC_IPRC
606 #define IRQ1_IPR_ADDR INTC_IPRC
607 #define IRQ2_IPR_ADDR INTC_IPRC
608 #define IRQ3_IPR_ADDR INTC_IPRC
609 #define IRQ4_IPR_ADDR INTC_IPRD
610 #define IRQ5_IPR_ADDR INTC_IPRD
612 #define IRQ0_IPR_POS 0
613 #define IRQ1_IPR_POS 1
614 #define IRQ2_IPR_POS 2
615 #define IRQ3_IPR_POS 3
616 #define IRQ4_IPR_POS 0
617 #define IRQ5_IPR_POS 1
619 #define IRQ0_PRIORITY 1
620 #define IRQ1_PRIORITY 1
621 #define IRQ2_PRIORITY 1
622 #define IRQ3_PRIORITY 1
623 #define IRQ4_PRIORITY 1
624 #define IRQ5_PRIORITY 1
629 #define PINT0_IPR_ADDR INTC_IPRD
630 #define PINT8_IPR_ADDR INTC_IPRD
632 #define PINT0_IPR_POS 3
633 #define PINT8_IPR_POS 2
634 #define PINT0_PRIORITY 2
635 #define PINT8_PRIORITY 2
637 extern int ipr_irq_demux(int irq);
638 #define __irq_demux(irq) ipr_irq_demux(irq)
639 #endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */
641 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
642 defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
643 #define INTC_ICR 0xffd00000
644 #define INTC_ICR_NMIL (1<<15)
645 #define INTC_ICR_MAI (1<<14)
646 #define INTC_ICR_NMIB (1<<9)
647 #define INTC_ICR_NMIE (1<<8)
648 #define INTC_ICR_IRLM (1<<7)
651 #ifdef CONFIG_CPU_SUBTYPE_SH7780
652 #include <asm/irq-sh7780.h>
655 /* SH with INTC2-style interrupts */
656 #ifdef CONFIG_CPU_HAS_INTC2_IRQ
657 #if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
658 #define INTC2_BASE 0xfe080000
659 #define INTC2_FIRST_IRQ 64
660 #define INTC2_INTREQ_OFFSET 0x20
661 #define INTC2_INTMSK_OFFSET 0x40
662 #define INTC2_INTMSKCLR_OFFSET 0x60
663 #define NR_INTC2_IRQS 25
664 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
665 #define INTC2_BASE 0xfe080000
666 #define INTC2_FIRST_IRQ 48 /* INTEVT 0x800 */
667 #define INTC2_INTREQ_OFFSET 0x20
668 #define INTC2_INTMSK_OFFSET 0x40
669 #define INTC2_INTMSKCLR_OFFSET 0x60
670 #define NR_INTC2_IRQS 64
671 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
672 #define INTC2_BASE 0xffd40000
673 #define INTC2_FIRST_IRQ 21
674 #define INTC2_INTMSK_OFFSET (0x38)
675 #define INTC2_INTMSKCLR_OFFSET (0x3c)
676 #define NR_INTC2_IRQS 60
679 #define INTC2_INTPRI_OFFSET 0x00
683 unsigned char ipr_offset, ipr_shift;
684 unsigned char msk_offset, msk_shift;
685 unsigned char priority;
688 void make_intc2_irq(struct intc2_data *, unsigned int nr_irqs);
689 void init_IRQ_intc2(void);
692 extern int shmse_irq_demux(int irq);
694 static inline int generic_irq_demux(int irq)
700 #define __irq_demux(irq) (irq)
702 #define irq_canonicalize(irq) (irq)
703 #define irq_demux(irq) __irq_demux(sh_mv.mv_irq_demux(irq))
705 #ifdef CONFIG_4KSTACKS
706 extern void irq_ctx_init(int cpu);
707 extern void irq_ctx_exit(int cpu);
708 # define __ARCH_HAS_DO_SOFTIRQ
710 # define irq_ctx_init(cpu) do { } while (0)
711 # define irq_ctx_exit(cpu) do { } while (0)
714 #if defined(CONFIG_CPU_SUBTYPE_SH73180)
715 #include <asm/irq-sh73180.h>
718 #if defined(CONFIG_CPU_SUBTYPE_SH7343)
719 #include <asm/irq-sh7343.h>
722 #endif /* __ASM_SH_IRQ_H */