1 #ifndef _SPARC64_HYPERVISOR_H
2 #define _SPARC64_HYPERVISOR_H
4 /* Sun4v hypervisor interfaces and defines.
6 * Hypervisor calls are made via traps to software traps number 0x80
7 * and above. Registers %o0 to %o5 serve as argument, status, and
8 * return value registers.
10 * There are two kinds of these traps. First there are the normal
11 * "fast traps" which use software trap 0x80 and encode the function
12 * to invoke by number in register %o5. Argument and return value
13 * handling is as follows:
15 * -----------------------------------------------
16 * | %o5 | function number | undefined |
17 * | %o0 | argument 0 | return status |
18 * | %o1 | argument 1 | return value 1 |
19 * | %o2 | argument 2 | return value 2 |
20 * | %o3 | argument 3 | return value 3 |
21 * | %o4 | argument 4 | return value 4 |
22 * -----------------------------------------------
24 * The second type are "hyper-fast traps" which encode the function
25 * number in the software trap number itself. So these use trap
26 * numbers > 0x80. The register usage for hyper-fast traps is as
29 * -----------------------------------------------
30 * | %o0 | argument 0 | return status |
31 * | %o1 | argument 1 | return value 1 |
32 * | %o2 | argument 2 | return value 2 |
33 * | %o3 | argument 3 | return value 3 |
34 * | %o4 | argument 4 | return value 4 |
35 * -----------------------------------------------
37 * Registers providing explicit arguments to the hypervisor calls
38 * are volatile across the call. Upon return their values are
39 * undefined unless explicitly specified as containing a particular
40 * return value by the specific call. The return status is always
41 * returned in register %o0, zero indicates a successful execution of
42 * the hypervisor call and other values indicate an error status as
43 * defined below. So, for example, if a hyper-fast trap takes
44 * arguments 0, 1, and 2, then %o0, %o1, and %o2 are volatile across
45 * the call and %o3, %o4, and %o5 would be preserved.
47 * If the hypervisor trap is invalid, or the fast trap function number
48 * is invalid, HV_EBADTRAP will be returned in %o0. Also, all 64-bits
49 * of the argument and return values are significant.
53 #define HV_FAST_TRAP 0x80
54 #define HV_MMU_MAP_ADDR_TRAP 0x83
55 #define HV_MMU_UNMAP_ADDR_TRAP 0x84
56 #define HV_TTRACE_ADDENTRY_TRAP 0x85
57 #define HV_CORE_TRAP 0xff
60 #define HV_EOK 0 /* Successful return */
61 #define HV_ENOCPU 1 /* Invalid CPU id */
62 #define HV_ENORADDR 2 /* Invalid real address */
63 #define HV_ENOINTR 3 /* Invalid interrupt id */
64 #define HV_EBADPGSZ 4 /* Invalid pagesize encoding */
65 #define HV_EBADTSB 5 /* Invalid TSB description */
66 #define HV_EINVAL 6 /* Invalid argument */
67 #define HV_EBADTRAP 7 /* Invalid function number */
68 #define HV_EBADALIGN 8 /* Invalid address alignment */
69 #define HV_EWOULDBLOCK 9 /* Cannot complete w/o blocking */
70 #define HV_ENOACCESS 10 /* No access to resource */
71 #define HV_EIO 11 /* I/O error */
72 #define HV_ECPUERROR 12 /* CPU in error state */
73 #define HV_ENOTSUPPORTED 13 /* Function not supported */
74 #define HV_ENOMAP 14 /* No mapping found */
75 #define HV_ETOOMANY 15 /* Too many items specified */
79 * FUNCTION: HV_FAST_MACH_EXIT
81 * ERRORS: This service does not return.
83 * Stop all CPUs in the virtual domain and place them into the stopped
84 * state. The 64-bit exit code may be passed to a service entity as
85 * the domain's exit status. On systems without a service entity, the
86 * domain will undergo a reset, and the boot firmware will be
89 * This function will never return to the guest that invokes it.
91 * Note: By convention an exit code of zero denotes a successful exit by
92 * the guest code. A non-zero exit code denotes a guest specific
96 #define HV_FAST_MACH_EXIT 0x00
98 /* Domain services. */
102 * FUNCTION: HV_FAST_MACH_DESC
107 * ERRORS: HV_EBADALIGN Buffer is badly aligned
108 * HV_ENORADDR Buffer is to an illegal real address.
109 * HV_EINVAL Buffer length is too small for complete
110 * machine description.
112 * Copy the most current machine description into the buffer indicated
113 * by the real address in ARG0. The buffer provided must be 16 byte
114 * aligned. Upon success or HV_EINVAL, this service returns the
115 * actual size of the machine description in the RET1 return value.
117 * Note: A method of determining the appropriate buffer size for the
118 * machine description is to first call this service with a buffer
121 #define HV_FAST_MACH_DESC 0x01
125 * FUNCTION: HV_FAST_MACH_SIR
126 * ERRORS: This service does not return.
128 * Perform a software initiated reset of the virtual machine domain.
129 * All CPUs are captured as soon as possible, all hardware devices are
130 * returned to the entry default state, and the domain is restarted at
131 * the SIR (trap type 0x04) real trap table (RTBA) entry point on one
132 * of the CPUs. The single CPU restarted is selected as determined by
133 * platform specific policy. Memory is preserved across this
136 #define HV_FAST_MACH_SIR 0x02
138 /* mach_set_soft_state()
140 * FUNCTION: HV_FAST_MACH_SET_SOFT_STATE
141 * ARG0: software state
142 * ARG1: software state description pointer
144 * ERRORS: EINVAL software state not valid or software state
145 * description is not NULL terminated
146 * ENORADDR software state description pointer is not a
148 * EBADALIGNED software state description is not correctly
151 * This allows the guest to report it's soft state to the hypervisor. There
152 * are two primary components to this state. The first part states whether
153 * the guest software is running or not. The second containts optional
154 * details specific to the software.
156 * The software state argument is defined below in HV_SOFT_STATE_*, and
157 * indicates whether the guest is operating normally or in a transitional
160 * The software state description argument is a real address of a data buffer
161 * of size 32-bytes aligned on a 32-byte boundary. It is treated as a NULL
162 * terminated 7-bit ASCII string of up to 31 characters not including the
165 #define HV_FAST_MACH_SET_SOFT_STATE 0x70
166 #define HV_SOFT_STATE_NORMAL 0x01
167 #define HV_SOFT_STATE_TRANSITION 0x02
170 extern unsigned long sun4v_mach_set_soft_state(unsigned long soft_state,
171 unsigned long msg_string_ra);
174 /* mach_get_soft_state()
176 * FUNCTION: HV_FAST_MACH_GET_SOFT_STATE
177 * ARG0: software state description pointer
179 * RET1: software state
180 * ERRORS: ENORADDR software state description pointer is not a
182 * EBADALIGNED software state description is not correctly
185 * Retrieve the current value of the guest's software state. The rules
186 * for the software state pointer are the same as for mach_set_soft_state()
189 #define HV_FAST_MACH_GET_SOFT_STATE 0x71
193 * CPUs represent devices that can execute software threads. A single
194 * chip that contains multiple cores or strands is represented as
195 * multiple CPUs with unique CPU identifiers. CPUs are exported to
196 * OBP via the machine description (and to the OS via the OBP device
197 * tree). CPUs are always in one of three states: stopped, running,
200 * A CPU ID is a pre-assigned 16-bit value that uniquely identifies a
201 * CPU within a logical domain. Operations that are to be performed
202 * on multiple CPUs specify them via a CPU list. A CPU list is an
203 * array in real memory, of which each 16-bit word is a CPU ID. CPU
204 * lists are passed through the API as two arguments. The first is
205 * the number of entries (16-bit words) in the CPU list, and the
206 * second is the (real address) pointer to the CPU ID list.
211 * FUNCTION: HV_FAST_CPU_START
217 * ERRORS: ENOCPU Invalid CPU ID
218 * EINVAL Target CPU ID is not in the stopped state
219 * ENORADDR Invalid PC or RTBA real address
220 * EBADALIGN Unaligned PC or unaligned RTBA
221 * EWOULDBLOCK Starting resources are not available
223 * Start CPU with given CPU ID with PC in %pc and with a real trap
224 * base address value of RTBA. The indicated CPU must be in the
225 * stopped state. The supplied RTBA must be aligned on a 256 byte
226 * boundary. On successful completion, the specified CPU will be in
227 * the running state and will be supplied with "target ARG0" in %o0
230 #define HV_FAST_CPU_START 0x10
234 * FUNCTION: HV_FAST_CPU_STOP
237 * ERRORS: ENOCPU Invalid CPU ID
238 * EINVAL Target CPU ID is the current cpu
239 * EINVAL Target CPU ID is not in the running state
240 * EWOULDBLOCK Stopping resources are not available
241 * ENOTSUPPORTED Not supported on this platform
243 * The specified CPU is stopped. The indicated CPU must be in the
244 * running state. On completion, it will be in the stopped state. It
245 * is not legal to stop the current CPU.
247 * Note: As this service cannot be used to stop the current cpu, this service
248 * may not be used to stop the last running CPU in a domain. To stop
249 * and exit a running domain, a guest must use the mach_exit() service.
251 #define HV_FAST_CPU_STOP 0x11
255 * FUNCTION: HV_FAST_CPU_YIELD
257 * ERRORS: No possible error.
259 * Suspend execution on the current CPU. Execution will resume when
260 * an interrupt (device, %stick_compare, or cross-call) is targeted to
261 * the CPU. On some CPUs, this API may be used by the hypervisor to
262 * save power by disabling hardware strands.
264 #define HV_FAST_CPU_YIELD 0x12
267 extern unsigned long sun4v_cpu_yield(void);
272 * FUNCTION: HV_FAST_CPU_QCONF
274 * ARG1: base real address
275 * ARG2: number of entries
277 * ERRORS: ENORADDR Invalid base real address
278 * EINVAL Invalid queue or number of entries is less
279 * than 2 or too large.
280 * EBADALIGN Base real address is not correctly aligned
283 * Configure the given queue to be placed at the given base real
284 * address, with the given number of entries. The number of entries
285 * must be a power of 2. The base real address must be aligned
286 * exactly to match the queue size. Each queue entry is 64 bytes
287 * long, so for example a 32 entry queue must be aligned on a 2048
288 * byte real address boundary.
290 * The specified queue is unconfigured if the number of entries is given
293 * For the current version of this API service, the argument queue is defined
297 * ----- -------------------------
298 * 0x3c cpu mondo queue
299 * 0x3d device mondo queue
300 * 0x3e resumable error queue
301 * 0x3f non-resumable error queue
303 * Note: The maximum number of entries for each queue for a specific cpu may
304 * be determined from the machine description.
306 #define HV_FAST_CPU_QCONF 0x14
307 #define HV_CPU_QUEUE_CPU_MONDO 0x3c
308 #define HV_CPU_QUEUE_DEVICE_MONDO 0x3d
309 #define HV_CPU_QUEUE_RES_ERROR 0x3e
310 #define HV_CPU_QUEUE_NONRES_ERROR 0x3f
313 extern unsigned long sun4v_cpu_qconf(unsigned long type,
314 unsigned long queue_paddr,
315 unsigned long num_queue_entries);
320 * FUNCTION: HV_FAST_CPU_QINFO
323 * RET1: base real address
324 * RET1: number of entries
325 * ERRORS: EINVAL Invalid queue
327 * Return the configuration info for the given queue. The base real
328 * address and number of entries of the defined queue are returned.
329 * The queue argument values are the same as for cpu_qconf() above.
331 * If the specified queue is a valid queue number, but no queue has
332 * been defined, the number of entries will be set to zero and the
333 * base real address returned is undefined.
335 #define HV_FAST_CPU_QINFO 0x15
339 * FUNCTION: HV_FAST_CPU_MONDO_SEND
341 * ARG2: data real address
343 * ERRORS: EBADALIGN Mondo data is not 64-byte aligned or CPU list
344 * is not 2-byte aligned.
345 * ENORADDR Invalid data mondo address, or invalid cpu list
347 * ENOCPU Invalid cpu in CPU list
348 * EWOULDBLOCK Some or all of the listed CPUs did not receive
350 * ECPUERROR One or more of the listed CPUs are in error
351 * state, use HV_FAST_CPU_STATE to see which ones
352 * EINVAL CPU list includes caller's CPU ID
354 * Send a mondo interrupt to the CPUs in the given CPU list with the
355 * 64-bytes at the given data real address. The data must be 64-byte
356 * aligned. The mondo data will be delivered to the cpu_mondo queues
357 * of the recipient CPUs.
359 * In all cases, error or not, the CPUs in the CPU list to which the
360 * mondo has been successfully delivered will be indicated by having
361 * their entry in CPU list updated with the value 0xffff.
363 #define HV_FAST_CPU_MONDO_SEND 0x42
366 extern unsigned long sun4v_cpu_mondo_send(unsigned long cpu_count, unsigned long cpu_list_pa, unsigned long mondo_block_pa);
371 * FUNCTION: HV_FAST_CPU_MYID
374 * ERRORS: No errors defined.
376 * Return the hypervisor ID handle for the current CPU. Use by a
377 * virtual CPU to discover it's own identity.
379 #define HV_FAST_CPU_MYID 0x16
383 * FUNCTION: HV_FAST_CPU_STATE
387 * ERRORS: ENOCPU Invalid CPU ID
389 * Retrieve the current state of the CPU with the given CPU ID.
391 #define HV_FAST_CPU_STATE 0x17
392 #define HV_CPU_STATE_STOPPED 0x01
393 #define HV_CPU_STATE_RUNNING 0x02
394 #define HV_CPU_STATE_ERROR 0x03
397 extern long sun4v_cpu_state(unsigned long cpuid);
402 * FUNCTION: HV_FAST_CPU_SET_RTBA
405 * RET1: previous RTBA
406 * ERRORS: ENORADDR Invalid RTBA real address
407 * EBADALIGN RTBA is incorrectly aligned for a trap table
409 * Set the real trap base address of the local cpu to the given RTBA.
410 * The supplied RTBA must be aligned on a 256 byte boundary. Upon
411 * success the previous value of the RTBA is returned in RET1.
413 * Note: This service does not affect %tba
415 #define HV_FAST_CPU_SET_RTBA 0x18
419 * FUNCTION: HV_FAST_CPU_GET_RTBA
421 * RET1: previous RTBA
422 * ERRORS: No possible error.
424 * Returns the current value of RTBA in RET1.
426 #define HV_FAST_CPU_GET_RTBA 0x19
430 * Layout of a TSB description for mmu_tsb_ctx{,non}0() calls.
433 struct hv_tsb_descr {
434 unsigned short pgsz_idx;
435 unsigned short assoc;
436 unsigned int num_ttes; /* in TTEs */
437 unsigned int ctx_idx;
438 unsigned int pgsz_mask;
439 unsigned long tsb_base;
443 #define HV_TSB_DESCR_PGSZ_IDX_OFFSET 0x00
444 #define HV_TSB_DESCR_ASSOC_OFFSET 0x02
445 #define HV_TSB_DESCR_NUM_TTES_OFFSET 0x04
446 #define HV_TSB_DESCR_CTX_IDX_OFFSET 0x08
447 #define HV_TSB_DESCR_PGSZ_MASK_OFFSET 0x0c
448 #define HV_TSB_DESCR_TSB_BASE_OFFSET 0x10
449 #define HV_TSB_DESCR_RESV_OFFSET 0x18
451 /* Page size bitmask. */
452 #define HV_PGSZ_MASK_8K (1 << 0)
453 #define HV_PGSZ_MASK_64K (1 << 1)
454 #define HV_PGSZ_MASK_512K (1 << 2)
455 #define HV_PGSZ_MASK_4MB (1 << 3)
456 #define HV_PGSZ_MASK_32MB (1 << 4)
457 #define HV_PGSZ_MASK_256MB (1 << 5)
458 #define HV_PGSZ_MASK_2GB (1 << 6)
459 #define HV_PGSZ_MASK_16GB (1 << 7)
461 /* Page size index. The value given in the TSB descriptor must correspond
462 * to the smallest page size specified in the pgsz_mask page size bitmask.
464 #define HV_PGSZ_IDX_8K 0
465 #define HV_PGSZ_IDX_64K 1
466 #define HV_PGSZ_IDX_512K 2
467 #define HV_PGSZ_IDX_4MB 3
468 #define HV_PGSZ_IDX_32MB 4
469 #define HV_PGSZ_IDX_256MB 5
470 #define HV_PGSZ_IDX_2GB 6
471 #define HV_PGSZ_IDX_16GB 7
473 /* MMU fault status area.
475 * MMU related faults have their status and fault address information
476 * placed into a memory region made available by privileged code. Each
477 * virtual processor must make a mmu_fault_area_conf() call to tell the
478 * hypervisor where that processor's fault status should be stored.
480 * The fault status block is a multiple of 64-bytes and must be aligned
481 * on a 64-byte boundary.
484 struct hv_fault_status {
485 unsigned long i_fault_type;
486 unsigned long i_fault_addr;
487 unsigned long i_fault_ctx;
488 unsigned long i_reserved[5];
489 unsigned long d_fault_type;
490 unsigned long d_fault_addr;
491 unsigned long d_fault_ctx;
492 unsigned long d_reserved[5];
495 #define HV_FAULT_I_TYPE_OFFSET 0x00
496 #define HV_FAULT_I_ADDR_OFFSET 0x08
497 #define HV_FAULT_I_CTX_OFFSET 0x10
498 #define HV_FAULT_D_TYPE_OFFSET 0x40
499 #define HV_FAULT_D_ADDR_OFFSET 0x48
500 #define HV_FAULT_D_CTX_OFFSET 0x50
502 #define HV_FAULT_TYPE_FAST_MISS 1
503 #define HV_FAULT_TYPE_FAST_PROT 2
504 #define HV_FAULT_TYPE_MMU_MISS 3
505 #define HV_FAULT_TYPE_INV_RA 4
506 #define HV_FAULT_TYPE_PRIV_VIOL 5
507 #define HV_FAULT_TYPE_PROT_VIOL 6
508 #define HV_FAULT_TYPE_NFO 7
509 #define HV_FAULT_TYPE_NFO_SEFF 8
510 #define HV_FAULT_TYPE_INV_VA 9
511 #define HV_FAULT_TYPE_INV_ASI 10
512 #define HV_FAULT_TYPE_NC_ATOMIC 11
513 #define HV_FAULT_TYPE_PRIV_ACT 12
514 #define HV_FAULT_TYPE_RESV1 13
515 #define HV_FAULT_TYPE_UNALIGNED 14
516 #define HV_FAULT_TYPE_INV_PGSZ 15
517 /* Values 16 --> -2 are reserved. */
518 #define HV_FAULT_TYPE_MULTIPLE -1
520 /* Flags argument for mmu_{map,unmap}_addr(), mmu_demap_{page,context,all}(),
521 * and mmu_{map,unmap}_perm_addr().
523 #define HV_MMU_DMMU 0x01
524 #define HV_MMU_IMMU 0x02
525 #define HV_MMU_ALL (HV_MMU_DMMU | HV_MMU_IMMU)
528 * TRAP: HV_MMU_MAP_ADDR_TRAP
529 * ARG0: virtual address
532 * ARG3: flags (HV_MMU_{IMMU,DMMU})
533 * ERRORS: EINVAL Invalid virtual address, mmu context, or flags
534 * EBADPGSZ Invalid page size value
535 * ENORADDR Invalid real address in TTE
537 * Create a non-permanent mapping using the given TTE, virtual
538 * address, and mmu context. The flags argument determines which
539 * (data, or instruction, or both) TLB the mapping gets loaded into.
541 * The behavior is undefined if the valid bit is clear in the TTE.
543 * Note: This API call is for privileged code to specify temporary translation
544 * mappings without the need to create and manage a TSB.
548 * TRAP: HV_MMU_UNMAP_ADDR_TRAP
549 * ARG0: virtual address
551 * ARG2: flags (HV_MMU_{IMMU,DMMU})
552 * ERRORS: EINVAL Invalid virtual address, mmu context, or flags
554 * Demaps the given virtual address in the given mmu context on this
555 * CPU. This function is intended to be used to demap pages mapped
556 * with mmu_map_addr. This service is equivalent to invoking
557 * mmu_demap_page() with only the current CPU in the CPU list. The
558 * flags argument determines which (data, or instruction, or both) TLB
559 * the mapping gets unmapped from.
561 * Attempting to perform an unmap operation for a previously defined
562 * permanent mapping will have undefined results.
567 * FUNCTION: HV_FAST_MMU_TSB_CTX0
568 * ARG0: number of TSB descriptions
569 * ARG1: TSB descriptions pointer
571 * ERRORS: ENORADDR Invalid TSB descriptions pointer or
572 * TSB base within a descriptor
573 * EBADALIGN TSB descriptions pointer is not aligned
574 * to an 8-byte boundary, or TSB base
575 * within a descriptor is not aligned for
577 * EBADPGSZ Invalid page size in a TSB descriptor
578 * EBADTSB Invalid associativity or size in a TSB
580 * EINVAL Invalid number of TSB descriptions, or
581 * invalid context index in a TSB
582 * descriptor, or index page size not
583 * equal to smallest page size in page
584 * size bitmask field.
586 * Configures the TSBs for the current CPU for virtual addresses with
587 * context zero. The TSB descriptions pointer is a pointer to an
588 * array of the given number of TSB descriptions.
590 * Note: The maximum number of TSBs available to a virtual CPU is given by the
591 * mmu-max-#tsbs property of the cpu's corresponding "cpu" node in the
592 * machine description.
594 #define HV_FAST_MMU_TSB_CTX0 0x20
598 * FUNCTION: HV_FAST_MMU_TSB_CTXNON0
599 * ARG0: number of TSB descriptions
600 * ARG1: TSB descriptions pointer
602 * ERRORS: Same as for mmu_tsb_ctx0() above.
604 * Configures the TSBs for the current CPU for virtual addresses with
605 * non-zero contexts. The TSB descriptions pointer is a pointer to an
606 * array of the given number of TSB descriptions.
608 * Note: A maximum of 16 TSBs may be specified in the TSB description list.
610 #define HV_FAST_MMU_TSB_CTXNON0 0x21
614 * FUNCTION: HV_FAST_MMU_DEMAP_PAGE
615 * ARG0: reserved, must be zero
616 * ARG1: reserved, must be zero
617 * ARG2: virtual address
619 * ARG4: flags (HV_MMU_{IMMU,DMMU})
621 * ERRORS: EINVAL Invalid virutal address, context, or
623 * ENOTSUPPORTED ARG0 or ARG1 is non-zero
625 * Demaps any page mapping of the given virtual address in the given
626 * mmu context for the current virtual CPU. Any virtually tagged
627 * caches are guaranteed to be kept consistent. The flags argument
628 * determines which TLB (instruction, or data, or both) participate in
631 * ARG0 and ARG1 are both reserved and must be set to zero.
633 #define HV_FAST_MMU_DEMAP_PAGE 0x22
637 * FUNCTION: HV_FAST_MMU_DEMAP_CTX
638 * ARG0: reserved, must be zero
639 * ARG1: reserved, must be zero
641 * ARG3: flags (HV_MMU_{IMMU,DMMU})
643 * ERRORS: EINVAL Invalid context or flags value
644 * ENOTSUPPORTED ARG0 or ARG1 is non-zero
646 * Demaps all non-permanent virtual page mappings previously specified
647 * for the given context for the current virtual CPU. Any virtual
648 * tagged caches are guaranteed to be kept consistent. The flags
649 * argument determines which TLB (instruction, or data, or both)
650 * participate in the operation.
652 * ARG0 and ARG1 are both reserved and must be set to zero.
654 #define HV_FAST_MMU_DEMAP_CTX 0x23
658 * FUNCTION: HV_FAST_MMU_DEMAP_ALL
659 * ARG0: reserved, must be zero
660 * ARG1: reserved, must be zero
661 * ARG2: flags (HV_MMU_{IMMU,DMMU})
663 * ERRORS: EINVAL Invalid flags value
664 * ENOTSUPPORTED ARG0 or ARG1 is non-zero
666 * Demaps all non-permanent virtual page mappings previously specified
667 * for the current virtual CPU. Any virtual tagged caches are
668 * guaranteed to be kept consistent. The flags argument determines
669 * which TLB (instruction, or data, or both) participate in the
672 * ARG0 and ARG1 are both reserved and must be set to zero.
674 #define HV_FAST_MMU_DEMAP_ALL 0x24
676 /* mmu_map_perm_addr()
678 * FUNCTION: HV_FAST_MMU_MAP_PERM_ADDR
679 * ARG0: virtual address
680 * ARG1: reserved, must be zero
682 * ARG3: flags (HV_MMU_{IMMU,DMMU})
684 * ERRORS: EINVAL Invalid virutal address or flags value
685 * EBADPGSZ Invalid page size value
686 * ENORADDR Invalid real address in TTE
687 * ETOOMANY Too many mappings (max of 8 reached)
689 * Create a permanent mapping using the given TTE and virtual address
690 * for context 0 on the calling virtual CPU. A maximum of 8 such
691 * permanent mappings may be specified by privileged code. Mappings
692 * may be removed with mmu_unmap_perm_addr().
694 * The behavior is undefined if a TTE with the valid bit clear is given.
696 * Note: This call is used to specify address space mappings for which
697 * privileged code does not expect to receive misses. For example,
698 * this mechanism can be used to map kernel nucleus code and data.
700 #define HV_FAST_MMU_MAP_PERM_ADDR 0x25
702 /* mmu_fault_area_conf()
704 * FUNCTION: HV_FAST_MMU_FAULT_AREA_CONF
707 * RET1: previous mmu fault area real address
708 * ERRORS: ENORADDR Invalid real address
709 * EBADALIGN Invalid alignment for fault area
711 * Configure the MMU fault status area for the calling CPU. A 64-byte
712 * aligned real address specifies where MMU fault status information
713 * is placed. The return value is the previously specified area, or 0
714 * for the first invocation. Specifying a fault area at real address
717 #define HV_FAST_MMU_FAULT_AREA_CONF 0x26
721 * FUNCTION: HV_FAST_MMU_ENABLE
723 * ARG1: return target address
725 * ERRORS: ENORADDR Invalid real address when disabling
727 * EBADALIGN The return target address is not
728 * aligned to an instruction.
729 * EINVAL The enable flag request the current
730 * operating mode (e.g. disable if already
733 * Enable or disable virtual address translation for the calling CPU
734 * within the virtual machine domain. If the enable flag is zero,
735 * translation is disabled, any non-zero value will enable
738 * When this function returns, the newly selected translation mode
739 * will be active. If the mmu is being enabled, then the return
740 * target address is a virtual address else it is a real address.
742 * Upon successful completion, control will be returned to the given
743 * return target address (ie. the cpu will jump to that address). On
744 * failure, the previous mmu mode remains and the trap simply returns
745 * as normal with the appropriate error code in RET0.
747 #define HV_FAST_MMU_ENABLE 0x27
749 /* mmu_unmap_perm_addr()
751 * FUNCTION: HV_FAST_MMU_UNMAP_PERM_ADDR
752 * ARG0: virtual address
753 * ARG1: reserved, must be zero
754 * ARG2: flags (HV_MMU_{IMMU,DMMU})
756 * ERRORS: EINVAL Invalid virutal address or flags value
757 * ENOMAP Specified mapping was not found
759 * Demaps any permanent page mapping (established via
760 * mmu_map_perm_addr()) at the given virtual address for context 0 on
761 * the current virtual CPU. Any virtual tagged caches are guaranteed
762 * to be kept consistent.
764 #define HV_FAST_MMU_UNMAP_PERM_ADDR 0x28
766 /* mmu_tsb_ctx0_info()
768 * FUNCTION: HV_FAST_MMU_TSB_CTX0_INFO
770 * ARG1: buffer pointer
772 * RET1: number of TSBs
773 * ERRORS: EINVAL Supplied buffer is too small
774 * EBADALIGN The buffer pointer is badly aligned
775 * ENORADDR Invalid real address for buffer pointer
777 * Return the TSB configuration as previous defined by mmu_tsb_ctx0()
778 * into the provided buffer. The size of the buffer is given in ARG1
779 * in terms of the number of TSB description entries.
781 * Upon return, RET1 always contains the number of TSB descriptions
782 * previously configured. If zero TSBs were configured, EOK is
783 * returned with RET1 containing 0.
785 #define HV_FAST_MMU_TSB_CTX0_INFO 0x29
787 /* mmu_tsb_ctxnon0_info()
789 * FUNCTION: HV_FAST_MMU_TSB_CTXNON0_INFO
791 * ARG1: buffer pointer
793 * RET1: number of TSBs
794 * ERRORS: EINVAL Supplied buffer is too small
795 * EBADALIGN The buffer pointer is badly aligned
796 * ENORADDR Invalid real address for buffer pointer
798 * Return the TSB configuration as previous defined by
799 * mmu_tsb_ctxnon0() into the provided buffer. The size of the buffer
800 * is given in ARG1 in terms of the number of TSB description entries.
802 * Upon return, RET1 always contains the number of TSB descriptions
803 * previously configured. If zero TSBs were configured, EOK is
804 * returned with RET1 containing 0.
806 #define HV_FAST_MMU_TSB_CTXNON0_INFO 0x2a
808 /* mmu_fault_area_info()
810 * FUNCTION: HV_FAST_MMU_FAULT_AREA_INFO
812 * RET1: fault area real address
813 * ERRORS: No errors defined.
815 * Return the currently defined MMU fault status area for the current
816 * CPU. The real address of the fault status area is returned in
817 * RET1, or 0 is returned in RET1 if no fault status area is defined.
819 * Note: mmu_fault_area_conf() may be called with the return value (RET1)
820 * from this service if there is a need to save and restore the fault
823 #define HV_FAST_MMU_FAULT_AREA_INFO 0x2b
825 /* Cache and Memory services. */
829 * FUNCTION: HV_FAST_MEM_SCRUB
833 * RET1: length scrubbed
834 * ERRORS: ENORADDR Invalid real address
835 * EBADALIGN Start address or length are not correctly
837 * EINVAL Length is zero
839 * Zero the memory contents in the range real address to real address
840 * plus length minus 1. Also, valid ECC will be generated for that
841 * memory address range. Scrubbing is started at the given real
842 * address, but may not scrub the entire given length. The actual
843 * length scrubbed will be returned in RET1.
845 * The real address and length must be aligned on an 8K boundary, or
846 * contain the start address and length from a sun4v error report.
848 * Note: There are two uses for this function. The first use is to block clear
849 * and initialize memory and the second is to scrub an u ncorrectable
850 * error reported via a resumable or non-resumable trap. The second
851 * use requires the arguments to be equal to the real address and length
852 * provided in a sun4v memory error report.
854 #define HV_FAST_MEM_SCRUB 0x31
858 * FUNCTION: HV_FAST_MEM_SYNC
862 * RET1: length synced
863 * ERRORS: ENORADDR Invalid real address
864 * EBADALIGN Start address or length are not correctly
866 * EINVAL Length is zero
868 * Force the next access within the real address to real address plus
869 * length minus 1 to be fetches from main system memory. Less than
870 * the given length may be synced, the actual amount synced is
871 * returned in RET1. The real address and length must be aligned on
874 #define HV_FAST_MEM_SYNC 0x32
876 /* Time of day services.
878 * The hypervisor maintains the time of day on a per-domain basis.
879 * Changing the time of day in one domain does not affect the time of
880 * day on any other domain.
882 * Time is described by a single unsigned 64-bit word which is the
883 * number of seconds since the UNIX Epoch (00:00:00 UTC, January 1,
889 * FUNCTION: HV_FAST_TOD_GET
892 * ERRORS: EWOULDBLOCK TOD resource is temporarily unavailable
893 * ENOTSUPPORTED If TOD not supported on this platform
895 * Return the current time of day. May block if TOD access is
896 * temporarily not possible.
898 #define HV_FAST_TOD_GET 0x50
902 * FUNCTION: HV_FAST_TOD_SET
905 * ERRORS: EWOULDBLOCK TOD resource is temporarily unavailable
906 * ENOTSUPPORTED If TOD not supported on this platform
908 * The current time of day is set to the value specified in ARG0. May
909 * block if TOD access is temporarily not possible.
911 #define HV_FAST_TOD_SET 0x51
913 /* Console services */
917 * FUNCTION: HV_FAST_CONS_GETCHAR
920 * ERRORS: EWOULDBLOCK No character available.
922 * Returns a character from the console device. If no character is
923 * available then an EWOULDBLOCK error is returned. If a character is
924 * available, then the returned status is EOK and the character value
927 * A virtual BREAK is represented by the 64-bit value -1.
929 * A virtual HUP signal is represented by the 64-bit value -2.
931 #define HV_FAST_CONS_GETCHAR 0x60
935 * FUNCTION: HV_FAST_CONS_PUTCHAR
938 * ERRORS: EINVAL Illegal character
939 * EWOULDBLOCK Output buffer currently full, would block
941 * Send a character to the console device. Only character values
942 * between 0 and 255 may be used. Values outside this range are
943 * invalid except for the 64-bit value -1 which is used to send a
946 #define HV_FAST_CONS_PUTCHAR 0x61
950 * FUNCTION: HV_FAST_CONS_READ
951 * ARG0: buffer real address
952 * ARG1: buffer size in bytes
954 * RET1: bytes read or BREAK or HUP
955 * ERRORS: EWOULDBLOCK No character available.
957 * Reads characters into a buffer from the console device. If no
958 * character is available then an EWOULDBLOCK error is returned.
959 * If a character is available, then the returned status is EOK
960 * and the number of bytes read into the given buffer is provided
963 * A virtual BREAK is represented by the 64-bit RET1 value -1.
965 * A virtual HUP signal is represented by the 64-bit RET1 value -2.
967 * If BREAK or HUP are indicated, no bytes were read into buffer.
969 #define HV_FAST_CONS_READ 0x62
973 * FUNCTION: HV_FAST_CONS_WRITE
974 * ARG0: buffer real address
975 * ARG1: buffer size in bytes
977 * RET1: bytes written
978 * ERRORS: EWOULDBLOCK Output buffer currently full, would block
980 * Send a characters in buffer to the console device. Breaks must be
981 * sent using con_putchar().
983 #define HV_FAST_CONS_WRITE 0x63
986 extern long sun4v_con_getchar(long *status);
987 extern long sun4v_con_putchar(long c);
988 extern long sun4v_con_read(unsigned long buffer,
990 unsigned long *bytes_read);
991 extern unsigned long sun4v_con_write(unsigned long buffer,
993 unsigned long *bytes_written);
996 /* Trap trace services.
998 * The hypervisor provides a trap tracing capability for privileged
999 * code running on each virtual CPU. Privileged code provides a
1000 * round-robin trap trace queue within which the hypervisor writes
1001 * 64-byte entries detailing hyperprivileged traps taken n behalf of
1002 * privileged code. This is provided as a debugging capability for
1005 * The trap trace control structure is 64-bytes long and placed at the
1006 * start (offset 0) of the trap trace buffer, and is described as
1009 #ifndef __ASSEMBLY__
1010 struct hv_trap_trace_control {
1011 unsigned long head_offset;
1012 unsigned long tail_offset;
1013 unsigned long __reserved[0x30 / sizeof(unsigned long)];
1016 #define HV_TRAP_TRACE_CTRL_HEAD_OFFSET 0x00
1017 #define HV_TRAP_TRACE_CTRL_TAIL_OFFSET 0x08
1019 /* The head offset is the offset of the most recently completed entry
1020 * in the trap-trace buffer. The tail offset is the offset of the
1021 * next entry to be written. The control structure is owned and
1022 * modified by the hypervisor. A guest may not modify the control
1023 * structure contents. Attempts to do so will result in undefined
1024 * behavior for the guest.
1026 * Each trap trace buffer entry is layed out as follows:
1028 #ifndef __ASSEMBLY__
1029 struct hv_trap_trace_entry {
1030 unsigned char type; /* Hypervisor or guest entry? */
1031 unsigned char hpstate; /* Hyper-privileged state */
1032 unsigned char tl; /* Trap level */
1033 unsigned char gl; /* Global register level */
1034 unsigned short tt; /* Trap type */
1035 unsigned short tag; /* Extended trap identifier */
1036 unsigned long tstate; /* Trap state */
1037 unsigned long tick; /* Tick */
1038 unsigned long tpc; /* Trap PC */
1039 unsigned long f1; /* Entry specific */
1040 unsigned long f2; /* Entry specific */
1041 unsigned long f3; /* Entry specific */
1042 unsigned long f4; /* Entry specific */
1045 #define HV_TRAP_TRACE_ENTRY_TYPE 0x00
1046 #define HV_TRAP_TRACE_ENTRY_HPSTATE 0x01
1047 #define HV_TRAP_TRACE_ENTRY_TL 0x02
1048 #define HV_TRAP_TRACE_ENTRY_GL 0x03
1049 #define HV_TRAP_TRACE_ENTRY_TT 0x04
1050 #define HV_TRAP_TRACE_ENTRY_TAG 0x06
1051 #define HV_TRAP_TRACE_ENTRY_TSTATE 0x08
1052 #define HV_TRAP_TRACE_ENTRY_TICK 0x10
1053 #define HV_TRAP_TRACE_ENTRY_TPC 0x18
1054 #define HV_TRAP_TRACE_ENTRY_F1 0x20
1055 #define HV_TRAP_TRACE_ENTRY_F2 0x28
1056 #define HV_TRAP_TRACE_ENTRY_F3 0x30
1057 #define HV_TRAP_TRACE_ENTRY_F4 0x38
1059 /* The type field is encoded as follows. */
1060 #define HV_TRAP_TYPE_UNDEF 0x00 /* Entry content undefined */
1061 #define HV_TRAP_TYPE_HV 0x01 /* Hypervisor trap entry */
1062 #define HV_TRAP_TYPE_GUEST 0xff /* Added via ttrace_addentry() */
1064 /* ttrace_buf_conf()
1065 * TRAP: HV_FAST_TRAP
1066 * FUNCTION: HV_FAST_TTRACE_BUF_CONF
1067 * ARG0: real address
1068 * ARG1: number of entries
1070 * RET1: number of entries
1071 * ERRORS: ENORADDR Invalid real address
1072 * EINVAL Size is too small
1073 * EBADALIGN Real address not aligned on 64-byte boundary
1075 * Requests hypervisor trap tracing and declares a virtual CPU's trap
1076 * trace buffer to the hypervisor. The real address supplies the real
1077 * base address of the trap trace queue and must be 64-byte aligned.
1078 * Specifying a value of 0 for the number of entries disables trap
1079 * tracing for the calling virtual CPU. The buffer allocated must be
1080 * sized for a power of two number of 64-byte trap trace entries plus
1081 * an initial 64-byte control structure.
1083 * This may be invoked any number of times so that a virtual CPU may
1084 * relocate a trap trace buffer or create "snapshots" of information.
1086 * If the real address is illegal or badly aligned, then trap tracing
1087 * is disabled and an error is returned.
1089 * Upon failure with EINVAL, this service call returns in RET1 the
1090 * minimum number of buffer entries required. Upon other failures
1091 * RET1 is undefined.
1093 #define HV_FAST_TTRACE_BUF_CONF 0x90
1095 /* ttrace_buf_info()
1096 * TRAP: HV_FAST_TRAP
1097 * FUNCTION: HV_FAST_TTRACE_BUF_INFO
1099 * RET1: real address
1101 * ERRORS: None defined.
1103 * Returns the size and location of the previously declared trap-trace
1104 * buffer. In the event that no buffer was previously defined, or the
1105 * buffer is disabled, this call will return a size of zero bytes.
1107 #define HV_FAST_TTRACE_BUF_INFO 0x91
1110 * TRAP: HV_FAST_TRAP
1111 * FUNCTION: HV_FAST_TTRACE_ENABLE
1114 * RET1: previous enable state
1115 * ERRORS: EINVAL No trap trace buffer currently defined
1117 * Enable or disable trap tracing, and return the previous enabled
1118 * state in RET1. Future systems may define various flags for the
1119 * enable argument (ARG0), for the moment a guest should pass
1120 * "(uint64_t) -1" to enable, and "(uint64_t) 0" to disable all
1121 * tracing - which will ensure future compatability.
1123 #define HV_FAST_TTRACE_ENABLE 0x92
1126 * TRAP: HV_FAST_TRAP
1127 * FUNCTION: HV_FAST_TTRACE_FREEZE
1130 * RET1: previous freeze state
1131 * ERRORS: EINVAL No trap trace buffer currently defined
1133 * Freeze or unfreeze trap tracing, returning the previous freeze
1134 * state in RET1. A guest should pass a non-zero value to freeze and
1135 * a zero value to unfreeze all tracing. The returned previous state
1136 * is 0 for not frozen and 1 for frozen.
1138 #define HV_FAST_TTRACE_FREEZE 0x93
1140 /* ttrace_addentry()
1141 * TRAP: HV_TTRACE_ADDENTRY_TRAP
1142 * ARG0: tag (16-bits)
1148 * ERRORS: EINVAL No trap trace buffer currently defined
1150 * Add an entry to the trap trace buffer. Upon return only ARG0/RET0
1151 * is modified - none of the other registers holding arguments are
1152 * volatile across this hypervisor service.
1155 /* Core dump services.
1157 * Since the hypervisor viraulizes and thus obscures a lot of the
1158 * physical machine layout and state, traditional OS crash dumps can
1159 * be difficult to diagnose especially when the problem is a
1160 * configuration error of some sort.
1162 * The dump services provide an opaque buffer into which the
1163 * hypervisor can place it's internal state in order to assist in
1164 * debugging such situations. The contents are opaque and extremely
1165 * platform and hypervisor implementation specific. The guest, during
1166 * a core dump, requests that the hypervisor update any information in
1167 * the dump buffer in preparation to being dumped as part of the
1168 * domain's memory image.
1171 /* dump_buf_update()
1172 * TRAP: HV_FAST_TRAP
1173 * FUNCTION: HV_FAST_DUMP_BUF_UPDATE
1174 * ARG0: real address
1177 * RET1: required size of dump buffer
1178 * ERRORS: ENORADDR Invalid real address
1179 * EBADALIGN Real address is not aligned on a 64-byte
1181 * EINVAL Size is non-zero but less than minimum size
1183 * ENOTSUPPORTED Operation not supported on current logical
1186 * Declare a domain dump buffer to the hypervisor. The real address
1187 * provided for the domain dump buffer must be 64-byte aligned. The
1188 * size specifies the size of the dump buffer and may be larger than
1189 * the minimum size specified in the machine description. The
1190 * hypervisor will fill the dump buffer with opaque data.
1192 * Note: A guest may elect to include dump buffer contents as part of a crash
1193 * dump to assist with debugging. This function may be called any number
1194 * of times so that a guest may relocate a dump buffer, or create
1195 * "snapshots" of any dump-buffer information. Each call to
1196 * dump_buf_update() atomically declares the new dump buffer to the
1199 * A specified size of 0 unconfigures the dump buffer. If the real
1200 * address is illegal or badly aligned, then any currently active dump
1201 * buffer is disabled and an error is returned.
1203 * In the event that the call fails with EINVAL, RET1 contains the
1204 * minimum size requires by the hypervisor for a valid dump buffer.
1206 #define HV_FAST_DUMP_BUF_UPDATE 0x94
1209 * TRAP: HV_FAST_TRAP
1210 * FUNCTION: HV_FAST_DUMP_BUF_INFO
1212 * RET1: real address of current dump buffer
1213 * RET2: size of current dump buffer
1214 * ERRORS: No errors defined.
1216 * Return the currently configures dump buffer description. A
1217 * returned size of 0 bytes indicates an undefined dump buffer. In
1218 * this case the return address in RET1 is undefined.
1220 #define HV_FAST_DUMP_BUF_INFO 0x95
1222 /* Device interrupt services.
1224 * Device interrupts are allocated to system bus bridges by the hypervisor,
1225 * and described to OBP in the machine description. OBP then describes
1226 * these interrupts to the OS via properties in the device tree.
1230 * cpuid Unique opaque value which represents a target cpu.
1232 * devhandle Device handle. It uniquely identifies a device, and
1233 * consistes of the lower 28-bits of the hi-cell of the
1234 * first entry of the device's "reg" property in the
1237 * devino Device interrupt number. Specifies the relative
1238 * interrupt number within the device. The unique
1239 * combination of devhandle and devino are used to
1240 * identify a specific device interrupt.
1242 * Note: The devino value is the same as the values in the
1243 * "interrupts" property or "interrupt-map" property
1244 * in the OBP device tree for that device.
1246 * sysino System interrupt number. A 64-bit unsigned interger
1247 * representing a unique interrupt within a virtual
1250 * intr_state A flag representing the interrupt state for a given
1251 * sysino. The state values are defined below.
1253 * intr_enabled A flag representing the 'enabled' state for a given
1254 * sysino. The enable values are defined below.
1257 #define HV_INTR_STATE_IDLE 0 /* Nothing pending */
1258 #define HV_INTR_STATE_RECEIVED 1 /* Interrupt received by hardware */
1259 #define HV_INTR_STATE_DELIVERED 2 /* Interrupt delivered to queue */
1261 #define HV_INTR_DISABLED 0 /* sysino not enabled */
1262 #define HV_INTR_ENABLED 1 /* sysino enabled */
1264 /* intr_devino_to_sysino()
1265 * TRAP: HV_FAST_TRAP
1266 * FUNCTION: HV_FAST_INTR_DEVINO2SYSINO
1271 * ERRORS: EINVAL Invalid devhandle/devino
1273 * Converts a device specific interrupt number of the given
1274 * devhandle/devino into a system specific ino (sysino).
1276 #define HV_FAST_INTR_DEVINO2SYSINO 0xa0
1278 #ifndef __ASSEMBLY__
1279 extern unsigned long sun4v_devino_to_sysino(unsigned long devhandle,
1280 unsigned long devino);
1283 /* intr_getenabled()
1284 * TRAP: HV_FAST_TRAP
1285 * FUNCTION: HV_FAST_INTR_GETENABLED
1288 * RET1: intr_enabled (HV_INTR_{DISABLED,ENABLED})
1289 * ERRORS: EINVAL Invalid sysino
1291 * Returns interrupt enabled state in RET1 for the interrupt defined
1292 * by the given sysino.
1294 #define HV_FAST_INTR_GETENABLED 0xa1
1296 #ifndef __ASSEMBLY__
1297 extern unsigned long sun4v_intr_getenabled(unsigned long sysino);
1300 /* intr_setenabled()
1301 * TRAP: HV_FAST_TRAP
1302 * FUNCTION: HV_FAST_INTR_SETENABLED
1304 * ARG1: intr_enabled (HV_INTR_{DISABLED,ENABLED})
1306 * ERRORS: EINVAL Invalid sysino or intr_enabled value
1308 * Set the 'enabled' state of the interrupt sysino.
1310 #define HV_FAST_INTR_SETENABLED 0xa2
1312 #ifndef __ASSEMBLY__
1313 extern unsigned long sun4v_intr_setenabled(unsigned long sysino, unsigned long intr_enabled);
1317 * TRAP: HV_FAST_TRAP
1318 * FUNCTION: HV_FAST_INTR_GETSTATE
1321 * RET1: intr_state (HV_INTR_STATE_*)
1322 * ERRORS: EINVAL Invalid sysino
1324 * Returns current state of the interrupt defined by the given sysino.
1326 #define HV_FAST_INTR_GETSTATE 0xa3
1328 #ifndef __ASSEMBLY__
1329 extern unsigned long sun4v_intr_getstate(unsigned long sysino);
1333 * TRAP: HV_FAST_TRAP
1334 * FUNCTION: HV_FAST_INTR_SETSTATE
1336 * ARG1: intr_state (HV_INTR_STATE_*)
1338 * ERRORS: EINVAL Invalid sysino or intr_state value
1340 * Sets the current state of the interrupt described by the given sysino
1343 * Note: Setting the state to HV_INTR_STATE_IDLE clears any pending
1344 * interrupt for sysino.
1346 #define HV_FAST_INTR_SETSTATE 0xa4
1348 #ifndef __ASSEMBLY__
1349 extern unsigned long sun4v_intr_setstate(unsigned long sysino, unsigned long intr_state);
1353 * TRAP: HV_FAST_TRAP
1354 * FUNCTION: HV_FAST_INTR_GETTARGET
1358 * ERRORS: EINVAL Invalid sysino
1360 * Returns CPU that is the current target of the interrupt defined by
1361 * the given sysino. The CPU value returned is undefined if the target
1362 * has not been set via intr_settarget().
1364 #define HV_FAST_INTR_GETTARGET 0xa5
1366 #ifndef __ASSEMBLY__
1367 extern unsigned long sun4v_intr_gettarget(unsigned long sysino);
1371 * TRAP: HV_FAST_TRAP
1372 * FUNCTION: HV_FAST_INTR_SETTARGET
1376 * ERRORS: EINVAL Invalid sysino
1377 * ENOCPU Invalid cpuid
1379 * Set the target CPU for the interrupt defined by the given sysino.
1381 #define HV_FAST_INTR_SETTARGET 0xa6
1383 #ifndef __ASSEMBLY__
1384 extern unsigned long sun4v_intr_settarget(unsigned long sysino, unsigned long cpuid);
1389 * See the terminology descriptions in the device interrupt services
1390 * section above as those apply here too. Here are terminology
1391 * definitions specific to these PCI IO services:
1393 * tsbnum TSB number. Indentifies which io-tsb is used.
1394 * For this version of the specification, tsbnum
1397 * tsbindex TSB index. Identifies which entry in the TSB
1398 * is used. The first entry is zero.
1400 * tsbid A 64-bit aligned data structure which contains
1401 * a tsbnum and a tsbindex. Bits 63:32 contain the
1402 * tsbnum and bits 31:00 contain the tsbindex.
1404 * Use the HV_PCI_TSBID() macro to construct such
1407 * io_attributes IO attributes for IOMMU mappings. One of more
1408 * of the attritbute bits are stores in a 64-bit
1409 * value. The values are defined below.
1411 * r_addr 64-bit real address
1413 * pci_device PCI device address. A PCI device address identifies
1414 * a specific device on a specific PCI bus segment.
1415 * A PCI device address ia a 32-bit unsigned integer
1416 * with the following format:
1418 * 00000000.bbbbbbbb.dddddfff.00000000
1420 * Use the HV_PCI_DEVICE_BUILD() macro to construct
1424 * PCI configureation space offset. For conventional
1425 * PCI a value between 0 and 255. For extended
1426 * configuration space, a value between 0 and 4095.
1428 * Note: For PCI configuration space accesses, the offset
1429 * must be aligned to the access size.
1431 * error_flag A return value which specifies if the action succeeded
1432 * or failed. 0 means no error, non-0 means some error
1433 * occurred while performing the service.
1436 * Direction definition for pci_dma_sync(), defined
1437 * below in HV_PCI_SYNC_*.
1439 * io_page_list A list of io_page_addresses, an io_page_address is
1442 * io_page_list_p A pointer to an io_page_list.
1444 * "size based byte swap" - Some functions do size based byte swapping
1445 * which allows sw to access pointers and
1446 * counters in native form when the processor
1447 * operates in a different endianness than the
1448 * IO bus. Size-based byte swapping converts a
1449 * multi-byte field between big-endian and
1450 * little-endian format.
1453 #define HV_PCI_MAP_ATTR_READ 0x01
1454 #define HV_PCI_MAP_ATTR_WRITE 0x02
1456 #define HV_PCI_DEVICE_BUILD(b,d,f) \
1457 ((((b) & 0xff) << 16) | \
1458 (((d) & 0x1f) << 11) | \
1459 (((f) & 0x07) << 8))
1461 #define HV_PCI_TSBID(__tsb_num, __tsb_index) \
1462 ((((u64)(__tsb_num)) << 32UL) | ((u64)(__tsb_index)))
1464 #define HV_PCI_SYNC_FOR_DEVICE 0x01
1465 #define HV_PCI_SYNC_FOR_CPU 0x02
1468 * TRAP: HV_FAST_TRAP
1469 * FUNCTION: HV_FAST_PCI_IOMMU_MAP
1473 * ARG3: io_attributes
1474 * ARG4: io_page_list_p
1476 * RET1: #ttes mapped
1477 * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex/io_attributes
1478 * EBADALIGN Improperly aligned real address
1479 * ENORADDR Invalid real address
1481 * Create IOMMU mappings in the sun4v device defined by the given
1482 * devhandle. The mappings are created in the TSB defined by the
1483 * tsbnum component of the given tsbid. The first mapping is created
1484 * in the TSB i ndex defined by the tsbindex component of the given tsbid.
1485 * The call creates up to #ttes mappings, the first one at tsbnum, tsbindex,
1486 * the second at tsbnum, tsbindex + 1, etc.
1488 * All mappings are created with the attributes defined by the io_attributes
1489 * argument. The page mapping addresses are described in the io_page_list
1490 * defined by the given io_page_list_p, which is a pointer to the io_page_list.
1491 * The first entry in the io_page_list is the address for the first iotte, the
1492 * 2nd for the 2nd iotte, and so on.
1494 * Each io_page_address in the io_page_list must be appropriately aligned.
1495 * #ttes must be greater than zero. For this version of the spec, the tsbnum
1496 * component of the given tsbid must be zero.
1498 * Returns the actual number of mappings creates, which may be less than
1499 * or equal to the argument #ttes. If the function returns a value which
1500 * is less than the #ttes, the caller may continus to call the function with
1501 * an updated tsbid, #ttes, io_page_list_p arguments until all pages are
1504 * Note: This function does not imply an iotte cache flush. The guest must
1505 * demap an entry before re-mapping it.
1507 #define HV_FAST_PCI_IOMMU_MAP 0xb0
1509 /* pci_iommu_demap()
1510 * TRAP: HV_FAST_TRAP
1511 * FUNCTION: HV_FAST_PCI_IOMMU_DEMAP
1516 * RET1: #ttes demapped
1517 * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex
1519 * Demap and flush IOMMU mappings in the device defined by the given
1520 * devhandle. Demaps up to #ttes entries in the TSB defined by the tsbnum
1521 * component of the given tsbid, starting at the TSB index defined by the
1522 * tsbindex component of the given tsbid.
1524 * For this version of the spec, the tsbnum of the given tsbid must be zero.
1525 * #ttes must be greater than zero.
1527 * Returns the actual number of ttes demapped, which may be less than or equal
1528 * to the argument #ttes. If #ttes demapped is less than #ttes, the caller
1529 * may continue to call this function with updated tsbid and #ttes arguments
1530 * until all pages are demapped.
1532 * Note: Entries do not have to be mapped to be demapped. A demap of an
1533 * unmapped page will flush the entry from the tte cache.
1535 #define HV_FAST_PCI_IOMMU_DEMAP 0xb1
1537 /* pci_iommu_getmap()
1538 * TRAP: HV_FAST_TRAP
1539 * FUNCTION: HV_FAST_PCI_IOMMU_GETMAP
1543 * RET1: io_attributes
1544 * RET2: real address
1545 * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex
1546 * ENOMAP Mapping is not valid, no translation exists
1548 * Read and return the mapping in the device described by the given devhandle
1549 * and tsbid. If successful, the io_attributes shall be returned in RET1
1550 * and the page address of the mapping shall be returned in RET2.
1552 * For this version of the spec, the tsbnum component of the given tsbid
1555 #define HV_FAST_PCI_IOMMU_GETMAP 0xb2
1557 /* pci_iommu_getbypass()
1558 * TRAP: HV_FAST_TRAP
1559 * FUNCTION: HV_FAST_PCI_IOMMU_GETBYPASS
1561 * ARG1: real address
1562 * ARG2: io_attributes
1565 * ERRORS: EINVAL Invalid devhandle/io_attributes
1566 * ENORADDR Invalid real address
1567 * ENOTSUPPORTED Function not supported in this implementation.
1569 * Create a "special" mapping in the device described by the given devhandle,
1570 * for the given real address and attributes. Return the IO address in RET1
1573 #define HV_FAST_PCI_IOMMU_GETBYPASS 0xb3
1576 * TRAP: HV_FAST_TRAP
1577 * FUNCTION: HV_FAST_PCI_CONFIG_GET
1580 * ARG2: pci_config_offset
1585 * ERRORS: EINVAL Invalid devhandle/pci_device/offset/size
1586 * EBADALIGN pci_config_offset not size aligned
1587 * ENOACCESS Access to this offset is not permitted
1589 * Read PCI configuration space for the adapter described by the given
1590 * devhandle. Read size (1, 2, or 4) bytes of data from the given
1591 * pci_device, at pci_config_offset from the beginning of the device's
1592 * configuration space. If there was no error, RET1 is set to zero and
1593 * RET2 is set to the data read. Insignificant bits in RET2 are not
1594 * guarenteed to have any specific value and therefore must be ignored.
1596 * The data returned in RET2 is size based byte swapped.
1598 * If an error occurs during the read, set RET1 to a non-zero value. The
1599 * given pci_config_offset must be 'size' aligned.
1601 #define HV_FAST_PCI_CONFIG_GET 0xb4
1604 * TRAP: HV_FAST_TRAP
1605 * FUNCTION: HV_FAST_PCI_CONFIG_PUT
1608 * ARG2: pci_config_offset
1613 * ERRORS: EINVAL Invalid devhandle/pci_device/offset/size
1614 * EBADALIGN pci_config_offset not size aligned
1615 * ENOACCESS Access to this offset is not permitted
1617 * Write PCI configuration space for the adapter described by the given
1618 * devhandle. Write size (1, 2, or 4) bytes of data in a single operation,
1619 * at pci_config_offset from the beginning of the device's configuration
1620 * space. The data argument contains the data to be written to configuration
1621 * space. Prior to writing, the data is size based byte swapped.
1623 * If an error occurs during the write access, do not generate an error
1624 * report, do set RET1 to a non-zero value. Otherwise RET1 is zero.
1625 * The given pci_config_offset must be 'size' aligned.
1627 * This function is permitted to read from offset zero in the configuration
1628 * space described by the given pci_device if necessary to ensure that the
1629 * write access to config space completes.
1631 #define HV_FAST_PCI_CONFIG_PUT 0xb5
1634 * TRAP: HV_FAST_TRAP
1635 * FUNCTION: HV_FAST_PCI_PEEK
1637 * ARG1: real address
1642 * ERRORS: EINVAL Invalid devhandle or size
1643 * EBADALIGN Improperly aligned real address
1644 * ENORADDR Bad real address
1645 * ENOACCESS Guest access prohibited
1647 * Attempt to read the IO address given by the given devhandle, real address,
1648 * and size. Size must be 1, 2, 4, or 8. The read is performed as a single
1649 * access operation using the given size. If an error occurs when reading
1650 * from the given location, do not generate an error report, but return a
1651 * non-zero value in RET1. If the read was successful, return zero in RET1
1652 * and return the actual data read in RET2. The data returned is size based
1655 * Non-significant bits in RET2 are not guarenteed to have any specific value
1656 * and therefore must be ignored. If RET1 is returned as non-zero, the data
1657 * value is not guarenteed to have any specific value and should be ignored.
1659 * The caller must have permission to read from the given devhandle, real
1660 * address, which must be an IO address. The argument real address must be a
1661 * size aligned address.
1663 * The hypervisor implementation of this function must block access to any
1664 * IO address that the guest does not have explicit permission to access.
1666 #define HV_FAST_PCI_PEEK 0xb6
1669 * TRAP: HV_FAST_TRAP
1670 * FUNCTION: HV_FAST_PCI_POKE
1672 * ARG1: real address
1678 * ERRORS: EINVAL Invalid devhandle, size, or pci_device
1679 * EBADALIGN Improperly aligned real address
1680 * ENORADDR Bad real address
1681 * ENOACCESS Guest access prohibited
1682 * ENOTSUPPORTED Function is not supported by implementation
1684 * Attempt to write data to the IO address given by the given devhandle,
1685 * real address, and size. Size must be 1, 2, 4, or 8. The write is
1686 * performed as a single access operation using the given size. Prior to
1687 * writing the data is size based swapped.
1689 * If an error occurs when writing to the given location, do not generate an
1690 * error report, but return a non-zero value in RET1. If the write was
1691 * successful, return zero in RET1.
1693 * pci_device describes the configuration address of the device being
1694 * written to. The implementation may safely read from offset 0 with
1695 * the configuration space of the device described by devhandle and
1696 * pci_device in order to guarantee that the write portion of the operation
1699 * Any error that occurs due to the read shall be reported using the normal
1700 * error reporting mechanisms .. the read error is not suppressed.
1702 * The caller must have permission to write to the given devhandle, real
1703 * address, which must be an IO address. The argument real address must be a
1704 * size aligned address. The caller must have permission to read from
1705 * the given devhandle, pci_device cofiguration space offset 0.
1707 * The hypervisor implementation of this function must block access to any
1708 * IO address that the guest does not have explicit permission to access.
1710 #define HV_FAST_PCI_POKE 0xb7
1713 * TRAP: HV_FAST_TRAP
1714 * FUNCTION: HV_FAST_PCI_DMA_SYNC
1716 * ARG1: real address
1718 * ARG3: io_sync_direction
1721 * ERRORS: EINVAL Invalid devhandle or io_sync_direction
1722 * ENORADDR Bad real address
1724 * Synchronize a memory region described by the given real address and size,
1725 * for the device defined by the given devhandle using the direction(s)
1726 * defined by the given io_sync_direction. The argument size is the size of
1727 * the memory region in bytes.
1729 * Return the actual number of bytes synchronized in the return value #synced,
1730 * which may be less than or equal to the argument size. If the return
1731 * value #synced is less than size, the caller must continue to call this
1732 * function with updated real address and size arguments until the entire
1733 * memory region is synchronized.
1735 #define HV_FAST_PCI_DMA_SYNC 0xb8
1737 /* PCI MSI services. */
1739 #define HV_MSITYPE_MSI32 0x00
1740 #define HV_MSITYPE_MSI64 0x01
1742 #define HV_MSIQSTATE_IDLE 0x00
1743 #define HV_MSIQSTATE_ERROR 0x01
1745 #define HV_MSIQ_INVALID 0x00
1746 #define HV_MSIQ_VALID 0x01
1748 #define HV_MSISTATE_IDLE 0x00
1749 #define HV_MSISTATE_DELIVERED 0x01
1751 #define HV_MSIVALID_INVALID 0x00
1752 #define HV_MSIVALID_VALID 0x01
1754 #define HV_PCIE_MSGTYPE_PME_MSG 0x18
1755 #define HV_PCIE_MSGTYPE_PME_ACK_MSG 0x1b
1756 #define HV_PCIE_MSGTYPE_CORR_MSG 0x30
1757 #define HV_PCIE_MSGTYPE_NONFATAL_MSG 0x31
1758 #define HV_PCIE_MSGTYPE_FATAL_MSG 0x33
1760 #define HV_MSG_INVALID 0x00
1761 #define HV_MSG_VALID 0x01
1764 * TRAP: HV_FAST_TRAP
1765 * FUNCTION: HV_FAST_PCI_MSIQ_CONF
1768 * ARG2: real address
1769 * ARG3: number of entries
1771 * ERRORS: EINVAL Invalid devhandle, msiqid or nentries
1772 * EBADALIGN Improperly aligned real address
1773 * ENORADDR Bad real address
1775 * Configure the MSI queue given by the devhandle and msiqid arguments,
1776 * and to be placed at the given real address and be of the given
1777 * number of entries. The real address must be aligned exactly to match
1778 * the queue size. Each queue entry is 64-bytes long, so f.e. a 32 entry
1779 * queue must be aligned on a 2048 byte real address boundary. The MSI-EQ
1780 * Head and Tail are initialized so that the MSI-EQ is 'empty'.
1782 * Implementation Note: Certain implementations have fixed sized queues. In
1783 * that case, number of entries must contain the correct
1786 #define HV_FAST_PCI_MSIQ_CONF 0xc0
1789 * TRAP: HV_FAST_TRAP
1790 * FUNCTION: HV_FAST_PCI_MSIQ_INFO
1794 * RET1: real address
1795 * RET2: number of entries
1796 * ERRORS: EINVAL Invalid devhandle or msiqid
1798 * Return the configuration information for the MSI queue described
1799 * by the given devhandle and msiqid. The base address of the queue
1800 * is returned in ARG1 and the number of entries is returned in ARG2.
1801 * If the queue is unconfigured, the real address is undefined and the
1802 * number of entries will be returned as zero.
1804 #define HV_FAST_PCI_MSIQ_INFO 0xc1
1806 /* pci_msiq_getvalid()
1807 * TRAP: HV_FAST_TRAP
1808 * FUNCTION: HV_FAST_PCI_MSIQ_GETVALID
1812 * RET1: msiqvalid (HV_MSIQ_VALID or HV_MSIQ_INVALID)
1813 * ERRORS: EINVAL Invalid devhandle or msiqid
1815 * Get the valid state of the MSI-EQ described by the given devhandle and
1818 #define HV_FAST_PCI_MSIQ_GETVALID 0xc2
1820 /* pci_msiq_setvalid()
1821 * TRAP: HV_FAST_TRAP
1822 * FUNCTION: HV_FAST_PCI_MSIQ_SETVALID
1825 * ARG2: msiqvalid (HV_MSIQ_VALID or HV_MSIQ_INVALID)
1827 * ERRORS: EINVAL Invalid devhandle or msiqid or msiqvalid
1828 * value or MSI EQ is uninitialized
1830 * Set the valid state of the MSI-EQ described by the given devhandle and
1831 * msiqid to the given msiqvalid.
1833 #define HV_FAST_PCI_MSIQ_SETVALID 0xc3
1835 /* pci_msiq_getstate()
1836 * TRAP: HV_FAST_TRAP
1837 * FUNCTION: HV_FAST_PCI_MSIQ_GETSTATE
1841 * RET1: msiqstate (HV_MSIQSTATE_IDLE or HV_MSIQSTATE_ERROR)
1842 * ERRORS: EINVAL Invalid devhandle or msiqid
1844 * Get the state of the MSI-EQ described by the given devhandle and
1847 #define HV_FAST_PCI_MSIQ_GETSTATE 0xc4
1849 /* pci_msiq_getvalid()
1850 * TRAP: HV_FAST_TRAP
1851 * FUNCTION: HV_FAST_PCI_MSIQ_GETVALID
1854 * ARG2: msiqstate (HV_MSIQSTATE_IDLE or HV_MSIQSTATE_ERROR)
1856 * ERRORS: EINVAL Invalid devhandle or msiqid or msiqstate
1857 * value or MSI EQ is uninitialized
1859 * Set the state of the MSI-EQ described by the given devhandle and
1860 * msiqid to the given msiqvalid.
1862 #define HV_FAST_PCI_MSIQ_SETSTATE 0xc5
1864 /* pci_msiq_gethead()
1865 * TRAP: HV_FAST_TRAP
1866 * FUNCTION: HV_FAST_PCI_MSIQ_GETHEAD
1871 * ERRORS: EINVAL Invalid devhandle or msiqid
1873 * Get the current MSI EQ queue head for the MSI-EQ described by the
1874 * given devhandle and msiqid.
1876 #define HV_FAST_PCI_MSIQ_GETHEAD 0xc6
1878 /* pci_msiq_sethead()
1879 * TRAP: HV_FAST_TRAP
1880 * FUNCTION: HV_FAST_PCI_MSIQ_SETHEAD
1885 * ERRORS: EINVAL Invalid devhandle or msiqid or msiqhead,
1886 * or MSI EQ is uninitialized
1888 * Set the current MSI EQ queue head for the MSI-EQ described by the
1889 * given devhandle and msiqid.
1891 #define HV_FAST_PCI_MSIQ_SETHEAD 0xc7
1893 /* pci_msiq_gettail()
1894 * TRAP: HV_FAST_TRAP
1895 * FUNCTION: HV_FAST_PCI_MSIQ_GETTAIL
1900 * ERRORS: EINVAL Invalid devhandle or msiqid
1902 * Get the current MSI EQ queue tail for the MSI-EQ described by the
1903 * given devhandle and msiqid.
1905 #define HV_FAST_PCI_MSIQ_GETTAIL 0xc8
1907 /* pci_msi_getvalid()
1908 * TRAP: HV_FAST_TRAP
1909 * FUNCTION: HV_FAST_PCI_MSI_GETVALID
1913 * RET1: msivalidstate
1914 * ERRORS: EINVAL Invalid devhandle or msinum
1916 * Get the current valid/enabled state for the MSI defined by the
1917 * given devhandle and msinum.
1919 #define HV_FAST_PCI_MSI_GETVALID 0xc9
1921 /* pci_msi_setvalid()
1922 * TRAP: HV_FAST_TRAP
1923 * FUNCTION: HV_FAST_PCI_MSI_SETVALID
1926 * ARG2: msivalidstate
1928 * ERRORS: EINVAL Invalid devhandle or msinum or msivalidstate
1930 * Set the current valid/enabled state for the MSI defined by the
1931 * given devhandle and msinum.
1933 #define HV_FAST_PCI_MSI_SETVALID 0xca
1935 /* pci_msi_getmsiq()
1936 * TRAP: HV_FAST_TRAP
1937 * FUNCTION: HV_FAST_PCI_MSI_GETMSIQ
1942 * ERRORS: EINVAL Invalid devhandle or msinum or MSI is unbound
1944 * Get the MSI EQ that the MSI defined by the given devhandle and
1945 * msinum is bound to.
1947 #define HV_FAST_PCI_MSI_GETMSIQ 0xcb
1949 /* pci_msi_setmsiq()
1950 * TRAP: HV_FAST_TRAP
1951 * FUNCTION: HV_FAST_PCI_MSI_SETMSIQ
1957 * ERRORS: EINVAL Invalid devhandle or msinum or msiqid
1959 * Set the MSI EQ that the MSI defined by the given devhandle and
1960 * msinum is bound to.
1962 #define HV_FAST_PCI_MSI_SETMSIQ 0xcc
1964 /* pci_msi_getstate()
1965 * TRAP: HV_FAST_TRAP
1966 * FUNCTION: HV_FAST_PCI_MSI_GETSTATE
1971 * ERRORS: EINVAL Invalid devhandle or msinum
1973 * Get the state of the MSI defined by the given devhandle and msinum.
1974 * If not initialized, return HV_MSISTATE_IDLE.
1976 #define HV_FAST_PCI_MSI_GETSTATE 0xcd
1978 /* pci_msi_setstate()
1979 * TRAP: HV_FAST_TRAP
1980 * FUNCTION: HV_FAST_PCI_MSI_SETSTATE
1985 * ERRORS: EINVAL Invalid devhandle or msinum or msistate
1987 * Set the state of the MSI defined by the given devhandle and msinum.
1989 #define HV_FAST_PCI_MSI_SETSTATE 0xce
1991 /* pci_msg_getmsiq()
1992 * TRAP: HV_FAST_TRAP
1993 * FUNCTION: HV_FAST_PCI_MSG_GETMSIQ
1998 * ERRORS: EINVAL Invalid devhandle or msgtype
2000 * Get the MSI EQ of the MSG defined by the given devhandle and msgtype.
2002 #define HV_FAST_PCI_MSG_GETMSIQ 0xd0
2004 /* pci_msg_setmsiq()
2005 * TRAP: HV_FAST_TRAP
2006 * FUNCTION: HV_FAST_PCI_MSG_SETMSIQ
2011 * ERRORS: EINVAL Invalid devhandle, msgtype, or msiqid
2013 * Set the MSI EQ of the MSG defined by the given devhandle and msgtype.
2015 #define HV_FAST_PCI_MSG_SETMSIQ 0xd1
2017 /* pci_msg_getvalid()
2018 * TRAP: HV_FAST_TRAP
2019 * FUNCTION: HV_FAST_PCI_MSG_GETVALID
2023 * RET1: msgvalidstate
2024 * ERRORS: EINVAL Invalid devhandle or msgtype
2026 * Get the valid/enabled state of the MSG defined by the given
2027 * devhandle and msgtype.
2029 #define HV_FAST_PCI_MSG_GETVALID 0xd2
2031 /* pci_msg_setvalid()
2032 * TRAP: HV_FAST_TRAP
2033 * FUNCTION: HV_FAST_PCI_MSG_SETVALID
2036 * ARG2: msgvalidstate
2038 * ERRORS: EINVAL Invalid devhandle or msgtype or msgvalidstate
2040 * Set the valid/enabled state of the MSG defined by the given
2041 * devhandle and msgtype.
2043 #define HV_FAST_PCI_MSG_SETVALID 0xd3
2045 /* Performance counter services. */
2047 #define HV_PERF_JBUS_PERF_CTRL_REG 0x00
2048 #define HV_PERF_JBUS_PERF_CNT_REG 0x01
2049 #define HV_PERF_DRAM_PERF_CTRL_REG_0 0x02
2050 #define HV_PERF_DRAM_PERF_CNT_REG_0 0x03
2051 #define HV_PERF_DRAM_PERF_CTRL_REG_1 0x04
2052 #define HV_PERF_DRAM_PERF_CNT_REG_1 0x05
2053 #define HV_PERF_DRAM_PERF_CTRL_REG_2 0x06
2054 #define HV_PERF_DRAM_PERF_CNT_REG_2 0x07
2055 #define HV_PERF_DRAM_PERF_CTRL_REG_3 0x08
2056 #define HV_PERF_DRAM_PERF_CNT_REG_3 0x09
2059 * TRAP: HV_FAST_TRAP
2060 * FUNCTION: HV_FAST_GET_PERFREG
2061 * ARG0: performance reg number
2063 * RET1: performance reg value
2064 * ERRORS: EINVAL Invalid performance register number
2065 * ENOACCESS No access allowed to performance counters
2067 * Read the value of the given DRAM/JBUS performance counter/control register.
2069 #define HV_FAST_GET_PERFREG 0x100
2072 * TRAP: HV_FAST_TRAP
2073 * FUNCTION: HV_FAST_SET_PERFREG
2074 * ARG0: performance reg number
2075 * ARG1: performance reg value
2077 * ERRORS: EINVAL Invalid performance register number
2078 * ENOACCESS No access allowed to performance counters
2080 * Write the given performance reg value to the given DRAM/JBUS
2081 * performance counter/control register.
2083 #define HV_FAST_SET_PERFREG 0x101
2085 /* MMU statistics services.
2087 * The hypervisor maintains MMU statistics and privileged code provides
2088 * a buffer where these statistics can be collected. It is continually
2089 * updated once configured. The layout is as follows:
2091 #ifndef __ASSEMBLY__
2092 struct hv_mmu_statistics {
2093 unsigned long immu_tsb_hits_ctx0_8k_tte;
2094 unsigned long immu_tsb_ticks_ctx0_8k_tte;
2095 unsigned long immu_tsb_hits_ctx0_64k_tte;
2096 unsigned long immu_tsb_ticks_ctx0_64k_tte;
2097 unsigned long __reserved1[2];
2098 unsigned long immu_tsb_hits_ctx0_4mb_tte;
2099 unsigned long immu_tsb_ticks_ctx0_4mb_tte;
2100 unsigned long __reserved2[2];
2101 unsigned long immu_tsb_hits_ctx0_256mb_tte;
2102 unsigned long immu_tsb_ticks_ctx0_256mb_tte;
2103 unsigned long __reserved3[4];
2104 unsigned long immu_tsb_hits_ctxnon0_8k_tte;
2105 unsigned long immu_tsb_ticks_ctxnon0_8k_tte;
2106 unsigned long immu_tsb_hits_ctxnon0_64k_tte;
2107 unsigned long immu_tsb_ticks_ctxnon0_64k_tte;
2108 unsigned long __reserved4[2];
2109 unsigned long immu_tsb_hits_ctxnon0_4mb_tte;
2110 unsigned long immu_tsb_ticks_ctxnon0_4mb_tte;
2111 unsigned long __reserved5[2];
2112 unsigned long immu_tsb_hits_ctxnon0_256mb_tte;
2113 unsigned long immu_tsb_ticks_ctxnon0_256mb_tte;
2114 unsigned long __reserved6[4];
2115 unsigned long dmmu_tsb_hits_ctx0_8k_tte;
2116 unsigned long dmmu_tsb_ticks_ctx0_8k_tte;
2117 unsigned long dmmu_tsb_hits_ctx0_64k_tte;
2118 unsigned long dmmu_tsb_ticks_ctx0_64k_tte;
2119 unsigned long __reserved7[2];
2120 unsigned long dmmu_tsb_hits_ctx0_4mb_tte;
2121 unsigned long dmmu_tsb_ticks_ctx0_4mb_tte;
2122 unsigned long __reserved8[2];
2123 unsigned long dmmu_tsb_hits_ctx0_256mb_tte;
2124 unsigned long dmmu_tsb_ticks_ctx0_256mb_tte;
2125 unsigned long __reserved9[4];
2126 unsigned long dmmu_tsb_hits_ctxnon0_8k_tte;
2127 unsigned long dmmu_tsb_ticks_ctxnon0_8k_tte;
2128 unsigned long dmmu_tsb_hits_ctxnon0_64k_tte;
2129 unsigned long dmmu_tsb_ticks_ctxnon0_64k_tte;
2130 unsigned long __reserved10[2];
2131 unsigned long dmmu_tsb_hits_ctxnon0_4mb_tte;
2132 unsigned long dmmu_tsb_ticks_ctxnon0_4mb_tte;
2133 unsigned long __reserved11[2];
2134 unsigned long dmmu_tsb_hits_ctxnon0_256mb_tte;
2135 unsigned long dmmu_tsb_ticks_ctxnon0_256mb_tte;
2136 unsigned long __reserved12[4];
2141 * TRAP: HV_FAST_TRAP
2142 * FUNCTION: HV_FAST_MMUSTAT_CONF
2143 * ARG0: real address
2145 * RET1: real address
2146 * ERRORS: ENORADDR Invalid real address
2147 * EBADALIGN Real address not aligned on 64-byte boundary
2148 * EBADTRAP API not supported on this processor
2150 * Enable MMU statistic gathering using the buffer at the given real
2151 * address on the current virtual CPU. The new buffer real address
2152 * is given in ARG1, and the previously specified buffer real address
2153 * is returned in RET1, or is returned as zero for the first invocation.
2155 * If the passed in real address argument is zero, this will disable
2156 * MMU statistic collection on the current virtual CPU. If an error is
2157 * returned then no statistics are collected.
2159 * The buffer contents should be initialized to all zeros before being
2160 * given to the hypervisor or else the statistics will be meaningless.
2162 #define HV_FAST_MMUSTAT_CONF 0x102
2165 * TRAP: HV_FAST_TRAP
2166 * FUNCTION: HV_FAST_MMUSTAT_INFO
2168 * RET1: real address
2169 * ERRORS: EBADTRAP API not supported on this processor
2171 * Return the current state and real address of the currently configured
2172 * MMU statistics buffer on the current virtual CPU.
2174 #define HV_FAST_MMUSTAT_INFO 0x103
2176 /* Function numbers for HV_CORE_TRAP. */
2177 #define HV_CORE_SET_VER 0x00
2178 #define HV_CORE_PUTCHAR 0x01
2179 #define HV_CORE_EXIT 0x02
2180 #define HV_CORE_GET_VER 0x03
2182 /* Hypervisor API groups for use with HV_CORE_SET_VER and
2185 #define HV_GRP_SUN4V 0x0000
2186 #define HV_GRP_CORE 0x0001
2187 #define HV_GRP_INTR 0x0002
2188 #define HV_GRP_SOFT_STATE 0x0003
2189 #define HV_GRP_PCI 0x0100
2190 #define HV_GRP_LDOM 0x0101
2191 #define HV_GRP_SVC_CHAN 0x0102
2192 #define HV_GRP_NCS 0x0103
2193 #define HV_GRP_NIAG_PERF 0x0200
2194 #define HV_GRP_FIRE_PERF 0x0201
2195 #define HV_GRP_DIAG 0x0300
2197 #ifndef __ASSEMBLY__
2198 extern unsigned long sun4v_get_version(unsigned long group,
2199 unsigned long *major,
2200 unsigned long *minor);
2201 extern unsigned long sun4v_set_version(unsigned long group,
2202 unsigned long major,
2203 unsigned long minor,
2204 unsigned long *actual_minor);
2206 extern int sun4v_hvapi_register(unsigned long group, unsigned long major,
2207 unsigned long *minor);
2208 extern void sun4v_hvapi_unregister(unsigned long group);
2209 extern int sun4v_hvapi_get(unsigned long group,
2210 unsigned long *major,
2211 unsigned long *minor);
2212 extern void sun4v_hvapi_init(void);
2215 #endif /* !(_SPARC64_HYPERVISOR_H) */