1 #ifndef _SPARC64_HYPERVISOR_H
2 #define _SPARC64_HYPERVISOR_H
4 /* Sun4v hypervisor interfaces and defines.
6 * Hypervisor calls are made via traps to software traps number 0x80
7 * and above. Registers %o0 to %o5 serve as argument, status, and
8 * return value registers.
10 * There are two kinds of these traps. First there are the normal
11 * "fast traps" which use software trap 0x80 and encode the function
12 * to invoke by number in register %o5. Argument and return value
13 * handling is as follows:
15 * -----------------------------------------------
16 * | %o5 | function number | undefined |
17 * | %o0 | argument 0 | return status |
18 * | %o1 | argument 1 | return value 1 |
19 * | %o2 | argument 2 | return value 2 |
20 * | %o3 | argument 3 | return value 3 |
21 * | %o4 | argument 4 | return value 4 |
22 * -----------------------------------------------
24 * The second type are "hyper-fast traps" which encode the function
25 * number in the software trap number itself. So these use trap
26 * numbers > 0x80. The register usage for hyper-fast traps is as
29 * -----------------------------------------------
30 * | %o0 | argument 0 | return status |
31 * | %o1 | argument 1 | return value 1 |
32 * | %o2 | argument 2 | return value 2 |
33 * | %o3 | argument 3 | return value 3 |
34 * | %o4 | argument 4 | return value 4 |
35 * -----------------------------------------------
37 * Registers providing explicit arguments to the hypervisor calls
38 * are volatile across the call. Upon return their values are
39 * undefined unless explicitly specified as containing a particular
40 * return value by the specific call. The return status is always
41 * returned in register %o0, zero indicates a successful execution of
42 * the hypervisor call and other values indicate an error status as
43 * defined below. So, for example, if a hyper-fast trap takes
44 * arguments 0, 1, and 2, then %o0, %o1, and %o2 are volatile across
45 * the call and %o3, %o4, and %o5 would be preserved.
47 * If the hypervisor trap is invalid, or the fast trap function number
48 * is invalid, HV_EBADTRAP will be returned in %o0. Also, all 64-bits
49 * of the argument and return values are significant.
53 #define HV_FAST_TRAP 0x80
54 #define HV_MMU_MAP_ADDR_TRAP 0x83
55 #define HV_MMU_UNMAP_ADDR_TRAP 0x84
56 #define HV_TTRACE_ADDENTRY_TRAP 0x85
57 #define HV_CORE_TRAP 0xff
60 #define HV_EOK 0 /* Successful return */
61 #define HV_ENOCPU 1 /* Invalid CPU id */
62 #define HV_ENORADDR 2 /* Invalid real address */
63 #define HV_ENOINTR 3 /* Invalid interrupt id */
64 #define HV_EBADPGSZ 4 /* Invalid pagesize encoding */
65 #define HV_EBADTSB 5 /* Invalid TSB description */
66 #define HV_EINVAL 6 /* Invalid argument */
67 #define HV_EBADTRAP 7 /* Invalid function number */
68 #define HV_EBADALIGN 8 /* Invalid address alignment */
69 #define HV_EWOULDBLOCK 9 /* Cannot complete w/o blocking */
70 #define HV_ENOACCESS 10 /* No access to resource */
71 #define HV_EIO 11 /* I/O error */
72 #define HV_ECPUERROR 12 /* CPU in error state */
73 #define HV_ENOTSUPPORTED 13 /* Function not supported */
74 #define HV_ENOMAP 14 /* No mapping found */
75 #define HV_ETOOMANY 15 /* Too many items specified */
79 * FUNCTION: HV_FAST_MACH_EXIT
81 * ERRORS: This service does not return.
83 * Stop all CPUs in the virtual domain and place them into the stopped
84 * state. The 64-bit exit code may be passed to a service entity as
85 * the domain's exit status. On systems without a service entity, the
86 * domain will undergo a reset, and the boot firmware will be
89 * This function will never return to the guest that invokes it.
91 * Note: By convention an exit code of zero denotes a successful exit by
92 * the guest code. A non-zero exit code denotes a guest specific
96 #define HV_FAST_MACH_EXIT 0x00
98 /* Domain services. */
102 * FUNCTION: HV_FAST_MACH_DESC
107 * ERRORS: HV_EBADALIGN Buffer is badly aligned
108 * HV_ENORADDR Buffer is to an illegal real address.
109 * HV_EINVAL Buffer length is too small for complete
110 * machine description.
112 * Copy the most current machine description into the buffer indicated
113 * by the real address in ARG0. The buffer provided must be 16 byte
114 * aligned. Upon success or HV_EINVAL, this service returns the
115 * actual size of the machine description in the RET1 return value.
117 * Note: A method of determining the appropriate buffer size for the
118 * machine description is to first call this service with a buffer
121 #define HV_FAST_MACH_DESC 0x01
125 * FUNCTION: HV_FAST_MACH_SIR
126 * ERRORS: This service does not return.
128 * Perform a software initiated reset of the virtual machine domain.
129 * All CPUs are captured as soon as possible, all hardware devices are
130 * returned to the entry default state, and the domain is restarted at
131 * the SIR (trap type 0x04) real trap table (RTBA) entry point on one
132 * of the CPUs. The single CPU restarted is selected as determined by
133 * platform specific policy. Memory is preserved across this
136 #define HV_FAST_MACH_SIR 0x02
138 /* mach_set_soft_state()
140 * FUNCTION: HV_FAST_MACH_SET_SOFT_STATE
141 * ARG0: software state
142 * ARG1: software state description pointer
144 * ERRORS: EINVAL software state not valid or software state
145 * description is not NULL terminated
146 * ENORADDR software state description pointer is not a
148 * EBADALIGNED software state description is not correctly
151 * This allows the guest to report it's soft state to the hypervisor. There
152 * are two primary components to this state. The first part states whether
153 * the guest software is running or not. The second containts optional
154 * details specific to the software.
156 * The software state argument is defined below in HV_SOFT_STATE_*, and
157 * indicates whether the guest is operating normally or in a transitional
160 * The software state description argument is a real address of a data buffer
161 * of size 32-bytes aligned on a 32-byte boundary. It is treated as a NULL
162 * terminated 7-bit ASCII string of up to 31 characters not including the
165 #define HV_FAST_MACH_SET_SOFT_STATE 0x03
166 #define HV_SOFT_STATE_NORMAL 0x01
167 #define HV_SOFT_STATE_TRANSITION 0x02
169 /* mach_get_soft_state()
171 * FUNCTION: HV_FAST_MACH_GET_SOFT_STATE
172 * ARG0: software state description pointer
174 * RET1: software state
175 * ERRORS: ENORADDR software state description pointer is not a
177 * EBADALIGNED software state description is not correctly
180 * Retrieve the current value of the guest's software state. The rules
181 * for the software state pointer are the same as for mach_set_soft_state()
184 #define HV_FAST_MACH_GET_SOFT_STATE 0x04
188 * CPUs represent devices that can execute software threads. A single
189 * chip that contains multiple cores or strands is represented as
190 * multiple CPUs with unique CPU identifiers. CPUs are exported to
191 * OBP via the machine description (and to the OS via the OBP device
192 * tree). CPUs are always in one of three states: stopped, running,
195 * A CPU ID is a pre-assigned 16-bit value that uniquely identifies a
196 * CPU within a logical domain. Operations that are to be performed
197 * on multiple CPUs specify them via a CPU list. A CPU list is an
198 * array in real memory, of which each 16-bit word is a CPU ID. CPU
199 * lists are passed through the API as two arguments. The first is
200 * the number of entries (16-bit words) in the CPU list, and the
201 * second is the (real address) pointer to the CPU ID list.
206 * FUNCTION: HV_FAST_CPU_START
212 * ERRORS: ENOCPU Invalid CPU ID
213 * EINVAL Target CPU ID is not in the stopped state
214 * ENORADDR Invalid PC or RTBA real address
215 * EBADALIGN Unaligned PC or unaligned RTBA
216 * EWOULDBLOCK Starting resources are not available
218 * Start CPU with given CPU ID with PC in %pc and with a real trap
219 * base address value of RTBA. The indicated CPU must be in the
220 * stopped state. The supplied RTBA must be aligned on a 256 byte
221 * boundary. On successful completion, the specified CPU will be in
222 * the running state and will be supplied with "target ARG0" in %o0
225 #define HV_FAST_CPU_START 0x10
229 * FUNCTION: HV_FAST_CPU_STOP
232 * ERRORS: ENOCPU Invalid CPU ID
233 * EINVAL Target CPU ID is the current cpu
234 * EINVAL Target CPU ID is not in the running state
235 * EWOULDBLOCK Stopping resources are not available
236 * ENOTSUPPORTED Not supported on this platform
238 * The specified CPU is stopped. The indicated CPU must be in the
239 * running state. On completion, it will be in the stopped state. It
240 * is not legal to stop the current CPU.
242 * Note: As this service cannot be used to stop the current cpu, this service
243 * may not be used to stop the last running CPU in a domain. To stop
244 * and exit a running domain, a guest must use the mach_exit() service.
246 #define HV_FAST_CPU_STOP 0x11
250 * FUNCTION: HV_FAST_CPU_YIELD
252 * ERRORS: No possible error.
254 * Suspend execution on the current CPU. Execution will resume when
255 * an interrupt (device, %stick_compare, or cross-call) is targeted to
256 * the CPU. On some CPUs, this API may be used by the hypervisor to
257 * save power by disabling hardware strands.
259 #define HV_FAST_CPU_YIELD 0x12
264 * FUNCTION: HV_FAST_CPU_QCONF
266 * ARG1: base real address
267 * ARG2: number of entries
269 * ERRORS: ENORADDR Invalid base real address
270 * EINVAL Invalid queue or number of entries is less
271 * than 2 or too large.
272 * EBADALIGN Base real address is not correctly aligned
275 * Configure the given queue to be placed at the given base real
276 * address, with the given number of entries. The number of entries
277 * must be a power of 2. The base real address must be aligned
278 * exactly to match the queue size. Each queue entry is 64 bytes
279 * long, so for example a 32 entry queue must be aligned on a 2048
280 * byte real address boundary.
282 * The specified queue is unconfigured if the number of entries is given
285 * For the current version of this API service, the argument queue is defined
289 * ----- -------------------------
290 * 0x3c cpu mondo queue
291 * 0x3d device mondo queue
292 * 0x3e resumable error queue
293 * 0x3f non-resumable error queue
295 * Note: The maximum number of entries for each queue for a specific cpu may
296 * be determined from the machine description.
298 #define HV_FAST_CPU_QCONF 0x14
299 #define HV_CPU_QUEUE_CPU_MONDO 0x3c
300 #define HV_CPU_QUEUE_DEVICE_MONDO 0x3d
301 #define HV_CPU_QUEUE_RES_ERROR 0x3e
302 #define HV_CPU_QUEUE_NONRES_ERROR 0x3f
306 * FUNCTION: HV_FAST_CPU_QINFO
309 * RET1: base real address
310 * RET1: number of entries
311 * ERRORS: EINVAL Invalid queue
313 * Return the configuration info for the given queue. The base real
314 * address and number of entries of the defined queue are returned.
315 * The queue argument values are the same as for cpu_qconf() above.
317 * If the specified queue is a valid queue number, but no queue has
318 * been defined, the number of entries will be set to zero and the
319 * base real address returned is undefined.
321 #define HV_FAST_CPU_QINFO 0x15
325 * FUNCTION: HV_FAST_CPU_MONDO_SEND
327 * ARG2: data real address
329 * ERRORS: EBADALIGN Mondo data is not 64-byte aligned or CPU list
330 * is not 2-byte aligned.
331 * ENORADDR Invalid data mondo address, or invalid cpu list
333 * ENOCPU Invalid cpu in CPU list
334 * EWOULDBLOCK Some or all of the listed CPUs did not receive
336 * EINVAL CPU list includes caller's CPU ID
338 * Send a mondo interrupt to the CPUs in the given CPU list with the
339 * 64-bytes at the given data real address. The data must be 64-byte
340 * aligned. The mondo data will be delivered to the cpu_mondo queues
341 * of the recipient CPUs.
343 * In all cases, error or not, the CPUs in the CPU list to which the
344 * mondo has been successfully delivered will be indicated by having
345 * their entry in CPU list updated with the value 0xffff.
347 #define HV_FAST_CPU_MONDO_SEND 0x42
351 * FUNCTION: HV_FAST_CPU_MYID
354 * ERRORS: No errors defined.
356 * Return the hypervisor ID handle for the current CPU. Use by a
357 * virtual CPU to discover it's own identity.
359 #define HV_FAST_CPU_MYID 0x16
363 * FUNCTION: HV_FAST_CPU_STATE
367 * ERRORS: ENOCPU Invalid CPU ID
369 * Retrieve the current state of the CPU with the given CPU ID.
371 #define HV_FAST_CPU_STATE 0x17
372 #define HV_CPU_STATE_STOPPED 0x01
373 #define HV_CPU_STATE_RUNNING 0x02
374 #define HV_CPU_STATE_ERROR 0x03
378 * FUNCTION: HV_FAST_CPU_SET_RTBA
381 * RET1: previous RTBA
382 * ERRORS: ENORADDR Invalid RTBA real address
383 * EBADALIGN RTBA is incorrectly aligned for a trap table
385 * Set the real trap base address of the local cpu to the given RTBA.
386 * The supplied RTBA must be aligned on a 256 byte boundary. Upon
387 * success the previous value of the RTBA is returned in RET1.
389 * Note: This service does not affect %tba
391 #define HV_FAST_CPU_SET_RTBA 0x18
395 * FUNCTION: HV_FAST_CPU_GET_RTBA
397 * RET1: previous RTBA
398 * ERRORS: No possible error.
400 * Returns the current value of RTBA in RET1.
402 #define HV_FAST_CPU_GET_RTBA 0x19
406 * Layout of a TSB description for mmu_tsb_ctx{,non}0() calls.
409 struct hv_tsb_descr {
410 unsigned short pgsz_idx;
411 unsigned short assoc;
412 unsigned int num_ttes; /* in TTEs */
413 unsigned int ctx_idx;
414 unsigned int pgsz_mask;
415 unsigned long tsb_base;
419 #define HV_TSB_DESCR_PGSZ_IDX_OFFSET 0x00
420 #define HV_TSB_DESCR_ASSOC_OFFSET 0x02
421 #define HV_TSB_DESCR_NUM_TTES_OFFSET 0x04
422 #define HV_TSB_DESCR_CTX_IDX_OFFSET 0x08
423 #define HV_TSB_DESCR_PGSZ_MASK_OFFSET 0x0c
424 #define HV_TSB_DESCR_TSB_BASE_OFFSET 0x10
425 #define HV_TSB_DESCR_RESV_OFFSET 0x18
427 /* Page size bitmask. */
428 #define HV_PGSZ_MASK_8K (1 << 0)
429 #define HV_PGSZ_MASK_64K (1 << 1)
430 #define HV_PGSZ_MASK_512K (1 << 2)
431 #define HV_PGSZ_MASK_4MB (1 << 3)
432 #define HV_PGSZ_MASK_32MB (1 << 4)
433 #define HV_PGSZ_MASK_256MB (1 << 5)
434 #define HV_PGSZ_MASK_2GB (1 << 6)
435 #define HV_PGSZ_MASK_16GB (1 << 7)
437 /* Page size index. The value given in the TSB descriptor must correspond
438 * to the smallest page size specified in the pgsz_mask page size bitmask.
440 #define HV_PGSZ_IDX_8K 0
441 #define HV_PGSZ_IDX_64K 1
442 #define HV_PGSZ_IDX_512K 2
443 #define HV_PGSZ_IDX_4MB 3
444 #define HV_PGSZ_IDX_32MB 4
445 #define HV_PGSZ_IDX_256MB 5
446 #define HV_PGSZ_IDX_2GB 6
447 #define HV_PGSZ_IDX_16GB 7
449 /* MMU fault status area.
451 * MMU related faults have their status and fault address information
452 * placed into a memory region made available by privileged code. Each
453 * virtual processor must make a mmu_fault_area_conf() call to tell the
454 * hypervisor where that processor's fault status should be stored.
456 * The fault status block is a multiple of 64-bytes and must be aligned
457 * on a 64-byte boundary.
460 struct hv_fault_status {
461 unsigned long i_fault_type;
462 unsigned long i_fault_addr;
463 unsigned long i_fault_ctx;
464 unsigned long i_reserved[5];
465 unsigned long d_fault_type;
466 unsigned long d_fault_addr;
467 unsigned long d_fault_ctx;
468 unsigned long d_reserved[5];
471 #define HV_FAULT_I_TYPE_OFFSET 0x00
472 #define HV_FAULT_I_ADDR_OFFSET 0x08
473 #define HV_FAULT_I_CTX_OFFSET 0x10
474 #define HV_FAULT_D_TYPE_OFFSET 0x40
475 #define HV_FAULT_D_ADDR_OFFSET 0x48
476 #define HV_FAULT_D_CTX_OFFSET 0x50
478 #define HV_FAULT_TYPE_FAST_MISS 1
479 #define HV_FAULT_TYPE_FAST_PROT 2
480 #define HV_FAULT_TYPE_MMU_MISS 3
481 #define HV_FAULT_TYPE_INV_RA 4
482 #define HV_FAULT_TYPE_PRIV_VIOL 5
483 #define HV_FAULT_TYPE_PROT_VIOL 6
484 #define HV_FAULT_TYPE_NFO 7
485 #define HV_FAULT_TYPE_NFO_SEFF 8
486 #define HV_FAULT_TYPE_INV_VA 9
487 #define HV_FAULT_TYPE_INV_ASI 10
488 #define HV_FAULT_TYPE_NC_ATOMIC 11
489 #define HV_FAULT_TYPE_PRIV_ACT 12
490 #define HV_FAULT_TYPE_RESV1 13
491 #define HV_FAULT_TYPE_UNALIGNED 14
492 #define HV_FAULT_TYPE_INV_PGSZ 15
493 /* Values 16 --> -2 are reserved. */
494 #define HV_FAULT_TYPE_MULTIPLE -1
496 /* Flags argument for mmu_{map,unmap}_addr(), mmu_demap_{page,context,all}(),
497 * and mmu_{map,unmap}_perm_addr().
499 #define HV_MMU_DMMU 0x01
500 #define HV_MMU_IMMU 0x02
501 #define HV_MMU_ALL (HV_MMU_DMMU | HV_MMU_IMMU)
504 * TRAP: HV_MMU_MAP_ADDR_TRAP
505 * ARG0: virtual address
508 * ARG3: flags (HV_MMU_{IMMU,DMMU})
509 * ERRORS: EINVAL Invalid virtual address, mmu context, or flags
510 * EBADPGSZ Invalid page size value
511 * ENORADDR Invalid real address in TTE
513 * Create a non-permanent mapping using the given TTE, virtual
514 * address, and mmu context. The flags argument determines which
515 * (data, or instruction, or both) TLB the mapping gets loaded into.
517 * The behavior is undefined if the valid bit is clear in the TTE.
519 * Note: This API call is for privileged code to specify temporary translation
520 * mappings without the need to create and manage a TSB.
524 * TRAP: HV_MMU_UNMAP_ADDR_TRAP
525 * ARG0: virtual address
527 * ARG2: flags (HV_MMU_{IMMU,DMMU})
528 * ERRORS: EINVAL Invalid virtual address, mmu context, or flags
530 * Demaps the given virtual address in the given mmu context on this
531 * CPU. This function is intended to be used to demap pages mapped
532 * with mmu_map_addr. This service is equivalent to invoking
533 * mmu_demap_page() with only the current CPU in the CPU list. The
534 * flags argument determines which (data, or instruction, or both) TLB
535 * the mapping gets unmapped from.
537 * Attempting to perform an unmap operation for a previously defined
538 * permanent mapping will have undefined results.
543 * FUNCTION: HV_FAST_MMU_TSB_CTX0
544 * ARG0: number of TSB descriptions
545 * ARG1: TSB descriptions pointer
547 * ERRORS: ENORADDR Invalid TSB descriptions pointer or
548 * TSB base within a descriptor
549 * EBADALIGN TSB descriptions pointer is not aligned
550 * to an 8-byte boundary, or TSB base
551 * within a descriptor is not aligned for
553 * EBADPGSZ Invalid page size in a TSB descriptor
554 * EBADTSB Invalid associativity or size in a TSB
556 * EINVAL Invalid number of TSB descriptions, or
557 * invalid context index in a TSB
558 * descriptor, or index page size not
559 * equal to smallest page size in page
560 * size bitmask field.
562 * Configures the TSBs for the current CPU for virtual addresses with
563 * context zero. The TSB descriptions pointer is a pointer to an
564 * array of the given number of TSB descriptions.
566 * Note: The maximum number of TSBs available to a virtual CPU is given by the
567 * mmu-max-#tsbs property of the cpu's corresponding "cpu" node in the
568 * machine description.
570 #define HV_FAST_MMU_TSB_CTX0 0x20
574 * FUNCTION: HV_FAST_MMU_TSB_CTXNON0
575 * ARG0: number of TSB descriptions
576 * ARG1: TSB descriptions pointer
578 * ERRORS: Same as for mmu_tsb_ctx0() above.
580 * Configures the TSBs for the current CPU for virtual addresses with
581 * non-zero contexts. The TSB descriptions pointer is a pointer to an
582 * array of the given number of TSB descriptions.
584 * Note: A maximum of 16 TSBs may be specified in the TSB description list.
586 #define HV_FAST_MMU_TSB_CTXNON0 0x21
590 * FUNCTION: HV_FAST_MMU_DEMAP_PAGE
591 * ARG0: reserved, must be zero
592 * ARG1: reserved, must be zero
593 * ARG2: virtual address
595 * ARG4: flags (HV_MMU_{IMMU,DMMU})
597 * ERRORS: EINVAL Invalid virutal address, context, or
599 * ENOTSUPPORTED ARG0 or ARG1 is non-zero
601 * Demaps any page mapping of the given virtual address in the given
602 * mmu context for the current virtual CPU. Any virtually tagged
603 * caches are guaranteed to be kept consistent. The flags argument
604 * determines which TLB (instruction, or data, or both) participate in
607 * ARG0 and ARG1 are both reserved and must be set to zero.
609 #define HV_FAST_MMU_DEMAP_PAGE 0x22
613 * FUNCTION: HV_FAST_MMU_DEMAP_CTX
614 * ARG0: reserved, must be zero
615 * ARG1: reserved, must be zero
617 * ARG3: flags (HV_MMU_{IMMU,DMMU})
619 * ERRORS: EINVAL Invalid context or flags value
620 * ENOTSUPPORTED ARG0 or ARG1 is non-zero
622 * Demaps all non-permanent virtual page mappings previously specified
623 * for the given context for the current virtual CPU. Any virtual
624 * tagged caches are guaranteed to be kept consistent. The flags
625 * argument determines which TLB (instruction, or data, or both)
626 * participate in the operation.
628 * ARG0 and ARG1 are both reserved and must be set to zero.
630 #define HV_FAST_MMU_DEMAP_CTX 0x23
634 * FUNCTION: HV_FAST_MMU_DEMAP_ALL
635 * ARG0: reserved, must be zero
636 * ARG1: reserved, must be zero
637 * ARG2: flags (HV_MMU_{IMMU,DMMU})
639 * ERRORS: EINVAL Invalid flags value
640 * ENOTSUPPORTED ARG0 or ARG1 is non-zero
642 * Demaps all non-permanent virtual page mappings previously specified
643 * for the current virtual CPU. Any virtual tagged caches are
644 * guaranteed to be kept consistent. The flags argument determines
645 * which TLB (instruction, or data, or both) participate in the
648 * ARG0 and ARG1 are both reserved and must be set to zero.
650 #define HV_FAST_MMU_DEMAP_ALL 0x24
652 /* mmu_map_perm_addr()
654 * FUNCTION: HV_FAST_MMU_MAP_PERM_ADDR
655 * ARG0: virtual address
656 * ARG1: reserved, must be zero
658 * ARG3: flags (HV_MMU_{IMMU,DMMU})
660 * ERRORS: EINVAL Invalid virutal address or flags value
661 * EBADPGSZ Invalid page size value
662 * ENORADDR Invalid real address in TTE
663 * ETOOMANY Too many mappings (max of 8 reached)
665 * Create a permanent mapping using the given TTE and virtual address
666 * for context 0 on the calling virtual CPU. A maximum of 8 such
667 * permanent mappings may be specified by privileged code. Mappings
668 * may be removed with mmu_unmap_perm_addr().
670 * The behavior is undefined if a TTE with the valid bit clear is given.
672 * Note: This call is used to specify address space mappings for which
673 * privileged code does not expect to receive misses. For example,
674 * this mechanism can be used to map kernel nucleus code and data.
676 #define HV_FAST_MMU_MAP_PERM_ADDR 0x25
678 /* mmu_fault_area_conf()
680 * FUNCTION: HV_FAST_MMU_FAULT_AREA_CONF
683 * RET1: previous mmu fault area real address
684 * ERRORS: ENORADDR Invalid real address
685 * EBADALIGN Invalid alignment for fault area
687 * Configure the MMU fault status area for the calling CPU. A 64-byte
688 * aligned real address specifies where MMU fault status information
689 * is placed. The return value is the previously specified area, or 0
690 * for the first invocation. Specifying a fault area at real address
693 #define HV_FAST_MMU_FAULT_AREA_CONF 0x26
697 * FUNCTION: HV_FAST_MMU_ENABLE
699 * ARG1: return target address
701 * ERRORS: ENORADDR Invalid real address when disabling
703 * EBADALIGN The return target address is not
704 * aligned to an instruction.
705 * EINVAL The enable flag request the current
706 * operating mode (e.g. disable if already
709 * Enable or disable virtual address translation for the calling CPU
710 * within the virtual machine domain. If the enable flag is zero,
711 * translation is disabled, any non-zero value will enable
714 * When this function returns, the newly selected translation mode
715 * will be active. If the mmu is being enabled, then the return
716 * target address is a virtual address else it is a real address.
718 * Upon successful completion, control will be returned to the given
719 * return target address (ie. the cpu will jump to that address). On
720 * failure, the previous mmu mode remains and the trap simply returns
721 * as normal with the appropriate error code in RET0.
723 #define HV_FAST_MMU_ENABLE 0x27
725 /* mmu_unmap_perm_addr()
727 * FUNCTION: HV_FAST_MMU_UNMAP_PERM_ADDR
728 * ARG0: virtual address
729 * ARG1: reserved, must be zero
730 * ARG2: flags (HV_MMU_{IMMU,DMMU})
732 * ERRORS: EINVAL Invalid virutal address or flags value
733 * ENOMAP Specified mapping was not found
735 * Demaps any permanent page mapping (established via
736 * mmu_map_perm_addr()) at the given virtual address for context 0 on
737 * the current virtual CPU. Any virtual tagged caches are guaranteed
738 * to be kept consistent.
740 #define HV_FAST_MMU_UNMAP_PERM_ADDR 0x28
742 /* mmu_tsb_ctx0_info()
744 * FUNCTION: HV_FAST_MMU_TSB_CTX0_INFO
746 * ARG1: buffer pointer
748 * RET1: number of TSBs
749 * ERRORS: EINVAL Supplied buffer is too small
750 * EBADALIGN The buffer pointer is badly aligned
751 * ENORADDR Invalid real address for buffer pointer
753 * Return the TSB configuration as previous defined by mmu_tsb_ctx0()
754 * into the provided buffer. The size of the buffer is given in ARG1
755 * in terms of the number of TSB description entries.
757 * Upon return, RET1 always contains the number of TSB descriptions
758 * previously configured. If zero TSBs were configured, EOK is
759 * returned with RET1 containing 0.
761 #define HV_FAST_MMU_TSB_CTX0_INFO 0x29
763 /* mmu_tsb_ctxnon0_info()
765 * FUNCTION: HV_FAST_MMU_TSB_CTXNON0_INFO
767 * ARG1: buffer pointer
769 * RET1: number of TSBs
770 * ERRORS: EINVAL Supplied buffer is too small
771 * EBADALIGN The buffer pointer is badly aligned
772 * ENORADDR Invalid real address for buffer pointer
774 * Return the TSB configuration as previous defined by
775 * mmu_tsb_ctxnon0() into the provided buffer. The size of the buffer
776 * is given in ARG1 in terms of the number of TSB description entries.
778 * Upon return, RET1 always contains the number of TSB descriptions
779 * previously configured. If zero TSBs were configured, EOK is
780 * returned with RET1 containing 0.
782 #define HV_FAST_MMU_TSB_CTXNON0_INFO 0x2a
784 /* mmu_fault_area_info()
786 * FUNCTION: HV_FAST_MMU_FAULT_AREA_INFO
788 * RET1: fault area real address
789 * ERRORS: No errors defined.
791 * Return the currently defined MMU fault status area for the current
792 * CPU. The real address of the fault status area is returned in
793 * RET1, or 0 is returned in RET1 if no fault status area is defined.
795 * Note: mmu_fault_area_conf() may be called with the return value (RET1)
796 * from this service if there is a need to save and restore the fault
799 #define HV_FAST_MMU_FAULT_AREA_INFO 0x2b
801 /* Cache and Memory services. */
805 * FUNCTION: HV_FAST_MEM_SCRUB
809 * RET1: length scrubbed
810 * ERRORS: ENORADDR Invalid real address
811 * EBADALIGN Start address or length are not correctly
813 * EINVAL Length is zero
815 * Zero the memory contents in the range real address to real address
816 * plus length minus 1. Also, valid ECC will be generated for that
817 * memory address range. Scrubbing is started at the given real
818 * address, but may not scrub the entire given length. The actual
819 * length scrubbed will be returned in RET1.
821 * The real address and length must be aligned on an 8K boundary, or
822 * contain the start address and length from a sun4v error report.
824 * Note: There are two uses for this function. The first use is to block clear
825 * and initialize memory and the second is to scrub an u ncorrectable
826 * error reported via a resumable or non-resumable trap. The second
827 * use requires the arguments to be equal to the real address and length
828 * provided in a sun4v memory error report.
830 #define HV_FAST_MEM_SCRUB 0x31
834 * FUNCTION: HV_FAST_MEM_SYNC
838 * RET1: length synced
839 * ERRORS: ENORADDR Invalid real address
840 * EBADALIGN Start address or length are not correctly
842 * EINVAL Length is zero
844 * Force the next access within the real address to real address plus
845 * length minus 1 to be fetches from main system memory. Less than
846 * the given length may be synced, the actual amount synced is
847 * returned in RET1. The real address and length must be aligned on
850 #define HV_FAST_MEM_SYNC 0x32
852 /* Time of day services.
854 * The hypervisor maintains the time of day on a per-domain basis.
855 * Changing the time of day in one domain does not affect the time of
856 * day on any other domain.
858 * Time is described by a single unsigned 64-bit word which is the
859 * number of seconds since the UNIX Epoch (00:00:00 UTC, January 1,
865 * FUNCTION: HV_FAST_TOD_GET
868 * ERRORS: EWOULDBLOCK TOD resource is temporarily unavailable
869 * ENOTSUPPORTED If TOD not supported on this platform
871 * Return the current time of day. May block if TOD access is
872 * temporarily not possible.
874 #define HV_FAST_TOD_GET 0x50
878 * FUNCTION: HV_FAST_TOD_SET
881 * ERRORS: EWOULDBLOCK TOD resource is temporarily unavailable
882 * ENOTSUPPORTED If TOD not supported on this platform
884 * The current time of day is set to the value specified in ARG0. May
885 * block if TOD access is temporarily not possible.
887 #define HV_FAST_TOD_SET 0x51
889 /* Console services */
893 * FUNCTION: HV_FAST_CONS_GETCHAR
896 * ERRORS: EWOULDBLOCK No character available.
898 * Returns a character from the console device. If no character is
899 * available then an EWOULDBLOCK error is returned. If a character is
900 * available, then the returned status is EOK and the character value
903 * A virtual BREAK is represented by the 64-bit value -1.
905 * A virtual HUP signal is represented by the 64-bit value -2.
907 #define HV_FAST_CONS_GETCHAR 0x60
911 * FUNCTION: HV_FAST_CONS_PUTCHAR
914 * ERRORS: EINVAL Illegal character
915 * EWOULDBLOCK Output buffer currentl full, would block
917 * Send a character to the console device. Only character values
918 * between 0 and 255 may be used. Values outside this range are
919 * invalid except for the 64-bit value -1 which is used to send a
922 #define HV_FAST_CONS_PUTCHAR 0x61
924 /* Trap trace services.
926 * The hypervisor provides a trap tracing capability for privileged
927 * code running on each virtual CPU. Privileged code provides a
928 * round-robin trap trace queue within which the hypervisor writes
929 * 64-byte entries detailing hyperprivileged traps taken n behalf of
930 * privileged code. This is provided as a debugging capability for
933 * The trap trace control structure is 64-bytes long and placed at the
934 * start (offset 0) of the trap trace buffer, and is described as
938 struct hv_trap_trace_control {
939 unsigned long head_offset;
940 unsigned long tail_offset;
941 unsigned long __reserved[0x30 / sizeof(unsigned long)];
944 #define HV_TRAP_TRACE_CTRL_HEAD_OFFSET 0x00
945 #define HV_TRAP_TRACE_CTRL_TAIL_OFFSET 0x08
947 /* The head offset is the offset of the most recently completed entry
948 * in the trap-trace buffer. The tail offset is the offset of the
949 * next entry to be written. The control structure is owned and
950 * modified by the hypervisor. A guest may not modify the control
951 * structure contents. Attempts to do so will result in undefined
952 * behavior for the guest.
954 * Each trap trace buffer entry is layed out as follows:
957 struct hv_trap_trace_entry {
958 unsigned char type; /* Hypervisor or guest entry? */
959 unsigned char hpstate; /* Hyper-privileged state */
960 unsigned char tl; /* Trap level */
961 unsigned char gl; /* Global register level */
962 unsigned short tt; /* Trap type */
963 unsigned short tag; /* Extended trap identifier */
964 unsigned long tstate; /* Trap state */
965 unsigned long tick; /* Tick */
966 unsigned long tpc; /* Trap PC */
967 unsigned long f1; /* Entry specific */
968 unsigned long f2; /* Entry specific */
969 unsigned long f3; /* Entry specific */
970 unsigned long f4; /* Entry specific */
973 #define HV_TRAP_TRACE_ENTRY_TYPE 0x00
974 #define HV_TRAP_TRACE_ENTRY_HPSTATE 0x01
975 #define HV_TRAP_TRACE_ENTRY_TL 0x02
976 #define HV_TRAP_TRACE_ENTRY_GL 0x03
977 #define HV_TRAP_TRACE_ENTRY_TT 0x04
978 #define HV_TRAP_TRACE_ENTRY_TAG 0x06
979 #define HV_TRAP_TRACE_ENTRY_TSTATE 0x08
980 #define HV_TRAP_TRACE_ENTRY_TICK 0x10
981 #define HV_TRAP_TRACE_ENTRY_TPC 0x18
982 #define HV_TRAP_TRACE_ENTRY_F1 0x20
983 #define HV_TRAP_TRACE_ENTRY_F2 0x28
984 #define HV_TRAP_TRACE_ENTRY_F3 0x30
985 #define HV_TRAP_TRACE_ENTRY_F4 0x38
987 /* The type field is encoded as follows. */
988 #define HV_TRAP_TYPE_UNDEF 0x00 /* Entry content undefined */
989 #define HV_TRAP_TYPE_HV 0x01 /* Hypervisor trap entry */
990 #define HV_TRAP_TYPE_GUEST 0xff /* Added via ttrace_addentry() */
994 * FUNCTION: HV_FAST_TTRACE_BUF_CONF
996 * ARG1: number of entries
998 * RET1: number of entries
999 * ERRORS: ENORADDR Invalid real address
1000 * EINVAL Size is too small
1001 * EBADALIGN Real address not aligned on 64-byte boundary
1003 * Requests hypervisor trap tracing and declares a virtual CPU's trap
1004 * trace buffer to the hypervisor. The real address supplies the real
1005 * base address of the trap trace queue and must be 64-byte aligned.
1006 * Specifying a value of 0 for the number of entries disables trap
1007 * tracing for the calling virtual CPU. The buffer allocated must be
1008 * sized for a power of two number of 64-byte trap trace entries plus
1009 * an initial 64-byte control structure.
1011 * This may be invoked any number of times so that a virtual CPU may
1012 * relocate a trap trace buffer or create "snapshots" of information.
1014 * If the real address is illegal or badly aligned, then trap tracing
1015 * is disabled and an error is returned.
1017 * Upon failure with EINVAL, this service call returns in RET1 the
1018 * minimum number of buffer entries required. Upon other failures
1019 * RET1 is undefined.
1021 #define HV_FAST_TTRACE_BUF_CONF 0x90
1023 /* ttrace_buf_info()
1024 * TRAP: HV_FAST_TRAP
1025 * FUNCTION: HV_FAST_TTRACE_BUF_INFO
1027 * RET1: real address
1029 * ERRORS: None defined.
1031 * Returns the size and location of the previously declared trap-trace
1032 * buffer. In the event that no buffer was previously defined, or the
1033 * buffer is disabled, this call will return a size of zero bytes.
1035 #define HV_FAST_TTRACE_BUF_INFO 0x91
1038 * TRAP: HV_FAST_TRAP
1039 * FUNCTION: HV_FAST_TTRACE_ENABLE
1042 * RET1: previous enable state
1043 * ERRORS: EINVAL No trap trace buffer currently defined
1045 * Enable or disable trap tracing, and return the previous enabled
1046 * state in RET1. Future systems may define various flags for the
1047 * enable argument (ARG0), for the moment a guest should pass
1048 * "(uint64_t) -1" to enable, and "(uint64_t) 0" to disable all
1049 * tracing - which will ensure future compatability.
1051 #define HV_FAST_TTRACE_ENABLE 0x92
1054 * TRAP: HV_FAST_TRAP
1055 * FUNCTION: HV_FAST_TTRACE_FREEZE
1058 * RET1: previous freeze state
1059 * ERRORS: EINVAL No trap trace buffer currently defined
1061 * Freeze or unfreeze trap tracing, returning the previous freeze
1062 * state in RET1. A guest should pass a non-zero value to freeze and
1063 * a zero value to unfreeze all tracing. The returned previous state
1064 * is 0 for not frozen and 1 for frozen.
1066 #define HV_FAST_TTRACE_FREEZE 0x93
1068 /* ttrace_addentry()
1069 * TRAP: HV_TTRACE_ADDENTRY_TRAP
1070 * ARG0: tag (16-bits)
1076 * ERRORS: EINVAL No trap trace buffer currently defined
1078 * Add an entry to the trap trace buffer. Upon return only ARG0/RET0
1079 * is modified - none of the other registers holding arguments are
1080 * volatile across this hypervisor service.
1083 /* Core dump services.
1085 * Since the hypervisor viraulizes and thus obscures a lot of the
1086 * physical machine layout and state, traditional OS crash dumps can
1087 * be difficult to diagnose especially when the problem is a
1088 * configuration error of some sort.
1090 * The dump services provide an opaque buffer into which the
1091 * hypervisor can place it's internal state in order to assist in
1092 * debugging such situations. The contents are opaque and extremely
1093 * platform and hypervisor implementation specific. The guest, during
1094 * a core dump, requests that the hypervisor update any information in
1095 * the dump buffer in preparation to being dumped as part of the
1096 * domain's memory image.
1099 /* dump_buf_update()
1100 * TRAP: HV_FAST_TRAP
1101 * FUNCTION: HV_FAST_DUMP_BUF_UPDATE
1102 * ARG0: real address
1105 * RET1: required size of dump buffer
1106 * ERRORS: ENORADDR Invalid real address
1107 * EBADALIGN Real address is not aligned on a 64-byte
1109 * EINVAL Size is non-zero but less than minimum size
1111 * ENOTSUPPORTED Operation not supported on current logical
1114 * Declare a domain dump buffer to the hypervisor. The real address
1115 * provided for the domain dump buffer must be 64-byte aligned. The
1116 * size specifies the size of the dump buffer and may be larger than
1117 * the minimum size specified in the machine description. The
1118 * hypervisor will fill the dump buffer with opaque data.
1120 * Note: A guest may elect to include dump buffer contents as part of a crash
1121 * dump to assist with debugging. This function may be called any number
1122 * of times so that a guest may relocate a dump buffer, or create
1123 * "snapshots" of any dump-buffer information. Each call to
1124 * dump_buf_update() atomically declares the new dump buffer to the
1127 * A specified size of 0 unconfigures the dump buffer. If the real
1128 * address is illegal or badly aligned, then any currently active dump
1129 * buffer is disabled and an error is returned.
1131 * In the event that the call fails with EINVAL, RET1 contains the
1132 * minimum size requires by the hypervisor for a valid dump buffer.
1134 #define HV_FAST_DUMP_BUF_UPDATE 0x94
1137 * TRAP: HV_FAST_TRAP
1138 * FUNCTION: HV_FAST_DUMP_BUF_INFO
1140 * RET1: real address of current dump buffer
1141 * RET2: size of current dump buffer
1142 * ERRORS: No errors defined.
1144 * Return the currently configures dump buffer description. A
1145 * returned size of 0 bytes indicates an undefined dump buffer. In
1146 * this case the return address in RET1 is undefined.
1148 #define HV_FAST_DUMP_BUF_INFO 0x95
1150 /* Device interrupt services.
1152 * Device interrupts are allocated to system bus bridges by the hypervisor,
1153 * and described to OBP in the machine description. OBP then describes
1154 * these interrupts to the OS via properties in the device tree.
1158 * cpuid Unique opaque value which represents a target cpu.
1160 * devhandle Device handle. It uniquely identifies a device, and
1161 * consistes of the lower 28-bits of the hi-cell of the
1162 * first entry of the device's "reg" property in the
1165 * devino Device interrupt number. Specifies the relative
1166 * interrupt number within the device. The unique
1167 * combination of devhandle and devino are used to
1168 * identify a specific device interrupt.
1170 * Note: The devino value is the same as the values in the
1171 * "interrupts" property or "interrupt-map" property
1172 * in the OBP device tree for that device.
1174 * sysino System interrupt number. A 64-bit unsigned interger
1175 * representing a unique interrupt within a virtual
1178 * intr_state A flag representing the interrupt state for a given
1179 * sysino. The state values are defined below.
1181 * intr_enabled A flag representing the 'enabled' state for a given
1182 * sysino. The enable values are defined below.
1185 #define HV_INTR_STATE_IDLE 0 /* Nothing pending */
1186 #define HV_INTR_STATE_RECEIVED 1 /* Interrupt received by hardware */
1187 #define HV_INTR_STATE_DELIVERED 2 /* Interrupt delivered to queue */
1189 #define HV_INTR_DISABLED 0 /* sysino not enabled */
1190 #define HV_INTR_ENABLED 1 /* sysino enabled */
1192 /* intr_devino_to_sysino()
1193 * TRAP: HV_FAST_TRAP
1194 * FUNCTION: HV_FAST_INTR_DEVINO2SYSINO
1199 * ERRORS: EINVAL Invalid devhandle/devino
1201 * Converts a device specific interrupt number of the given
1202 * devhandle/devino into a system specific ino (sysino).
1204 #define HV_FAST_INTR_DEVINO2SYSINO 0xa0
1206 /* intr_getenabled()
1207 * TRAP: HV_FAST_TRAP
1208 * FUNCTION: HV_FAST_INTR_GETENABLED
1211 * RET1: intr_enabled (HV_INTR_{DISABLED,ENABLED})
1212 * ERRORS: EINVAL Invalid sysino
1214 * Returns interrupt enabled state in RET1 for the interrupt defined
1215 * by the given sysino.
1217 #define HV_FAST_INTR_GETENABLED 0xa1
1219 /* intr_setenabled()
1220 * TRAP: HV_FAST_TRAP
1221 * FUNCTION: HV_FAST_INTR_SETENABLED
1223 * ARG1: intr_enabled (HV_INTR_{DISABLED,ENABLED})
1225 * ERRORS: EINVAL Invalid sysino or intr_enabled value
1227 * Set the 'enabled' state of the interrupt sysino.
1229 #define HV_FAST_INTR_SETENABLED 0xa2
1232 * TRAP: HV_FAST_TRAP
1233 * FUNCTION: HV_FAST_INTR_GETSTATE
1236 * RET1: intr_state (HV_INTR_STATE_*)
1237 * ERRORS: EINVAL Invalid sysino
1239 * Returns current state of the interrupt defined by the given sysino.
1241 #define HV_FAST_INTR_GETSTATE 0xa3
1244 * TRAP: HV_FAST_TRAP
1245 * FUNCTION: HV_FAST_INTR_SETSTATE
1247 * ARG1: intr_state (HV_INTR_STATE_*)
1249 * ERRORS: EINVAL Invalid sysino or intr_state value
1251 * Sets the current state of the interrupt described by the given sysino
1254 * Note: Setting the state to HV_INTR_STATE_IDLE clears any pending
1255 * interrupt for sysino.
1257 #define HV_FAST_INTR_SETSTATE 0xa4
1260 * TRAP: HV_FAST_TRAP
1261 * FUNCTION: HV_FAST_INTR_GETTARGET
1265 * ERRORS: EINVAL Invalid sysino
1267 * Returns CPU that is the current target of the interrupt defined by
1268 * the given sysino. The CPU value returned is undefined if the target
1269 * has not been set via intr_settarget().
1271 #define HV_FAST_INTR_GETTARGET 0xa5
1274 * TRAP: HV_FAST_TRAP
1275 * FUNCTION: HV_FAST_INTR_SETTARGET
1279 * ERRORS: EINVAL Invalid sysino
1280 * ENOCPU Invalid cpuid
1282 * Set the target CPU for the interrupt defined by the given sysino.
1284 #define HV_FAST_INTR_SETTARGET 0xa6
1288 * See the terminology descriptions in the device interrupt services
1289 * section above as those apply here too. Here are terminology
1290 * definitions specific to these PCI IO services:
1292 * tsbnum TSB number. Indentifies which io-tsb is used.
1293 * For this version of the specification, tsbnum
1296 * tsbindex TSB index. Identifies which entry in the TSB
1297 * is used. The first entry is zero.
1299 * tsbid A 64-bit aligned data structure which contains
1300 * a tsbnum and a tsbindex. Bits 63:32 contain the
1301 * tsbnum and bits 31:00 contain the tsbindex.
1303 * io_attributes IO attributes for IOMMU mappings. One of more
1304 * of the attritbute bits are stores in a 64-bit
1305 * value. The values are defined below.
1307 * r_addr 64-bit real address
1309 * pci_device PCI device address. A PCI device address identifies
1310 * a specific device on a specific PCI bus segment.
1311 * A PCI device address ia a 32-bit unsigned integer
1312 * with the following format:
1314 * 00000000.bbbbbbbb.dddddfff.00000000
1316 * Use the HV_PCI_DEVICE_BUILD() macro to construct
1320 * PCI configureation space offset. For conventional
1321 * PCI a value between 0 and 255. For extended
1322 * configuration space, a value between 0 and 4095.
1324 * Note: For PCI configuration space accesses, the offset
1325 * must be aligned to the access size.
1327 * error_flag A return value which specifies if the action succeeded
1328 * or failed. 0 means no error, non-0 means some error
1329 * occurred while performing the service.
1332 * Direction definition for pci_dma_sync(), defined
1333 * below in HV_PCI_SYNC_*.
1335 * io_page_list A list of io_page_addresses, an io_page_address is
1338 * io_page_list_p A pointer to an io_page_list.
1340 * "size based byte swap" - Some functions do size based byte swapping
1341 * which allows sw to access pointers and
1342 * counters in native form when the processor
1343 * operates in a different endianness than the
1344 * IO bus. Size-based byte swapping converts a
1345 * multi-byte field between big-endian and
1346 * little-endian format.
1349 #define HV_PCI_MAP_ATTR_READ 0x01
1350 #define HV_PCI_MAP_ATTR_WRITE 0x02
1352 #define HV_PCI_DEVICE_BUILD(b,d,f) \
1353 ((((b) & 0xff) << 16) | \
1354 (((d) & 0x1f) << 11) | \
1355 (((f) & 0x07) << 8))
1357 #define HV_PCI_SYNC_FOR_DEVICE 0x01
1358 #define HV_PCI_SYNC_FOR_CPU 0x02
1361 * TRAP: HV_FAST_TRAP
1362 * FUNCTION: HV_FAST_PCI_IOMMU_MAP
1366 * ARG3: io_attributes
1367 * ARG4: io_page_list_p
1369 * RET1: #ttes mapped
1370 * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex/io_attributes
1371 * EBADALIGN Improperly aligned real address
1372 * ENORADDR Invalid real address
1374 * Create IOMMU mappings in the sun4v device defined by the given
1375 * devhandle. The mappings are created in the TSB defined by the
1376 * tsbnum component of the given tsbid. The first mapping is created
1377 * in the TSB i ndex defined by the tsbindex component of the given tsbid.
1378 * The call creates up to #ttes mappings, the first one at tsbnum, tsbindex,
1379 * the second at tsbnum, tsbindex + 1, etc.
1381 * All mappings are created with the attributes defined by the io_attributes
1382 * argument. The page mapping addresses are described in the io_page_list
1383 * defined by the given io_page_list_p, which is a pointer to the io_page_list.
1384 * The first entry in the io_page_list is the address for the first iotte, the
1385 * 2nd for the 2nd iotte, and so on.
1387 * Each io_page_address in the io_page_list must be appropriately aligned.
1388 * #ttes must be greater than zero. For this version of the spec, the tsbnum
1389 * component of the given tsbid must be zero.
1391 * Returns the actual number of mappings creates, which may be less than
1392 * or equal to the argument #ttes. If the function returns a value which
1393 * is less than the #ttes, the caller may continus to call the function with
1394 * an updated tsbid, #ttes, io_page_list_p arguments until all pages are
1397 * Note: This function does not imply an iotte cache flush. The guest must
1398 * demap an entry before re-mapping it.
1400 #define HV_FAST_PCI_IOMMU_MAP 0xb0
1402 /* pci_iommu_demap()
1403 * TRAP: HV_FAST_TRAP
1404 * FUNCTION: HV_FAST_PCI_IOMMU_DEMAP
1409 * RET1: #ttes demapped
1410 * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex
1412 * Demap and flush IOMMU mappings in the device defined by the given
1413 * devhandle. Demaps up to #ttes entries in the TSB defined by the tsbnum
1414 * component of the given tsbid, starting at the TSB index defined by the
1415 * tsbindex component of the given tsbid.
1417 * For this version of the spec, the tsbnum of the given tsbid must be zero.
1418 * #ttes must be greater than zero.
1420 * Returns the actual number of ttes demapped, which may be less than or equal
1421 * to the argument #ttes. If #ttes demapped is less than #ttes, the caller
1422 * may continue to call this function with updated tsbid and #ttes arguments
1423 * until all pages are demapped.
1425 * Note: Entries do not have to be mapped to be demapped. A demap of an
1426 * unmapped page will flush the entry from the tte cache.
1428 #define HV_FAST_PCI_IOMMU_DEMAP 0xb1
1430 /* pci_iommu_getmap()
1431 * TRAP: HV_FAST_TRAP
1432 * FUNCTION: HV_FAST_PCI_IOMMU_GETMAP
1436 * RET1: io_attributes
1437 * RET2: real address
1438 * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex
1439 * ENOMAP Mapping is not valid, no translation exists
1441 * Read and return the mapping in the device described by the given devhandle
1442 * and tsbid. If successful, the io_attributes shall be returned in RET1
1443 * and the page address of the mapping shall be returned in RET2.
1445 * For this version of the spec, the tsbnum component of the given tsbid
1448 #define HV_FAST_PCI_IOMMU_GETMAP 0xb2
1450 /* pci_iommu_getbypass()
1451 * TRAP: HV_FAST_TRAP
1452 * FUNCTION: HV_FAST_PCI_IOMMU_GETBYPASS
1454 * ARG1: real address
1455 * ARG2: io_attributes
1458 * ERRORS: EINVAL Invalid devhandle/io_attributes
1459 * ENORADDR Invalid real address
1460 * ENOTSUPPORTED Function not supported in this implementation.
1462 * Create a "special" mapping in the device described by the given devhandle,
1463 * for the given real address and attributes. Return the IO address in RET1
1466 #define HV_FAST_PCI_IOMMU_GETBYPASS 0xb3
1469 * TRAP: HV_FAST_TRAP
1470 * FUNCTION: HV_FAST_PCI_CONFIG_GET
1473 * ARG2: pci_config_offset
1478 * ERRORS: EINVAL Invalid devhandle/pci_device/offset/size
1479 * EBADALIGN pci_config_offset not size aligned
1480 * ENOACCESS Access to this offset is not permitted
1482 * Read PCI configuration space for the adapter described by the given
1483 * devhandle. Read size (1, 2, or 4) bytes of data from the given
1484 * pci_device, at pci_config_offset from the beginning of the device's
1485 * configuration space. If there was no error, RET1 is set to zero and
1486 * RET2 is set to the data read. Insignificant bits in RET2 are not
1487 * guarenteed to have any specific value and therefore must be ignored.
1489 * The data returned in RET2 is size based byte swapped.
1491 * If an error occurs during the read, set RET1 to a non-zero value. The
1492 * given pci_config_offset must be 'size' aligned.
1494 #define HV_FAST_PCI_CONFIG_GET 0xb4
1497 * TRAP: HV_FAST_TRAP
1498 * FUNCTION: HV_FAST_PCI_CONFIG_PUT
1501 * ARG2: pci_config_offset
1506 * ERRORS: EINVAL Invalid devhandle/pci_device/offset/size
1507 * EBADALIGN pci_config_offset not size aligned
1508 * ENOACCESS Access to this offset is not permitted
1510 * Write PCI configuration space for the adapter described by the given
1511 * devhandle. Write size (1, 2, or 4) bytes of data in a single operation,
1512 * at pci_config_offset from the beginning of the device's configuration
1513 * space. The data argument contains the data to be written to configuration
1514 * space. Prior to writing, the data is size based byte swapped.
1516 * If an error occurs during the write access, do not generate an error
1517 * report, do set RET1 to a non-zero value. Otherwise RET1 is zero.
1518 * The given pci_config_offset must be 'size' aligned.
1520 * This function is permitted to read from offset zero in the configuration
1521 * space described by the given pci_device if necessary to ensure that the
1522 * write access to config space completes.
1524 #define HV_FAST_PCI_CONFIG_PUT 0xb5
1527 * TRAP: HV_FAST_TRAP
1528 * FUNCTION: HV_FAST_PCI_PEEK
1530 * ARG1: real address
1535 * ERRORS: EINVAL Invalid devhandle or size
1536 * EBADALIGN Improperly aligned real address
1537 * ENORADDR Bad real address
1538 * ENOACCESS Guest access prohibited
1540 * Attempt to read the IO address given by the given devhandle, real address,
1541 * and size. Size must be 1, 2, 4, or 8. The read is performed as a single
1542 * access operation using the given size. If an error occurs when reading
1543 * from the given location, do not generate an error report, but return a
1544 * non-zero value in RET1. If the read was successful, return zero in RET1
1545 * and return the actual data read in RET2. The data returned is size based
1548 * Non-significant bits in RET2 are not guarenteed to have any specific value
1549 * and therefore must be ignored. If RET1 is returned as non-zero, the data
1550 * value is not guarenteed to have any specific value and should be ignored.
1552 * The caller must have permission to read from the given devhandle, real
1553 * address, which must be an IO address. The argument real address must be a
1554 * size aligned address.
1556 * The hypervisor implementation of this function must block access to any
1557 * IO address that the guest does not have explicit permission to access.
1559 #define HV_FAST_PCI_PEEK 0xb6
1562 * TRAP: HV_FAST_TRAP
1563 * FUNCTION: HV_FAST_PCI_POKE
1565 * ARG1: real address
1571 * ERRORS: EINVAL Invalid devhandle, size, or pci_device
1572 * EBADALIGN Improperly aligned real address
1573 * ENORADDR Bad real address
1574 * ENOACCESS Guest access prohibited
1575 * ENOTSUPPORTED Function is not supported by implementation
1577 * Attempt to write data to the IO address given by the given devhandle,
1578 * real address, and size. Size must be 1, 2, 4, or 8. The write is
1579 * performed as a single access operation using the given size. Prior to
1580 * writing the data is size based swapped.
1582 * If an error occurs when writing to the given location, do not generate an
1583 * error report, but return a non-zero value in RET1. If the write was
1584 * successful, return zero in RET1.
1586 * pci_device describes the configuration address of the device being
1587 * written to. The implementation may safely read from offset 0 with
1588 * the configuration space of the device described by devhandle and
1589 * pci_device in order to guarantee that the write portion of the operation
1592 * Any error that occurs due to the read shall be reported using the normal
1593 * error reporting mechanisms .. the read error is not suppressed.
1595 * The caller must have permission to write to the given devhandle, real
1596 * address, which must be an IO address. The argument real address must be a
1597 * size aligned address. The caller must have permission to read from
1598 * the given devhandle, pci_device cofiguration space offset 0.
1600 * The hypervisor implementation of this function must block access to any
1601 * IO address that the guest does not have explicit permission to access.
1603 #define HV_FAST_PCI_POKE 0xb7
1606 * TRAP: HV_FAST_TRAP
1607 * FUNCTION: HV_FAST_PCI_DMA_SYNC
1609 * ARG1: real address
1611 * ARG3: io_sync_direction
1614 * ERRORS: EINVAL Invalid devhandle or io_sync_direction
1615 * ENORADDR Bad real address
1617 * Synchronize a memory region described by the given real address and size,
1618 * for the device defined by the given devhandle using the direction(s)
1619 * defined by the given io_sync_direction. The argument size is the size of
1620 * the memory region in bytes.
1622 * Return the actual number of bytes synchronized in the return value #synced,
1623 * which may be less than or equal to the argument size. If the return
1624 * value #synced is less than size, the caller must continue to call this
1625 * function with updated real address and size arguments until the entire
1626 * memory region is synchronized.
1628 #define HV_FAST_PCI_DMA_SYNC 0xb8
1630 /* PCI MSI services. */
1632 #define HV_MSITYPE_MSI32 0x00
1633 #define HV_MSITYPE_MSI64 0x01
1635 #define HV_MSIQSTATE_IDLE 0x00
1636 #define HV_MSIQSTATE_ERROR 0x01
1638 #define HV_MSIQ_INVALID 0x00
1639 #define HV_MSIQ_VALID 0x01
1641 #define HV_MSISTATE_IDLE 0x00
1642 #define HV_MSISTATE_DELIVERED 0x01
1644 #define HV_MSIVALID_INVALID 0x00
1645 #define HV_MSIVALID_VALID 0x01
1647 #define HV_PCIE_MSGTYPE_PME_MSG 0x18
1648 #define HV_PCIE_MSGTYPE_PME_ACK_MSG 0x1b
1649 #define HV_PCIE_MSGTYPE_CORR_MSG 0x30
1650 #define HV_PCIE_MSGTYPE_NONFATAL_MSG 0x31
1651 #define HV_PCIE_MSGTYPE_FATAL_MSG 0x33
1653 #define HV_MSG_INVALID 0x00
1654 #define HV_MSG_VALID 0x01
1657 * TRAP: HV_FAST_TRAP
1658 * FUNCTION: HV_FAST_PCI_MSIQ_CONF
1661 * ARG2: real address
1662 * ARG3: number of entries
1664 * ERRORS: EINVAL Invalid devhandle, msiqid or nentries
1665 * EBADALIGN Improperly aligned real address
1666 * ENORADDR Bad real address
1668 * Configure the MSI queue given by the devhandle and msiqid arguments,
1669 * and to be placed at the given real address and be of the given
1670 * number of entries. The real address must be aligned exactly to match
1671 * the queue size. Each queue entry is 64-bytes long, so f.e. a 32 entry
1672 * queue must be aligned on a 2048 byte real address boundary. The MSI-EQ
1673 * Head and Tail are initialized so that the MSI-EQ is 'empty'.
1675 * Implementation Note: Certain implementations have fixed sized queues. In
1676 * that case, number of entries must contain the correct
1679 #define HV_FAST_PCI_MSIQ_CONF 0xc0
1682 * TRAP: HV_FAST_TRAP
1683 * FUNCTION: HV_FAST_PCI_MSIQ_INFO
1687 * RET1: real address
1688 * RET2: number of entries
1689 * ERRORS: EINVAL Invalid devhandle or msiqid
1691 * Return the configuration information for the MSI queue described
1692 * by the given devhandle and msiqid. The base address of the queue
1693 * is returned in ARG1 and the number of entries is returned in ARG2.
1694 * If the queue is unconfigured, the real address is undefined and the
1695 * number of entries will be returned as zero.
1697 #define HV_FAST_PCI_MSIQ_INFO 0xc1
1699 /* pci_msiq_getvalid()
1700 * TRAP: HV_FAST_TRAP
1701 * FUNCTION: HV_FAST_PCI_MSIQ_GETVALID
1705 * RET1: msiqvalid (HV_MSIQ_VALID or HV_MSIQ_INVALID)
1706 * ERRORS: EINVAL Invalid devhandle or msiqid
1708 * Get the valid state of the MSI-EQ described by the given devhandle and
1711 #define HV_FAST_PCI_MSIQ_GETVALID 0xc2
1713 /* pci_msiq_setvalid()
1714 * TRAP: HV_FAST_TRAP
1715 * FUNCTION: HV_FAST_PCI_MSIQ_SETVALID
1718 * ARG2: msiqvalid (HV_MSIQ_VALID or HV_MSIQ_INVALID)
1720 * ERRORS: EINVAL Invalid devhandle or msiqid or msiqvalid
1721 * value or MSI EQ is uninitialized
1723 * Set the valid state of the MSI-EQ described by the given devhandle and
1724 * msiqid to the given msiqvalid.
1726 #define HV_FAST_PCI_MSIQ_SETVALID 0xc3
1728 /* pci_msiq_getstate()
1729 * TRAP: HV_FAST_TRAP
1730 * FUNCTION: HV_FAST_PCI_MSIQ_GETSTATE
1734 * RET1: msiqstate (HV_MSIQSTATE_IDLE or HV_MSIQSTATE_ERROR)
1735 * ERRORS: EINVAL Invalid devhandle or msiqid
1737 * Get the state of the MSI-EQ described by the given devhandle and
1740 #define HV_FAST_PCI_MSIQ_GETSTATE 0xc4
1742 /* pci_msiq_getvalid()
1743 * TRAP: HV_FAST_TRAP
1744 * FUNCTION: HV_FAST_PCI_MSIQ_GETVALID
1747 * ARG2: msiqstate (HV_MSIQSTATE_IDLE or HV_MSIQSTATE_ERROR)
1749 * ERRORS: EINVAL Invalid devhandle or msiqid or msiqstate
1750 * value or MSI EQ is uninitialized
1752 * Set the state of the MSI-EQ described by the given devhandle and
1753 * msiqid to the given msiqvalid.
1755 #define HV_FAST_PCI_MSIQ_SETSTATE 0xc5
1757 /* pci_msiq_gethead()
1758 * TRAP: HV_FAST_TRAP
1759 * FUNCTION: HV_FAST_PCI_MSIQ_GETHEAD
1764 * ERRORS: EINVAL Invalid devhandle or msiqid
1766 * Get the current MSI EQ queue head for the MSI-EQ described by the
1767 * given devhandle and msiqid.
1769 #define HV_FAST_PCI_MSIQ_GETHEAD 0xc6
1771 /* pci_msiq_sethead()
1772 * TRAP: HV_FAST_TRAP
1773 * FUNCTION: HV_FAST_PCI_MSIQ_SETHEAD
1778 * ERRORS: EINVAL Invalid devhandle or msiqid or msiqhead,
1779 * or MSI EQ is uninitialized
1781 * Set the current MSI EQ queue head for the MSI-EQ described by the
1782 * given devhandle and msiqid.
1784 #define HV_FAST_PCI_MSIQ_SETHEAD 0xc7
1786 /* pci_msiq_gettail()
1787 * TRAP: HV_FAST_TRAP
1788 * FUNCTION: HV_FAST_PCI_MSIQ_GETTAIL
1793 * ERRORS: EINVAL Invalid devhandle or msiqid
1795 * Get the current MSI EQ queue tail for the MSI-EQ described by the
1796 * given devhandle and msiqid.
1798 #define HV_FAST_PCI_MSIQ_GETTAIL 0xc8
1800 /* pci_msi_getvalid()
1801 * TRAP: HV_FAST_TRAP
1802 * FUNCTION: HV_FAST_PCI_MSI_GETVALID
1806 * RET1: msivalidstate
1807 * ERRORS: EINVAL Invalid devhandle or msinum
1809 * Get the current valid/enabled state for the MSI defined by the
1810 * given devhandle and msinum.
1812 #define HV_FAST_PCI_MSI_GETVALID 0xc9
1814 /* pci_msi_setvalid()
1815 * TRAP: HV_FAST_TRAP
1816 * FUNCTION: HV_FAST_PCI_MSI_SETVALID
1819 * ARG2: msivalidstate
1821 * ERRORS: EINVAL Invalid devhandle or msinum or msivalidstate
1823 * Set the current valid/enabled state for the MSI defined by the
1824 * given devhandle and msinum.
1826 #define HV_FAST_PCI_MSI_SETVALID 0xca
1828 /* pci_msi_getmsiq()
1829 * TRAP: HV_FAST_TRAP
1830 * FUNCTION: HV_FAST_PCI_MSI_GETMSIQ
1835 * ERRORS: EINVAL Invalid devhandle or msinum or MSI is unbound
1837 * Get the MSI EQ that the MSI defined by the given devhandle and
1838 * msinum is bound to.
1840 #define HV_FAST_PCI_MSI_GETMSIQ 0xcb
1842 /* pci_msi_setmsiq()
1843 * TRAP: HV_FAST_TRAP
1844 * FUNCTION: HV_FAST_PCI_MSI_SETMSIQ
1850 * ERRORS: EINVAL Invalid devhandle or msinum or msiqid
1852 * Set the MSI EQ that the MSI defined by the given devhandle and
1853 * msinum is bound to.
1855 #define HV_FAST_PCI_MSI_SETMSIQ 0xcc
1857 /* pci_msi_getstate()
1858 * TRAP: HV_FAST_TRAP
1859 * FUNCTION: HV_FAST_PCI_MSI_GETSTATE
1864 * ERRORS: EINVAL Invalid devhandle or msinum
1866 * Get the state of the MSI defined by the given devhandle and msinum.
1867 * If not initialized, return HV_MSISTATE_IDLE.
1869 #define HV_FAST_PCI_MSI_GETSTATE 0xcd
1871 /* pci_msi_setstate()
1872 * TRAP: HV_FAST_TRAP
1873 * FUNCTION: HV_FAST_PCI_MSI_SETSTATE
1878 * ERRORS: EINVAL Invalid devhandle or msinum or msistate
1880 * Set the state of the MSI defined by the given devhandle and msinum.
1882 #define HV_FAST_PCI_MSI_SETSTATE 0xce
1884 /* pci_msg_getmsiq()
1885 * TRAP: HV_FAST_TRAP
1886 * FUNCTION: HV_FAST_PCI_MSG_GETMSIQ
1891 * ERRORS: EINVAL Invalid devhandle or msgtype
1893 * Get the MSI EQ of the MSG defined by the given devhandle and msgtype.
1895 #define HV_FAST_PCI_MSG_GETMSIQ 0xd0
1897 /* pci_msg_setmsiq()
1898 * TRAP: HV_FAST_TRAP
1899 * FUNCTION: HV_FAST_PCI_MSG_SETMSIQ
1904 * ERRORS: EINVAL Invalid devhandle, msgtype, or msiqid
1906 * Set the MSI EQ of the MSG defined by the given devhandle and msgtype.
1908 #define HV_FAST_PCI_MSG_SETMSIQ 0xd1
1910 /* pci_msg_getvalid()
1911 * TRAP: HV_FAST_TRAP
1912 * FUNCTION: HV_FAST_PCI_MSG_GETVALID
1916 * RET1: msgvalidstate
1917 * ERRORS: EINVAL Invalid devhandle or msgtype
1919 * Get the valid/enabled state of the MSG defined by the given
1920 * devhandle and msgtype.
1922 #define HV_FAST_PCI_MSG_GETVALID 0xd2
1924 /* pci_msg_setvalid()
1925 * TRAP: HV_FAST_TRAP
1926 * FUNCTION: HV_FAST_PCI_MSG_SETVALID
1929 * ARG2: msgvalidstate
1931 * ERRORS: EINVAL Invalid devhandle or msgtype or msgvalidstate
1933 * Set the valid/enabled state of the MSG defined by the given
1934 * devhandle and msgtype.
1936 #define HV_FAST_PCI_MSG_SETVALID 0xd3
1938 /* Performance counter services. */
1940 #define HV_PERF_JBUS_PERF_CTRL_REG 0x00
1941 #define HV_PERF_JBUS_PERF_CNT_REG 0x01
1942 #define HV_PERF_DRAM_PERF_CTRL_REG_0 0x02
1943 #define HV_PERF_DRAM_PERF_CNT_REG_0 0x03
1944 #define HV_PERF_DRAM_PERF_CTRL_REG_1 0x04
1945 #define HV_PERF_DRAM_PERF_CNT_REG_1 0x05
1946 #define HV_PERF_DRAM_PERF_CTRL_REG_2 0x06
1947 #define HV_PERF_DRAM_PERF_CNT_REG_2 0x07
1948 #define HV_PERF_DRAM_PERF_CTRL_REG_3 0x08
1949 #define HV_PERF_DRAM_PERF_CNT_REG_3 0x09
1952 * TRAP: HV_FAST_TRAP
1953 * FUNCTION: HV_FAST_GET_PERFREG
1954 * ARG0: performance reg number
1956 * RET1: performance reg value
1957 * ERRORS: EINVAL Invalid performance register number
1958 * ENOACCESS No access allowed to performance counters
1960 * Read the value of the given DRAM/JBUS performance counter/control register.
1962 #define HV_FAST_GET_PERFREG 0x100
1965 * TRAP: HV_FAST_TRAP
1966 * FUNCTION: HV_FAST_SET_PERFREG
1967 * ARG0: performance reg number
1968 * ARG1: performance reg value
1970 * ERRORS: EINVAL Invalid performance register number
1971 * ENOACCESS No access allowed to performance counters
1973 * Write the given performance reg value to the given DRAM/JBUS
1974 * performance counter/control register.
1976 #define HV_FAST_SET_PERFREG 0x101
1978 /* MMU statistics services.
1980 * The hypervisor maintains MMU statistics and privileged code provides
1981 * a buffer where these statistics can be collected. It is continually
1982 * updated once configured. The layout is as follows:
1984 #ifndef __ASSEMBLY__
1985 struct hv_mmu_statistics {
1986 unsigned long immu_tsb_hits_ctx0_8k_tte;
1987 unsigned long immu_tsb_ticks_ctx0_8k_tte;
1988 unsigned long immu_tsb_hits_ctx0_64k_tte;
1989 unsigned long immu_tsb_ticks_ctx0_64k_tte;
1990 unsigned long __reserved1[2];
1991 unsigned long immu_tsb_hits_ctx0_4mb_tte;
1992 unsigned long immu_tsb_ticks_ctx0_4mb_tte;
1993 unsigned long __reserved2[2];
1994 unsigned long immu_tsb_hits_ctx0_256mb_tte;
1995 unsigned long immu_tsb_ticks_ctx0_256mb_tte;
1996 unsigned long __reserved3[4];
1997 unsigned long immu_tsb_hits_ctxnon0_8k_tte;
1998 unsigned long immu_tsb_ticks_ctxnon0_8k_tte;
1999 unsigned long immu_tsb_hits_ctxnon0_64k_tte;
2000 unsigned long immu_tsb_ticks_ctxnon0_64k_tte;
2001 unsigned long __reserved4[2];
2002 unsigned long immu_tsb_hits_ctxnon0_4mb_tte;
2003 unsigned long immu_tsb_ticks_ctxnon0_4mb_tte;
2004 unsigned long __reserved5[2];
2005 unsigned long immu_tsb_hits_ctxnon0_256mb_tte;
2006 unsigned long immu_tsb_ticks_ctxnon0_256mb_tte;
2007 unsigned long __reserved6[4];
2008 unsigned long dmmu_tsb_hits_ctx0_8k_tte;
2009 unsigned long dmmu_tsb_ticks_ctx0_8k_tte;
2010 unsigned long dmmu_tsb_hits_ctx0_64k_tte;
2011 unsigned long dmmu_tsb_ticks_ctx0_64k_tte;
2012 unsigned long __reserved7[2];
2013 unsigned long dmmu_tsb_hits_ctx0_4mb_tte;
2014 unsigned long dmmu_tsb_ticks_ctx0_4mb_tte;
2015 unsigned long __reserved8[2];
2016 unsigned long dmmu_tsb_hits_ctx0_256mb_tte;
2017 unsigned long dmmu_tsb_ticks_ctx0_256mb_tte;
2018 unsigned long __reserved9[4];
2019 unsigned long dmmu_tsb_hits_ctxnon0_8k_tte;
2020 unsigned long dmmu_tsb_ticks_ctxnon0_8k_tte;
2021 unsigned long dmmu_tsb_hits_ctxnon0_64k_tte;
2022 unsigned long dmmu_tsb_ticks_ctxnon0_64k_tte;
2023 unsigned long __reserved10[2];
2024 unsigned long dmmu_tsb_hits_ctxnon0_4mb_tte;
2025 unsigned long dmmu_tsb_ticks_ctxnon0_4mb_tte;
2026 unsigned long __reserved11[2];
2027 unsigned long dmmu_tsb_hits_ctxnon0_256mb_tte;
2028 unsigned long dmmu_tsb_ticks_ctxnon0_256mb_tte;
2029 unsigned long __reserved12[4];
2034 * TRAP: HV_FAST_TRAP
2035 * FUNCTION: HV_FAST_MMUSTAT_CONF
2036 * ARG0: real address
2038 * RET1: real address
2039 * ERRORS: ENORADDR Invalid real address
2040 * EBADALIGN Real address not aligned on 64-byte boundary
2041 * EBADTRAP API not supported on this processor
2043 * Enable MMU statistic gathering using the buffer at the given real
2044 * address on the current virtual CPU. The new buffer real address
2045 * is given in ARG1, and the previously specified buffer real address
2046 * is returned in RET1, or is returned as zero for the first invocation.
2048 * If the passed in real address argument is zero, this will disable
2049 * MMU statistic collection on the current virtual CPU. If an error is
2050 * returned then no statistics are collected.
2052 * The buffer contents should be initialized to all zeros before being
2053 * given to the hypervisor or else the statistics will be meaningless.
2055 #define HV_FAST_MMUSTAT_CONF 0x102
2058 * TRAP: HV_FAST_TRAP
2059 * FUNCTION: HV_FAST_MMUSTAT_INFO
2061 * RET1: real address
2062 * ERRORS: EBADTRAP API not supported on this processor
2064 * Return the current state and real address of the currently configured
2065 * MMU statistics buffer on the current virtual CPU.
2067 #define HV_FAST_MMUSTAT_INFO 0x103
2069 /* Function numbers for HV_CORE_TRAP. */
2070 #define HV_CORE_VER 0x00
2071 #define HV_CORE_PUTCHAR 0x01
2072 #define HV_CORE_EXIT 0x02
2074 #endif /* !(_SPARC64_HYPERVISOR_H) */