1 #ifndef _SPARC64_HYPERVISOR_H
2 #define _SPARC64_HYPERVISOR_H
4 /* Sun4v hypervisor interfaces and defines.
6 * Hypervisor calls are made via traps to software traps number 0x80
7 * and above. Registers %o0 to %o5 serve as argument, status, and
8 * return value registers.
10 * There are two kinds of these traps. First there are the normal
11 * "fast traps" which use software trap 0x80 and encode the function
12 * to invoke by number in register %o5. Argument and return value
13 * handling is as follows:
15 * -----------------------------------------------
16 * | %o5 | function number | undefined |
17 * | %o0 | argument 0 | return status |
18 * | %o1 | argument 1 | return value 1 |
19 * | %o2 | argument 2 | return value 2 |
20 * | %o3 | argument 3 | return value 3 |
21 * | %o4 | argument 4 | return value 4 |
22 * -----------------------------------------------
24 * The second type are "hyper-fast traps" which encode the function
25 * number in the software trap number itself. So these use trap
26 * numbers > 0x80. The register usage for hyper-fast traps is as
29 * -----------------------------------------------
30 * | %o0 | argument 0 | return status |
31 * | %o1 | argument 1 | return value 1 |
32 * | %o2 | argument 2 | return value 2 |
33 * | %o3 | argument 3 | return value 3 |
34 * | %o4 | argument 4 | return value 4 |
35 * -----------------------------------------------
37 * Registers providing explicit arguments to the hypervisor calls
38 * are volatile across the call. Upon return their values are
39 * undefined unless explicitly specified as containing a particular
40 * return value by the specific call. The return status is always
41 * returned in register %o0, zero indicates a successful execution of
42 * the hypervisor call and other values indicate an error status as
43 * defined below. So, for example, if a hyper-fast trap takes
44 * arguments 0, 1, and 2, then %o0, %o1, and %o2 are volatile across
45 * the call and %o3, %o4, and %o5 would be preserved.
47 * If the hypervisor trap is invalid, or the fast trap function number
48 * is invalid, HV_EBADTRAP will be returned in %o0. Also, all 64-bits
49 * of the argument and return values are significant.
53 #define HV_FAST_TRAP 0x80
54 #define HV_MMU_MAP_ADDR_TRAP 0x83
55 #define HV_MMU_UNMAP_ADDR_TRAP 0x84
56 #define HV_TTRACE_ADDENTRY_TRAP 0x85
57 #define HV_CORE_TRAP 0xff
60 #define HV_EOK 0 /* Successful return */
61 #define HV_ENOCPU 1 /* Invalid CPU id */
62 #define HV_ENORADDR 2 /* Invalid real address */
63 #define HV_ENOINTR 3 /* Invalid interrupt id */
64 #define HV_EBADPGSZ 4 /* Invalid pagesize encoding */
65 #define HV_EBADTSB 5 /* Invalid TSB description */
66 #define HV_EINVAL 6 /* Invalid argument */
67 #define HV_EBADTRAP 7 /* Invalid function number */
68 #define HV_EBADALIGN 8 /* Invalid address alignment */
69 #define HV_EWOULDBLOCK 9 /* Cannot complete w/o blocking */
70 #define HV_ENOACCESS 10 /* No access to resource */
71 #define HV_EIO 11 /* I/O error */
72 #define HV_ECPUERROR 12 /* CPU in error state */
73 #define HV_ENOTSUPPORTED 13 /* Function not supported */
74 #define HV_ENOMAP 14 /* No mapping found */
75 #define HV_ETOOMANY 15 /* Too many items specified */
79 * FUNCTION: HV_FAST_MACH_EXIT
81 * ERRORS: This service does not return.
83 * Stop all CPUs in the virtual domain and place them into the stopped
84 * state. The 64-bit exit code may be passed to a service entity as
85 * the domain's exit status. On systems without a service entity, the
86 * domain will undergo a reset, and the boot firmware will be
89 * This function will never return to the guest that invokes it.
91 * Note: By convention an exit code of zero denotes a successful exit by
92 * the guest code. A non-zero exit code denotes a guest specific
96 #define HV_FAST_MACH_EXIT 0x00
98 /* Domain services. */
102 * FUNCTION: HV_FAST_MACH_DESC
107 * ERRORS: HV_EBADALIGN Buffer is badly aligned
108 * HV_ENORADDR Buffer is to an illegal real address.
109 * HV_EINVAL Buffer length is too small for complete
110 * machine description.
112 * Copy the most current machine description into the buffer indicated
113 * by the real address in ARG0. The buffer provided must be 16 byte
114 * aligned. Upon success or HV_EINVAL, this service returns the
115 * actual size of the machine description in the RET1 return value.
117 * Note: A method of determining the appropriate buffer size for the
118 * machine description is to first call this service with a buffer
121 #define HV_FAST_MACH_DESC 0x01
125 * FUNCTION: HV_FAST_MACH_SIR
126 * ERRORS: This service does not return.
128 * Perform a software initiated reset of the virtual machine domain.
129 * All CPUs are captured as soon as possible, all hardware devices are
130 * returned to the entry default state, and the domain is restarted at
131 * the SIR (trap type 0x04) real trap table (RTBA) entry point on one
132 * of the CPUs. The single CPU restarted is selected as determined by
133 * platform specific policy. Memory is preserved across this
136 #define HV_FAST_MACH_SIR 0x02
138 /* mach_set_soft_state()
140 * FUNCTION: HV_FAST_MACH_SET_SOFT_STATE
141 * ARG0: software state
142 * ARG1: software state description pointer
144 * ERRORS: EINVAL software state not valid or software state
145 * description is not NULL terminated
146 * ENORADDR software state description pointer is not a
148 * EBADALIGNED software state description is not correctly
151 * This allows the guest to report it's soft state to the hypervisor. There
152 * are two primary components to this state. The first part states whether
153 * the guest software is running or not. The second containts optional
154 * details specific to the software.
156 * The software state argument is defined below in HV_SOFT_STATE_*, and
157 * indicates whether the guest is operating normally or in a transitional
160 * The software state description argument is a real address of a data buffer
161 * of size 32-bytes aligned on a 32-byte boundary. It is treated as a NULL
162 * terminated 7-bit ASCII string of up to 31 characters not including the
165 #define HV_FAST_MACH_SET_SOFT_STATE 0x03
166 #define HV_SOFT_STATE_NORMAL 0x01
167 #define HV_SOFT_STATE_TRANSITION 0x02
169 /* mach_get_soft_state()
171 * FUNCTION: HV_FAST_MACH_GET_SOFT_STATE
172 * ARG0: software state description pointer
174 * RET1: software state
175 * ERRORS: ENORADDR software state description pointer is not a
177 * EBADALIGNED software state description is not correctly
180 * Retrieve the current value of the guest's software state. The rules
181 * for the software state pointer are the same as for mach_set_soft_state()
184 #define HV_FAST_MACH_GET_SOFT_STATE 0x04
188 * CPUs represent devices that can execute software threads. A single
189 * chip that contains multiple cores or strands is represented as
190 * multiple CPUs with unique CPU identifiers. CPUs are exported to
191 * OBP via the machine description (and to the OS via the OBP device
192 * tree). CPUs are always in one of three states: stopped, running,
195 * A CPU ID is a pre-assigned 16-bit value that uniquely identifies a
196 * CPU within a logical domain. Operations that are to be performed
197 * on multiple CPUs specify them via a CPU list. A CPU list is an
198 * array in real memory, of which each 16-bit word is a CPU ID. CPU
199 * lists are passed through the API as two arguments. The first is
200 * the number of entries (16-bit words) in the CPU list, and the
201 * second is the (real address) pointer to the CPU ID list.
206 * FUNCTION: HV_FAST_CPU_START
212 * ERRORS: ENOCPU Invalid CPU ID
213 * EINVAL Target CPU ID is not in the stopped state
214 * ENORADDR Invalid PC or RTBA real address
215 * EBADALIGN Unaligned PC or unaligned RTBA
216 * EWOULDBLOCK Starting resources are not available
218 * Start CPU with given CPU ID with PC in %pc and with a real trap
219 * base address value of RTBA. The indicated CPU must be in the
220 * stopped state. The supplied RTBA must be aligned on a 256 byte
221 * boundary. On successful completion, the specified CPU will be in
222 * the running state and will be supplied with "target ARG0" in %o0
225 #define HV_FAST_CPU_START 0x10
229 * FUNCTION: HV_FAST_CPU_STOP
232 * ERRORS: ENOCPU Invalid CPU ID
233 * EINVAL Target CPU ID is the current cpu
234 * EINVAL Target CPU ID is not in the running state
235 * EWOULDBLOCK Stopping resources are not available
236 * ENOTSUPPORTED Not supported on this platform
238 * The specified CPU is stopped. The indicated CPU must be in the
239 * running state. On completion, it will be in the stopped state. It
240 * is not legal to stop the current CPU.
242 * Note: As this service cannot be used to stop the current cpu, this service
243 * may not be used to stop the last running CPU in a domain. To stop
244 * and exit a running domain, a guest must use the mach_exit() service.
246 #define HV_FAST_CPU_STOP 0x11
250 * FUNCTION: HV_FAST_CPU_YIELD
252 * ERRORS: No possible error.
254 * Suspend execution on the current CPU. Execution will resume when
255 * an interrupt (device, %stick_compare, or cross-call) is targeted to
256 * the CPU. On some CPUs, this API may be used by the hypervisor to
257 * save power by disabling hardware strands.
259 #define HV_FAST_CPU_YIELD 0x12
264 * FUNCTION: HV_FAST_CPU_QCONF
266 * ARG1: base real address
267 * ARG2: number of entries
269 * ERRORS: ENORADDR Invalid base real address
270 * EINVAL Invalid queue or number of entries is less
271 * than 2 or too large.
272 * EBADALIGN Base real address is not correctly aligned
275 * Configure the given queue to be placed at the given base real
276 * address, with the given number of entries. The number of entries
277 * must be a power of 2. The base real address must be aligned
278 * exactly to match the queue size. Each queue entry is 64 bytes
279 * long, so for example a 32 entry queue must be aligned on a 2048
280 * byte real address boundary.
282 * The specified queue is unconfigured if the number of entries is given
285 * For the current version of this API service, the argument queue is defined
289 * ----- -------------------------
290 * 0x3c cpu mondo queue
291 * 0x3d device mondo queue
292 * 0x3e resumable error queue
293 * 0x3f non-resumable error queue
295 * Note: The maximum number of entries for each queue for a specific cpu may
296 * be determined from the machine description.
298 #define HV_FAST_CPU_QCONF 0x14
299 #define HV_CPU_QUEUE_CPU_MONDO 0x3c
300 #define HV_CPU_QUEUE_DEVICE_MONDO 0x3d
301 #define HV_CPU_QUEUE_RES_ERROR 0x3e
302 #define HV_CPU_QUEUE_NONRES_ERROR 0x3f
305 extern unsigned long sun4v_cpu_qconf(unsigned long type,
306 unsigned long queue_paddr,
307 unsigned long num_queue_entries);
312 * FUNCTION: HV_FAST_CPU_QINFO
315 * RET1: base real address
316 * RET1: number of entries
317 * ERRORS: EINVAL Invalid queue
319 * Return the configuration info for the given queue. The base real
320 * address and number of entries of the defined queue are returned.
321 * The queue argument values are the same as for cpu_qconf() above.
323 * If the specified queue is a valid queue number, but no queue has
324 * been defined, the number of entries will be set to zero and the
325 * base real address returned is undefined.
327 #define HV_FAST_CPU_QINFO 0x15
331 * FUNCTION: HV_FAST_CPU_MONDO_SEND
333 * ARG2: data real address
335 * ERRORS: EBADALIGN Mondo data is not 64-byte aligned or CPU list
336 * is not 2-byte aligned.
337 * ENORADDR Invalid data mondo address, or invalid cpu list
339 * ENOCPU Invalid cpu in CPU list
340 * EWOULDBLOCK Some or all of the listed CPUs did not receive
342 * EINVAL CPU list includes caller's CPU ID
344 * Send a mondo interrupt to the CPUs in the given CPU list with the
345 * 64-bytes at the given data real address. The data must be 64-byte
346 * aligned. The mondo data will be delivered to the cpu_mondo queues
347 * of the recipient CPUs.
349 * In all cases, error or not, the CPUs in the CPU list to which the
350 * mondo has been successfully delivered will be indicated by having
351 * their entry in CPU list updated with the value 0xffff.
353 #define HV_FAST_CPU_MONDO_SEND 0x42
357 * FUNCTION: HV_FAST_CPU_MYID
360 * ERRORS: No errors defined.
362 * Return the hypervisor ID handle for the current CPU. Use by a
363 * virtual CPU to discover it's own identity.
365 #define HV_FAST_CPU_MYID 0x16
369 * FUNCTION: HV_FAST_CPU_STATE
373 * ERRORS: ENOCPU Invalid CPU ID
375 * Retrieve the current state of the CPU with the given CPU ID.
377 #define HV_FAST_CPU_STATE 0x17
378 #define HV_CPU_STATE_STOPPED 0x01
379 #define HV_CPU_STATE_RUNNING 0x02
380 #define HV_CPU_STATE_ERROR 0x03
384 * FUNCTION: HV_FAST_CPU_SET_RTBA
387 * RET1: previous RTBA
388 * ERRORS: ENORADDR Invalid RTBA real address
389 * EBADALIGN RTBA is incorrectly aligned for a trap table
391 * Set the real trap base address of the local cpu to the given RTBA.
392 * The supplied RTBA must be aligned on a 256 byte boundary. Upon
393 * success the previous value of the RTBA is returned in RET1.
395 * Note: This service does not affect %tba
397 #define HV_FAST_CPU_SET_RTBA 0x18
401 * FUNCTION: HV_FAST_CPU_GET_RTBA
403 * RET1: previous RTBA
404 * ERRORS: No possible error.
406 * Returns the current value of RTBA in RET1.
408 #define HV_FAST_CPU_GET_RTBA 0x19
412 * Layout of a TSB description for mmu_tsb_ctx{,non}0() calls.
415 struct hv_tsb_descr {
416 unsigned short pgsz_idx;
417 unsigned short assoc;
418 unsigned int num_ttes; /* in TTEs */
419 unsigned int ctx_idx;
420 unsigned int pgsz_mask;
421 unsigned long tsb_base;
425 #define HV_TSB_DESCR_PGSZ_IDX_OFFSET 0x00
426 #define HV_TSB_DESCR_ASSOC_OFFSET 0x02
427 #define HV_TSB_DESCR_NUM_TTES_OFFSET 0x04
428 #define HV_TSB_DESCR_CTX_IDX_OFFSET 0x08
429 #define HV_TSB_DESCR_PGSZ_MASK_OFFSET 0x0c
430 #define HV_TSB_DESCR_TSB_BASE_OFFSET 0x10
431 #define HV_TSB_DESCR_RESV_OFFSET 0x18
433 /* Page size bitmask. */
434 #define HV_PGSZ_MASK_8K (1 << 0)
435 #define HV_PGSZ_MASK_64K (1 << 1)
436 #define HV_PGSZ_MASK_512K (1 << 2)
437 #define HV_PGSZ_MASK_4MB (1 << 3)
438 #define HV_PGSZ_MASK_32MB (1 << 4)
439 #define HV_PGSZ_MASK_256MB (1 << 5)
440 #define HV_PGSZ_MASK_2GB (1 << 6)
441 #define HV_PGSZ_MASK_16GB (1 << 7)
443 /* Page size index. The value given in the TSB descriptor must correspond
444 * to the smallest page size specified in the pgsz_mask page size bitmask.
446 #define HV_PGSZ_IDX_8K 0
447 #define HV_PGSZ_IDX_64K 1
448 #define HV_PGSZ_IDX_512K 2
449 #define HV_PGSZ_IDX_4MB 3
450 #define HV_PGSZ_IDX_32MB 4
451 #define HV_PGSZ_IDX_256MB 5
452 #define HV_PGSZ_IDX_2GB 6
453 #define HV_PGSZ_IDX_16GB 7
455 /* MMU fault status area.
457 * MMU related faults have their status and fault address information
458 * placed into a memory region made available by privileged code. Each
459 * virtual processor must make a mmu_fault_area_conf() call to tell the
460 * hypervisor where that processor's fault status should be stored.
462 * The fault status block is a multiple of 64-bytes and must be aligned
463 * on a 64-byte boundary.
466 struct hv_fault_status {
467 unsigned long i_fault_type;
468 unsigned long i_fault_addr;
469 unsigned long i_fault_ctx;
470 unsigned long i_reserved[5];
471 unsigned long d_fault_type;
472 unsigned long d_fault_addr;
473 unsigned long d_fault_ctx;
474 unsigned long d_reserved[5];
477 #define HV_FAULT_I_TYPE_OFFSET 0x00
478 #define HV_FAULT_I_ADDR_OFFSET 0x08
479 #define HV_FAULT_I_CTX_OFFSET 0x10
480 #define HV_FAULT_D_TYPE_OFFSET 0x40
481 #define HV_FAULT_D_ADDR_OFFSET 0x48
482 #define HV_FAULT_D_CTX_OFFSET 0x50
484 #define HV_FAULT_TYPE_FAST_MISS 1
485 #define HV_FAULT_TYPE_FAST_PROT 2
486 #define HV_FAULT_TYPE_MMU_MISS 3
487 #define HV_FAULT_TYPE_INV_RA 4
488 #define HV_FAULT_TYPE_PRIV_VIOL 5
489 #define HV_FAULT_TYPE_PROT_VIOL 6
490 #define HV_FAULT_TYPE_NFO 7
491 #define HV_FAULT_TYPE_NFO_SEFF 8
492 #define HV_FAULT_TYPE_INV_VA 9
493 #define HV_FAULT_TYPE_INV_ASI 10
494 #define HV_FAULT_TYPE_NC_ATOMIC 11
495 #define HV_FAULT_TYPE_PRIV_ACT 12
496 #define HV_FAULT_TYPE_RESV1 13
497 #define HV_FAULT_TYPE_UNALIGNED 14
498 #define HV_FAULT_TYPE_INV_PGSZ 15
499 /* Values 16 --> -2 are reserved. */
500 #define HV_FAULT_TYPE_MULTIPLE -1
502 /* Flags argument for mmu_{map,unmap}_addr(), mmu_demap_{page,context,all}(),
503 * and mmu_{map,unmap}_perm_addr().
505 #define HV_MMU_DMMU 0x01
506 #define HV_MMU_IMMU 0x02
507 #define HV_MMU_ALL (HV_MMU_DMMU | HV_MMU_IMMU)
510 * TRAP: HV_MMU_MAP_ADDR_TRAP
511 * ARG0: virtual address
514 * ARG3: flags (HV_MMU_{IMMU,DMMU})
515 * ERRORS: EINVAL Invalid virtual address, mmu context, or flags
516 * EBADPGSZ Invalid page size value
517 * ENORADDR Invalid real address in TTE
519 * Create a non-permanent mapping using the given TTE, virtual
520 * address, and mmu context. The flags argument determines which
521 * (data, or instruction, or both) TLB the mapping gets loaded into.
523 * The behavior is undefined if the valid bit is clear in the TTE.
525 * Note: This API call is for privileged code to specify temporary translation
526 * mappings without the need to create and manage a TSB.
530 * TRAP: HV_MMU_UNMAP_ADDR_TRAP
531 * ARG0: virtual address
533 * ARG2: flags (HV_MMU_{IMMU,DMMU})
534 * ERRORS: EINVAL Invalid virtual address, mmu context, or flags
536 * Demaps the given virtual address in the given mmu context on this
537 * CPU. This function is intended to be used to demap pages mapped
538 * with mmu_map_addr. This service is equivalent to invoking
539 * mmu_demap_page() with only the current CPU in the CPU list. The
540 * flags argument determines which (data, or instruction, or both) TLB
541 * the mapping gets unmapped from.
543 * Attempting to perform an unmap operation for a previously defined
544 * permanent mapping will have undefined results.
549 * FUNCTION: HV_FAST_MMU_TSB_CTX0
550 * ARG0: number of TSB descriptions
551 * ARG1: TSB descriptions pointer
553 * ERRORS: ENORADDR Invalid TSB descriptions pointer or
554 * TSB base within a descriptor
555 * EBADALIGN TSB descriptions pointer is not aligned
556 * to an 8-byte boundary, or TSB base
557 * within a descriptor is not aligned for
559 * EBADPGSZ Invalid page size in a TSB descriptor
560 * EBADTSB Invalid associativity or size in a TSB
562 * EINVAL Invalid number of TSB descriptions, or
563 * invalid context index in a TSB
564 * descriptor, or index page size not
565 * equal to smallest page size in page
566 * size bitmask field.
568 * Configures the TSBs for the current CPU for virtual addresses with
569 * context zero. The TSB descriptions pointer is a pointer to an
570 * array of the given number of TSB descriptions.
572 * Note: The maximum number of TSBs available to a virtual CPU is given by the
573 * mmu-max-#tsbs property of the cpu's corresponding "cpu" node in the
574 * machine description.
576 #define HV_FAST_MMU_TSB_CTX0 0x20
580 * FUNCTION: HV_FAST_MMU_TSB_CTXNON0
581 * ARG0: number of TSB descriptions
582 * ARG1: TSB descriptions pointer
584 * ERRORS: Same as for mmu_tsb_ctx0() above.
586 * Configures the TSBs for the current CPU for virtual addresses with
587 * non-zero contexts. The TSB descriptions pointer is a pointer to an
588 * array of the given number of TSB descriptions.
590 * Note: A maximum of 16 TSBs may be specified in the TSB description list.
592 #define HV_FAST_MMU_TSB_CTXNON0 0x21
596 * FUNCTION: HV_FAST_MMU_DEMAP_PAGE
597 * ARG0: reserved, must be zero
598 * ARG1: reserved, must be zero
599 * ARG2: virtual address
601 * ARG4: flags (HV_MMU_{IMMU,DMMU})
603 * ERRORS: EINVAL Invalid virutal address, context, or
605 * ENOTSUPPORTED ARG0 or ARG1 is non-zero
607 * Demaps any page mapping of the given virtual address in the given
608 * mmu context for the current virtual CPU. Any virtually tagged
609 * caches are guaranteed to be kept consistent. The flags argument
610 * determines which TLB (instruction, or data, or both) participate in
613 * ARG0 and ARG1 are both reserved and must be set to zero.
615 #define HV_FAST_MMU_DEMAP_PAGE 0x22
619 * FUNCTION: HV_FAST_MMU_DEMAP_CTX
620 * ARG0: reserved, must be zero
621 * ARG1: reserved, must be zero
623 * ARG3: flags (HV_MMU_{IMMU,DMMU})
625 * ERRORS: EINVAL Invalid context or flags value
626 * ENOTSUPPORTED ARG0 or ARG1 is non-zero
628 * Demaps all non-permanent virtual page mappings previously specified
629 * for the given context for the current virtual CPU. Any virtual
630 * tagged caches are guaranteed to be kept consistent. The flags
631 * argument determines which TLB (instruction, or data, or both)
632 * participate in the operation.
634 * ARG0 and ARG1 are both reserved and must be set to zero.
636 #define HV_FAST_MMU_DEMAP_CTX 0x23
640 * FUNCTION: HV_FAST_MMU_DEMAP_ALL
641 * ARG0: reserved, must be zero
642 * ARG1: reserved, must be zero
643 * ARG2: flags (HV_MMU_{IMMU,DMMU})
645 * ERRORS: EINVAL Invalid flags value
646 * ENOTSUPPORTED ARG0 or ARG1 is non-zero
648 * Demaps all non-permanent virtual page mappings previously specified
649 * for the current virtual CPU. Any virtual tagged caches are
650 * guaranteed to be kept consistent. The flags argument determines
651 * which TLB (instruction, or data, or both) participate in the
654 * ARG0 and ARG1 are both reserved and must be set to zero.
656 #define HV_FAST_MMU_DEMAP_ALL 0x24
658 /* mmu_map_perm_addr()
660 * FUNCTION: HV_FAST_MMU_MAP_PERM_ADDR
661 * ARG0: virtual address
662 * ARG1: reserved, must be zero
664 * ARG3: flags (HV_MMU_{IMMU,DMMU})
666 * ERRORS: EINVAL Invalid virutal address or flags value
667 * EBADPGSZ Invalid page size value
668 * ENORADDR Invalid real address in TTE
669 * ETOOMANY Too many mappings (max of 8 reached)
671 * Create a permanent mapping using the given TTE and virtual address
672 * for context 0 on the calling virtual CPU. A maximum of 8 such
673 * permanent mappings may be specified by privileged code. Mappings
674 * may be removed with mmu_unmap_perm_addr().
676 * The behavior is undefined if a TTE with the valid bit clear is given.
678 * Note: This call is used to specify address space mappings for which
679 * privileged code does not expect to receive misses. For example,
680 * this mechanism can be used to map kernel nucleus code and data.
682 #define HV_FAST_MMU_MAP_PERM_ADDR 0x25
684 /* mmu_fault_area_conf()
686 * FUNCTION: HV_FAST_MMU_FAULT_AREA_CONF
689 * RET1: previous mmu fault area real address
690 * ERRORS: ENORADDR Invalid real address
691 * EBADALIGN Invalid alignment for fault area
693 * Configure the MMU fault status area for the calling CPU. A 64-byte
694 * aligned real address specifies where MMU fault status information
695 * is placed. The return value is the previously specified area, or 0
696 * for the first invocation. Specifying a fault area at real address
699 #define HV_FAST_MMU_FAULT_AREA_CONF 0x26
703 * FUNCTION: HV_FAST_MMU_ENABLE
705 * ARG1: return target address
707 * ERRORS: ENORADDR Invalid real address when disabling
709 * EBADALIGN The return target address is not
710 * aligned to an instruction.
711 * EINVAL The enable flag request the current
712 * operating mode (e.g. disable if already
715 * Enable or disable virtual address translation for the calling CPU
716 * within the virtual machine domain. If the enable flag is zero,
717 * translation is disabled, any non-zero value will enable
720 * When this function returns, the newly selected translation mode
721 * will be active. If the mmu is being enabled, then the return
722 * target address is a virtual address else it is a real address.
724 * Upon successful completion, control will be returned to the given
725 * return target address (ie. the cpu will jump to that address). On
726 * failure, the previous mmu mode remains and the trap simply returns
727 * as normal with the appropriate error code in RET0.
729 #define HV_FAST_MMU_ENABLE 0x27
731 /* mmu_unmap_perm_addr()
733 * FUNCTION: HV_FAST_MMU_UNMAP_PERM_ADDR
734 * ARG0: virtual address
735 * ARG1: reserved, must be zero
736 * ARG2: flags (HV_MMU_{IMMU,DMMU})
738 * ERRORS: EINVAL Invalid virutal address or flags value
739 * ENOMAP Specified mapping was not found
741 * Demaps any permanent page mapping (established via
742 * mmu_map_perm_addr()) at the given virtual address for context 0 on
743 * the current virtual CPU. Any virtual tagged caches are guaranteed
744 * to be kept consistent.
746 #define HV_FAST_MMU_UNMAP_PERM_ADDR 0x28
748 /* mmu_tsb_ctx0_info()
750 * FUNCTION: HV_FAST_MMU_TSB_CTX0_INFO
752 * ARG1: buffer pointer
754 * RET1: number of TSBs
755 * ERRORS: EINVAL Supplied buffer is too small
756 * EBADALIGN The buffer pointer is badly aligned
757 * ENORADDR Invalid real address for buffer pointer
759 * Return the TSB configuration as previous defined by mmu_tsb_ctx0()
760 * into the provided buffer. The size of the buffer is given in ARG1
761 * in terms of the number of TSB description entries.
763 * Upon return, RET1 always contains the number of TSB descriptions
764 * previously configured. If zero TSBs were configured, EOK is
765 * returned with RET1 containing 0.
767 #define HV_FAST_MMU_TSB_CTX0_INFO 0x29
769 /* mmu_tsb_ctxnon0_info()
771 * FUNCTION: HV_FAST_MMU_TSB_CTXNON0_INFO
773 * ARG1: buffer pointer
775 * RET1: number of TSBs
776 * ERRORS: EINVAL Supplied buffer is too small
777 * EBADALIGN The buffer pointer is badly aligned
778 * ENORADDR Invalid real address for buffer pointer
780 * Return the TSB configuration as previous defined by
781 * mmu_tsb_ctxnon0() into the provided buffer. The size of the buffer
782 * is given in ARG1 in terms of the number of TSB description entries.
784 * Upon return, RET1 always contains the number of TSB descriptions
785 * previously configured. If zero TSBs were configured, EOK is
786 * returned with RET1 containing 0.
788 #define HV_FAST_MMU_TSB_CTXNON0_INFO 0x2a
790 /* mmu_fault_area_info()
792 * FUNCTION: HV_FAST_MMU_FAULT_AREA_INFO
794 * RET1: fault area real address
795 * ERRORS: No errors defined.
797 * Return the currently defined MMU fault status area for the current
798 * CPU. The real address of the fault status area is returned in
799 * RET1, or 0 is returned in RET1 if no fault status area is defined.
801 * Note: mmu_fault_area_conf() may be called with the return value (RET1)
802 * from this service if there is a need to save and restore the fault
805 #define HV_FAST_MMU_FAULT_AREA_INFO 0x2b
807 /* Cache and Memory services. */
811 * FUNCTION: HV_FAST_MEM_SCRUB
815 * RET1: length scrubbed
816 * ERRORS: ENORADDR Invalid real address
817 * EBADALIGN Start address or length are not correctly
819 * EINVAL Length is zero
821 * Zero the memory contents in the range real address to real address
822 * plus length minus 1. Also, valid ECC will be generated for that
823 * memory address range. Scrubbing is started at the given real
824 * address, but may not scrub the entire given length. The actual
825 * length scrubbed will be returned in RET1.
827 * The real address and length must be aligned on an 8K boundary, or
828 * contain the start address and length from a sun4v error report.
830 * Note: There are two uses for this function. The first use is to block clear
831 * and initialize memory and the second is to scrub an u ncorrectable
832 * error reported via a resumable or non-resumable trap. The second
833 * use requires the arguments to be equal to the real address and length
834 * provided in a sun4v memory error report.
836 #define HV_FAST_MEM_SCRUB 0x31
840 * FUNCTION: HV_FAST_MEM_SYNC
844 * RET1: length synced
845 * ERRORS: ENORADDR Invalid real address
846 * EBADALIGN Start address or length are not correctly
848 * EINVAL Length is zero
850 * Force the next access within the real address to real address plus
851 * length minus 1 to be fetches from main system memory. Less than
852 * the given length may be synced, the actual amount synced is
853 * returned in RET1. The real address and length must be aligned on
856 #define HV_FAST_MEM_SYNC 0x32
858 /* Time of day services.
860 * The hypervisor maintains the time of day on a per-domain basis.
861 * Changing the time of day in one domain does not affect the time of
862 * day on any other domain.
864 * Time is described by a single unsigned 64-bit word which is the
865 * number of seconds since the UNIX Epoch (00:00:00 UTC, January 1,
871 * FUNCTION: HV_FAST_TOD_GET
874 * ERRORS: EWOULDBLOCK TOD resource is temporarily unavailable
875 * ENOTSUPPORTED If TOD not supported on this platform
877 * Return the current time of day. May block if TOD access is
878 * temporarily not possible.
880 #define HV_FAST_TOD_GET 0x50
884 * FUNCTION: HV_FAST_TOD_SET
887 * ERRORS: EWOULDBLOCK TOD resource is temporarily unavailable
888 * ENOTSUPPORTED If TOD not supported on this platform
890 * The current time of day is set to the value specified in ARG0. May
891 * block if TOD access is temporarily not possible.
893 #define HV_FAST_TOD_SET 0x51
895 /* Console services */
899 * FUNCTION: HV_FAST_CONS_GETCHAR
902 * ERRORS: EWOULDBLOCK No character available.
904 * Returns a character from the console device. If no character is
905 * available then an EWOULDBLOCK error is returned. If a character is
906 * available, then the returned status is EOK and the character value
909 * A virtual BREAK is represented by the 64-bit value -1.
911 * A virtual HUP signal is represented by the 64-bit value -2.
913 #define HV_FAST_CONS_GETCHAR 0x60
917 * FUNCTION: HV_FAST_CONS_PUTCHAR
920 * ERRORS: EINVAL Illegal character
921 * EWOULDBLOCK Output buffer currently full, would block
923 * Send a character to the console device. Only character values
924 * between 0 and 255 may be used. Values outside this range are
925 * invalid except for the 64-bit value -1 which is used to send a
928 #define HV_FAST_CONS_PUTCHAR 0x61
930 /* Trap trace services.
932 * The hypervisor provides a trap tracing capability for privileged
933 * code running on each virtual CPU. Privileged code provides a
934 * round-robin trap trace queue within which the hypervisor writes
935 * 64-byte entries detailing hyperprivileged traps taken n behalf of
936 * privileged code. This is provided as a debugging capability for
939 * The trap trace control structure is 64-bytes long and placed at the
940 * start (offset 0) of the trap trace buffer, and is described as
944 struct hv_trap_trace_control {
945 unsigned long head_offset;
946 unsigned long tail_offset;
947 unsigned long __reserved[0x30 / sizeof(unsigned long)];
950 #define HV_TRAP_TRACE_CTRL_HEAD_OFFSET 0x00
951 #define HV_TRAP_TRACE_CTRL_TAIL_OFFSET 0x08
953 /* The head offset is the offset of the most recently completed entry
954 * in the trap-trace buffer. The tail offset is the offset of the
955 * next entry to be written. The control structure is owned and
956 * modified by the hypervisor. A guest may not modify the control
957 * structure contents. Attempts to do so will result in undefined
958 * behavior for the guest.
960 * Each trap trace buffer entry is layed out as follows:
963 struct hv_trap_trace_entry {
964 unsigned char type; /* Hypervisor or guest entry? */
965 unsigned char hpstate; /* Hyper-privileged state */
966 unsigned char tl; /* Trap level */
967 unsigned char gl; /* Global register level */
968 unsigned short tt; /* Trap type */
969 unsigned short tag; /* Extended trap identifier */
970 unsigned long tstate; /* Trap state */
971 unsigned long tick; /* Tick */
972 unsigned long tpc; /* Trap PC */
973 unsigned long f1; /* Entry specific */
974 unsigned long f2; /* Entry specific */
975 unsigned long f3; /* Entry specific */
976 unsigned long f4; /* Entry specific */
979 #define HV_TRAP_TRACE_ENTRY_TYPE 0x00
980 #define HV_TRAP_TRACE_ENTRY_HPSTATE 0x01
981 #define HV_TRAP_TRACE_ENTRY_TL 0x02
982 #define HV_TRAP_TRACE_ENTRY_GL 0x03
983 #define HV_TRAP_TRACE_ENTRY_TT 0x04
984 #define HV_TRAP_TRACE_ENTRY_TAG 0x06
985 #define HV_TRAP_TRACE_ENTRY_TSTATE 0x08
986 #define HV_TRAP_TRACE_ENTRY_TICK 0x10
987 #define HV_TRAP_TRACE_ENTRY_TPC 0x18
988 #define HV_TRAP_TRACE_ENTRY_F1 0x20
989 #define HV_TRAP_TRACE_ENTRY_F2 0x28
990 #define HV_TRAP_TRACE_ENTRY_F3 0x30
991 #define HV_TRAP_TRACE_ENTRY_F4 0x38
993 /* The type field is encoded as follows. */
994 #define HV_TRAP_TYPE_UNDEF 0x00 /* Entry content undefined */
995 #define HV_TRAP_TYPE_HV 0x01 /* Hypervisor trap entry */
996 #define HV_TRAP_TYPE_GUEST 0xff /* Added via ttrace_addentry() */
1000 * FUNCTION: HV_FAST_TTRACE_BUF_CONF
1001 * ARG0: real address
1002 * ARG1: number of entries
1004 * RET1: number of entries
1005 * ERRORS: ENORADDR Invalid real address
1006 * EINVAL Size is too small
1007 * EBADALIGN Real address not aligned on 64-byte boundary
1009 * Requests hypervisor trap tracing and declares a virtual CPU's trap
1010 * trace buffer to the hypervisor. The real address supplies the real
1011 * base address of the trap trace queue and must be 64-byte aligned.
1012 * Specifying a value of 0 for the number of entries disables trap
1013 * tracing for the calling virtual CPU. The buffer allocated must be
1014 * sized for a power of two number of 64-byte trap trace entries plus
1015 * an initial 64-byte control structure.
1017 * This may be invoked any number of times so that a virtual CPU may
1018 * relocate a trap trace buffer or create "snapshots" of information.
1020 * If the real address is illegal or badly aligned, then trap tracing
1021 * is disabled and an error is returned.
1023 * Upon failure with EINVAL, this service call returns in RET1 the
1024 * minimum number of buffer entries required. Upon other failures
1025 * RET1 is undefined.
1027 #define HV_FAST_TTRACE_BUF_CONF 0x90
1029 /* ttrace_buf_info()
1030 * TRAP: HV_FAST_TRAP
1031 * FUNCTION: HV_FAST_TTRACE_BUF_INFO
1033 * RET1: real address
1035 * ERRORS: None defined.
1037 * Returns the size and location of the previously declared trap-trace
1038 * buffer. In the event that no buffer was previously defined, or the
1039 * buffer is disabled, this call will return a size of zero bytes.
1041 #define HV_FAST_TTRACE_BUF_INFO 0x91
1044 * TRAP: HV_FAST_TRAP
1045 * FUNCTION: HV_FAST_TTRACE_ENABLE
1048 * RET1: previous enable state
1049 * ERRORS: EINVAL No trap trace buffer currently defined
1051 * Enable or disable trap tracing, and return the previous enabled
1052 * state in RET1. Future systems may define various flags for the
1053 * enable argument (ARG0), for the moment a guest should pass
1054 * "(uint64_t) -1" to enable, and "(uint64_t) 0" to disable all
1055 * tracing - which will ensure future compatability.
1057 #define HV_FAST_TTRACE_ENABLE 0x92
1060 * TRAP: HV_FAST_TRAP
1061 * FUNCTION: HV_FAST_TTRACE_FREEZE
1064 * RET1: previous freeze state
1065 * ERRORS: EINVAL No trap trace buffer currently defined
1067 * Freeze or unfreeze trap tracing, returning the previous freeze
1068 * state in RET1. A guest should pass a non-zero value to freeze and
1069 * a zero value to unfreeze all tracing. The returned previous state
1070 * is 0 for not frozen and 1 for frozen.
1072 #define HV_FAST_TTRACE_FREEZE 0x93
1074 /* ttrace_addentry()
1075 * TRAP: HV_TTRACE_ADDENTRY_TRAP
1076 * ARG0: tag (16-bits)
1082 * ERRORS: EINVAL No trap trace buffer currently defined
1084 * Add an entry to the trap trace buffer. Upon return only ARG0/RET0
1085 * is modified - none of the other registers holding arguments are
1086 * volatile across this hypervisor service.
1089 /* Core dump services.
1091 * Since the hypervisor viraulizes and thus obscures a lot of the
1092 * physical machine layout and state, traditional OS crash dumps can
1093 * be difficult to diagnose especially when the problem is a
1094 * configuration error of some sort.
1096 * The dump services provide an opaque buffer into which the
1097 * hypervisor can place it's internal state in order to assist in
1098 * debugging such situations. The contents are opaque and extremely
1099 * platform and hypervisor implementation specific. The guest, during
1100 * a core dump, requests that the hypervisor update any information in
1101 * the dump buffer in preparation to being dumped as part of the
1102 * domain's memory image.
1105 /* dump_buf_update()
1106 * TRAP: HV_FAST_TRAP
1107 * FUNCTION: HV_FAST_DUMP_BUF_UPDATE
1108 * ARG0: real address
1111 * RET1: required size of dump buffer
1112 * ERRORS: ENORADDR Invalid real address
1113 * EBADALIGN Real address is not aligned on a 64-byte
1115 * EINVAL Size is non-zero but less than minimum size
1117 * ENOTSUPPORTED Operation not supported on current logical
1120 * Declare a domain dump buffer to the hypervisor. The real address
1121 * provided for the domain dump buffer must be 64-byte aligned. The
1122 * size specifies the size of the dump buffer and may be larger than
1123 * the minimum size specified in the machine description. The
1124 * hypervisor will fill the dump buffer with opaque data.
1126 * Note: A guest may elect to include dump buffer contents as part of a crash
1127 * dump to assist with debugging. This function may be called any number
1128 * of times so that a guest may relocate a dump buffer, or create
1129 * "snapshots" of any dump-buffer information. Each call to
1130 * dump_buf_update() atomically declares the new dump buffer to the
1133 * A specified size of 0 unconfigures the dump buffer. If the real
1134 * address is illegal or badly aligned, then any currently active dump
1135 * buffer is disabled and an error is returned.
1137 * In the event that the call fails with EINVAL, RET1 contains the
1138 * minimum size requires by the hypervisor for a valid dump buffer.
1140 #define HV_FAST_DUMP_BUF_UPDATE 0x94
1143 * TRAP: HV_FAST_TRAP
1144 * FUNCTION: HV_FAST_DUMP_BUF_INFO
1146 * RET1: real address of current dump buffer
1147 * RET2: size of current dump buffer
1148 * ERRORS: No errors defined.
1150 * Return the currently configures dump buffer description. A
1151 * returned size of 0 bytes indicates an undefined dump buffer. In
1152 * this case the return address in RET1 is undefined.
1154 #define HV_FAST_DUMP_BUF_INFO 0x95
1156 /* Device interrupt services.
1158 * Device interrupts are allocated to system bus bridges by the hypervisor,
1159 * and described to OBP in the machine description. OBP then describes
1160 * these interrupts to the OS via properties in the device tree.
1164 * cpuid Unique opaque value which represents a target cpu.
1166 * devhandle Device handle. It uniquely identifies a device, and
1167 * consistes of the lower 28-bits of the hi-cell of the
1168 * first entry of the device's "reg" property in the
1171 * devino Device interrupt number. Specifies the relative
1172 * interrupt number within the device. The unique
1173 * combination of devhandle and devino are used to
1174 * identify a specific device interrupt.
1176 * Note: The devino value is the same as the values in the
1177 * "interrupts" property or "interrupt-map" property
1178 * in the OBP device tree for that device.
1180 * sysino System interrupt number. A 64-bit unsigned interger
1181 * representing a unique interrupt within a virtual
1184 * intr_state A flag representing the interrupt state for a given
1185 * sysino. The state values are defined below.
1187 * intr_enabled A flag representing the 'enabled' state for a given
1188 * sysino. The enable values are defined below.
1191 #define HV_INTR_STATE_IDLE 0 /* Nothing pending */
1192 #define HV_INTR_STATE_RECEIVED 1 /* Interrupt received by hardware */
1193 #define HV_INTR_STATE_DELIVERED 2 /* Interrupt delivered to queue */
1195 #define HV_INTR_DISABLED 0 /* sysino not enabled */
1196 #define HV_INTR_ENABLED 1 /* sysino enabled */
1198 /* intr_devino_to_sysino()
1199 * TRAP: HV_FAST_TRAP
1200 * FUNCTION: HV_FAST_INTR_DEVINO2SYSINO
1205 * ERRORS: EINVAL Invalid devhandle/devino
1207 * Converts a device specific interrupt number of the given
1208 * devhandle/devino into a system specific ino (sysino).
1210 #define HV_FAST_INTR_DEVINO2SYSINO 0xa0
1212 #ifndef __ASSEMBLY__
1213 extern unsigned long sun4v_devino_to_sysino(unsigned long devhandle,
1214 unsigned long devino);
1217 /* intr_getenabled()
1218 * TRAP: HV_FAST_TRAP
1219 * FUNCTION: HV_FAST_INTR_GETENABLED
1222 * RET1: intr_enabled (HV_INTR_{DISABLED,ENABLED})
1223 * ERRORS: EINVAL Invalid sysino
1225 * Returns interrupt enabled state in RET1 for the interrupt defined
1226 * by the given sysino.
1228 #define HV_FAST_INTR_GETENABLED 0xa1
1230 #ifndef __ASSEMBLY__
1231 extern unsigned long sun4v_intr_getenabled(unsigned long sysino);
1234 /* intr_setenabled()
1235 * TRAP: HV_FAST_TRAP
1236 * FUNCTION: HV_FAST_INTR_SETENABLED
1238 * ARG1: intr_enabled (HV_INTR_{DISABLED,ENABLED})
1240 * ERRORS: EINVAL Invalid sysino or intr_enabled value
1242 * Set the 'enabled' state of the interrupt sysino.
1244 #define HV_FAST_INTR_SETENABLED 0xa2
1246 #ifndef __ASSEMBLY__
1247 extern unsigned long sun4v_intr_setenabled(unsigned long sysino, unsigned long intr_enabled);
1251 * TRAP: HV_FAST_TRAP
1252 * FUNCTION: HV_FAST_INTR_GETSTATE
1255 * RET1: intr_state (HV_INTR_STATE_*)
1256 * ERRORS: EINVAL Invalid sysino
1258 * Returns current state of the interrupt defined by the given sysino.
1260 #define HV_FAST_INTR_GETSTATE 0xa3
1262 #ifndef __ASSEMBLY__
1263 extern unsigned long sun4v_intr_getstate(unsigned long sysino);
1267 * TRAP: HV_FAST_TRAP
1268 * FUNCTION: HV_FAST_INTR_SETSTATE
1270 * ARG1: intr_state (HV_INTR_STATE_*)
1272 * ERRORS: EINVAL Invalid sysino or intr_state value
1274 * Sets the current state of the interrupt described by the given sysino
1277 * Note: Setting the state to HV_INTR_STATE_IDLE clears any pending
1278 * interrupt for sysino.
1280 #define HV_FAST_INTR_SETSTATE 0xa4
1282 #ifndef __ASSEMBLY__
1283 extern unsigned long sun4v_intr_setstate(unsigned long sysino, unsigned long intr_state);
1287 * TRAP: HV_FAST_TRAP
1288 * FUNCTION: HV_FAST_INTR_GETTARGET
1292 * ERRORS: EINVAL Invalid sysino
1294 * Returns CPU that is the current target of the interrupt defined by
1295 * the given sysino. The CPU value returned is undefined if the target
1296 * has not been set via intr_settarget().
1298 #define HV_FAST_INTR_GETTARGET 0xa5
1300 #ifndef __ASSEMBLY__
1301 extern unsigned long sun4v_intr_gettarget(unsigned long sysino);
1305 * TRAP: HV_FAST_TRAP
1306 * FUNCTION: HV_FAST_INTR_SETTARGET
1310 * ERRORS: EINVAL Invalid sysino
1311 * ENOCPU Invalid cpuid
1313 * Set the target CPU for the interrupt defined by the given sysino.
1315 #define HV_FAST_INTR_SETTARGET 0xa6
1317 #ifndef __ASSEMBLY__
1318 extern unsigned long sun4v_intr_settarget(unsigned long sysino, unsigned long cpuid);
1323 * See the terminology descriptions in the device interrupt services
1324 * section above as those apply here too. Here are terminology
1325 * definitions specific to these PCI IO services:
1327 * tsbnum TSB number. Indentifies which io-tsb is used.
1328 * For this version of the specification, tsbnum
1331 * tsbindex TSB index. Identifies which entry in the TSB
1332 * is used. The first entry is zero.
1334 * tsbid A 64-bit aligned data structure which contains
1335 * a tsbnum and a tsbindex. Bits 63:32 contain the
1336 * tsbnum and bits 31:00 contain the tsbindex.
1338 * Use the HV_PCI_TSBID() macro to construct such
1341 * io_attributes IO attributes for IOMMU mappings. One of more
1342 * of the attritbute bits are stores in a 64-bit
1343 * value. The values are defined below.
1345 * r_addr 64-bit real address
1347 * pci_device PCI device address. A PCI device address identifies
1348 * a specific device on a specific PCI bus segment.
1349 * A PCI device address ia a 32-bit unsigned integer
1350 * with the following format:
1352 * 00000000.bbbbbbbb.dddddfff.00000000
1354 * Use the HV_PCI_DEVICE_BUILD() macro to construct
1358 * PCI configureation space offset. For conventional
1359 * PCI a value between 0 and 255. For extended
1360 * configuration space, a value between 0 and 4095.
1362 * Note: For PCI configuration space accesses, the offset
1363 * must be aligned to the access size.
1365 * error_flag A return value which specifies if the action succeeded
1366 * or failed. 0 means no error, non-0 means some error
1367 * occurred while performing the service.
1370 * Direction definition for pci_dma_sync(), defined
1371 * below in HV_PCI_SYNC_*.
1373 * io_page_list A list of io_page_addresses, an io_page_address is
1376 * io_page_list_p A pointer to an io_page_list.
1378 * "size based byte swap" - Some functions do size based byte swapping
1379 * which allows sw to access pointers and
1380 * counters in native form when the processor
1381 * operates in a different endianness than the
1382 * IO bus. Size-based byte swapping converts a
1383 * multi-byte field between big-endian and
1384 * little-endian format.
1387 #define HV_PCI_MAP_ATTR_READ 0x01
1388 #define HV_PCI_MAP_ATTR_WRITE 0x02
1390 #define HV_PCI_DEVICE_BUILD(b,d,f) \
1391 ((((b) & 0xff) << 16) | \
1392 (((d) & 0x1f) << 11) | \
1393 (((f) & 0x07) << 8))
1395 #define HV_PCI_TSBID(__tsb_num, __tsb_index) \
1396 ((((u64)(__tsb_num)) << 32UL) | ((u64)(__tsb_index)))
1398 #define HV_PCI_SYNC_FOR_DEVICE 0x01
1399 #define HV_PCI_SYNC_FOR_CPU 0x02
1402 * TRAP: HV_FAST_TRAP
1403 * FUNCTION: HV_FAST_PCI_IOMMU_MAP
1407 * ARG3: io_attributes
1408 * ARG4: io_page_list_p
1410 * RET1: #ttes mapped
1411 * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex/io_attributes
1412 * EBADALIGN Improperly aligned real address
1413 * ENORADDR Invalid real address
1415 * Create IOMMU mappings in the sun4v device defined by the given
1416 * devhandle. The mappings are created in the TSB defined by the
1417 * tsbnum component of the given tsbid. The first mapping is created
1418 * in the TSB i ndex defined by the tsbindex component of the given tsbid.
1419 * The call creates up to #ttes mappings, the first one at tsbnum, tsbindex,
1420 * the second at tsbnum, tsbindex + 1, etc.
1422 * All mappings are created with the attributes defined by the io_attributes
1423 * argument. The page mapping addresses are described in the io_page_list
1424 * defined by the given io_page_list_p, which is a pointer to the io_page_list.
1425 * The first entry in the io_page_list is the address for the first iotte, the
1426 * 2nd for the 2nd iotte, and so on.
1428 * Each io_page_address in the io_page_list must be appropriately aligned.
1429 * #ttes must be greater than zero. For this version of the spec, the tsbnum
1430 * component of the given tsbid must be zero.
1432 * Returns the actual number of mappings creates, which may be less than
1433 * or equal to the argument #ttes. If the function returns a value which
1434 * is less than the #ttes, the caller may continus to call the function with
1435 * an updated tsbid, #ttes, io_page_list_p arguments until all pages are
1438 * Note: This function does not imply an iotte cache flush. The guest must
1439 * demap an entry before re-mapping it.
1441 #define HV_FAST_PCI_IOMMU_MAP 0xb0
1443 /* pci_iommu_demap()
1444 * TRAP: HV_FAST_TRAP
1445 * FUNCTION: HV_FAST_PCI_IOMMU_DEMAP
1450 * RET1: #ttes demapped
1451 * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex
1453 * Demap and flush IOMMU mappings in the device defined by the given
1454 * devhandle. Demaps up to #ttes entries in the TSB defined by the tsbnum
1455 * component of the given tsbid, starting at the TSB index defined by the
1456 * tsbindex component of the given tsbid.
1458 * For this version of the spec, the tsbnum of the given tsbid must be zero.
1459 * #ttes must be greater than zero.
1461 * Returns the actual number of ttes demapped, which may be less than or equal
1462 * to the argument #ttes. If #ttes demapped is less than #ttes, the caller
1463 * may continue to call this function with updated tsbid and #ttes arguments
1464 * until all pages are demapped.
1466 * Note: Entries do not have to be mapped to be demapped. A demap of an
1467 * unmapped page will flush the entry from the tte cache.
1469 #define HV_FAST_PCI_IOMMU_DEMAP 0xb1
1471 /* pci_iommu_getmap()
1472 * TRAP: HV_FAST_TRAP
1473 * FUNCTION: HV_FAST_PCI_IOMMU_GETMAP
1477 * RET1: io_attributes
1478 * RET2: real address
1479 * ERRORS: EINVAL Invalid devhandle/tsbnum/tsbindex
1480 * ENOMAP Mapping is not valid, no translation exists
1482 * Read and return the mapping in the device described by the given devhandle
1483 * and tsbid. If successful, the io_attributes shall be returned in RET1
1484 * and the page address of the mapping shall be returned in RET2.
1486 * For this version of the spec, the tsbnum component of the given tsbid
1489 #define HV_FAST_PCI_IOMMU_GETMAP 0xb2
1491 /* pci_iommu_getbypass()
1492 * TRAP: HV_FAST_TRAP
1493 * FUNCTION: HV_FAST_PCI_IOMMU_GETBYPASS
1495 * ARG1: real address
1496 * ARG2: io_attributes
1499 * ERRORS: EINVAL Invalid devhandle/io_attributes
1500 * ENORADDR Invalid real address
1501 * ENOTSUPPORTED Function not supported in this implementation.
1503 * Create a "special" mapping in the device described by the given devhandle,
1504 * for the given real address and attributes. Return the IO address in RET1
1507 #define HV_FAST_PCI_IOMMU_GETBYPASS 0xb3
1510 * TRAP: HV_FAST_TRAP
1511 * FUNCTION: HV_FAST_PCI_CONFIG_GET
1514 * ARG2: pci_config_offset
1519 * ERRORS: EINVAL Invalid devhandle/pci_device/offset/size
1520 * EBADALIGN pci_config_offset not size aligned
1521 * ENOACCESS Access to this offset is not permitted
1523 * Read PCI configuration space for the adapter described by the given
1524 * devhandle. Read size (1, 2, or 4) bytes of data from the given
1525 * pci_device, at pci_config_offset from the beginning of the device's
1526 * configuration space. If there was no error, RET1 is set to zero and
1527 * RET2 is set to the data read. Insignificant bits in RET2 are not
1528 * guarenteed to have any specific value and therefore must be ignored.
1530 * The data returned in RET2 is size based byte swapped.
1532 * If an error occurs during the read, set RET1 to a non-zero value. The
1533 * given pci_config_offset must be 'size' aligned.
1535 #define HV_FAST_PCI_CONFIG_GET 0xb4
1538 * TRAP: HV_FAST_TRAP
1539 * FUNCTION: HV_FAST_PCI_CONFIG_PUT
1542 * ARG2: pci_config_offset
1547 * ERRORS: EINVAL Invalid devhandle/pci_device/offset/size
1548 * EBADALIGN pci_config_offset not size aligned
1549 * ENOACCESS Access to this offset is not permitted
1551 * Write PCI configuration space for the adapter described by the given
1552 * devhandle. Write size (1, 2, or 4) bytes of data in a single operation,
1553 * at pci_config_offset from the beginning of the device's configuration
1554 * space. The data argument contains the data to be written to configuration
1555 * space. Prior to writing, the data is size based byte swapped.
1557 * If an error occurs during the write access, do not generate an error
1558 * report, do set RET1 to a non-zero value. Otherwise RET1 is zero.
1559 * The given pci_config_offset must be 'size' aligned.
1561 * This function is permitted to read from offset zero in the configuration
1562 * space described by the given pci_device if necessary to ensure that the
1563 * write access to config space completes.
1565 #define HV_FAST_PCI_CONFIG_PUT 0xb5
1568 * TRAP: HV_FAST_TRAP
1569 * FUNCTION: HV_FAST_PCI_PEEK
1571 * ARG1: real address
1576 * ERRORS: EINVAL Invalid devhandle or size
1577 * EBADALIGN Improperly aligned real address
1578 * ENORADDR Bad real address
1579 * ENOACCESS Guest access prohibited
1581 * Attempt to read the IO address given by the given devhandle, real address,
1582 * and size. Size must be 1, 2, 4, or 8. The read is performed as a single
1583 * access operation using the given size. If an error occurs when reading
1584 * from the given location, do not generate an error report, but return a
1585 * non-zero value in RET1. If the read was successful, return zero in RET1
1586 * and return the actual data read in RET2. The data returned is size based
1589 * Non-significant bits in RET2 are not guarenteed to have any specific value
1590 * and therefore must be ignored. If RET1 is returned as non-zero, the data
1591 * value is not guarenteed to have any specific value and should be ignored.
1593 * The caller must have permission to read from the given devhandle, real
1594 * address, which must be an IO address. The argument real address must be a
1595 * size aligned address.
1597 * The hypervisor implementation of this function must block access to any
1598 * IO address that the guest does not have explicit permission to access.
1600 #define HV_FAST_PCI_PEEK 0xb6
1603 * TRAP: HV_FAST_TRAP
1604 * FUNCTION: HV_FAST_PCI_POKE
1606 * ARG1: real address
1612 * ERRORS: EINVAL Invalid devhandle, size, or pci_device
1613 * EBADALIGN Improperly aligned real address
1614 * ENORADDR Bad real address
1615 * ENOACCESS Guest access prohibited
1616 * ENOTSUPPORTED Function is not supported by implementation
1618 * Attempt to write data to the IO address given by the given devhandle,
1619 * real address, and size. Size must be 1, 2, 4, or 8. The write is
1620 * performed as a single access operation using the given size. Prior to
1621 * writing the data is size based swapped.
1623 * If an error occurs when writing to the given location, do not generate an
1624 * error report, but return a non-zero value in RET1. If the write was
1625 * successful, return zero in RET1.
1627 * pci_device describes the configuration address of the device being
1628 * written to. The implementation may safely read from offset 0 with
1629 * the configuration space of the device described by devhandle and
1630 * pci_device in order to guarantee that the write portion of the operation
1633 * Any error that occurs due to the read shall be reported using the normal
1634 * error reporting mechanisms .. the read error is not suppressed.
1636 * The caller must have permission to write to the given devhandle, real
1637 * address, which must be an IO address. The argument real address must be a
1638 * size aligned address. The caller must have permission to read from
1639 * the given devhandle, pci_device cofiguration space offset 0.
1641 * The hypervisor implementation of this function must block access to any
1642 * IO address that the guest does not have explicit permission to access.
1644 #define HV_FAST_PCI_POKE 0xb7
1647 * TRAP: HV_FAST_TRAP
1648 * FUNCTION: HV_FAST_PCI_DMA_SYNC
1650 * ARG1: real address
1652 * ARG3: io_sync_direction
1655 * ERRORS: EINVAL Invalid devhandle or io_sync_direction
1656 * ENORADDR Bad real address
1658 * Synchronize a memory region described by the given real address and size,
1659 * for the device defined by the given devhandle using the direction(s)
1660 * defined by the given io_sync_direction. The argument size is the size of
1661 * the memory region in bytes.
1663 * Return the actual number of bytes synchronized in the return value #synced,
1664 * which may be less than or equal to the argument size. If the return
1665 * value #synced is less than size, the caller must continue to call this
1666 * function with updated real address and size arguments until the entire
1667 * memory region is synchronized.
1669 #define HV_FAST_PCI_DMA_SYNC 0xb8
1671 /* PCI MSI services. */
1673 #define HV_MSITYPE_MSI32 0x00
1674 #define HV_MSITYPE_MSI64 0x01
1676 #define HV_MSIQSTATE_IDLE 0x00
1677 #define HV_MSIQSTATE_ERROR 0x01
1679 #define HV_MSIQ_INVALID 0x00
1680 #define HV_MSIQ_VALID 0x01
1682 #define HV_MSISTATE_IDLE 0x00
1683 #define HV_MSISTATE_DELIVERED 0x01
1685 #define HV_MSIVALID_INVALID 0x00
1686 #define HV_MSIVALID_VALID 0x01
1688 #define HV_PCIE_MSGTYPE_PME_MSG 0x18
1689 #define HV_PCIE_MSGTYPE_PME_ACK_MSG 0x1b
1690 #define HV_PCIE_MSGTYPE_CORR_MSG 0x30
1691 #define HV_PCIE_MSGTYPE_NONFATAL_MSG 0x31
1692 #define HV_PCIE_MSGTYPE_FATAL_MSG 0x33
1694 #define HV_MSG_INVALID 0x00
1695 #define HV_MSG_VALID 0x01
1698 * TRAP: HV_FAST_TRAP
1699 * FUNCTION: HV_FAST_PCI_MSIQ_CONF
1702 * ARG2: real address
1703 * ARG3: number of entries
1705 * ERRORS: EINVAL Invalid devhandle, msiqid or nentries
1706 * EBADALIGN Improperly aligned real address
1707 * ENORADDR Bad real address
1709 * Configure the MSI queue given by the devhandle and msiqid arguments,
1710 * and to be placed at the given real address and be of the given
1711 * number of entries. The real address must be aligned exactly to match
1712 * the queue size. Each queue entry is 64-bytes long, so f.e. a 32 entry
1713 * queue must be aligned on a 2048 byte real address boundary. The MSI-EQ
1714 * Head and Tail are initialized so that the MSI-EQ is 'empty'.
1716 * Implementation Note: Certain implementations have fixed sized queues. In
1717 * that case, number of entries must contain the correct
1720 #define HV_FAST_PCI_MSIQ_CONF 0xc0
1723 * TRAP: HV_FAST_TRAP
1724 * FUNCTION: HV_FAST_PCI_MSIQ_INFO
1728 * RET1: real address
1729 * RET2: number of entries
1730 * ERRORS: EINVAL Invalid devhandle or msiqid
1732 * Return the configuration information for the MSI queue described
1733 * by the given devhandle and msiqid. The base address of the queue
1734 * is returned in ARG1 and the number of entries is returned in ARG2.
1735 * If the queue is unconfigured, the real address is undefined and the
1736 * number of entries will be returned as zero.
1738 #define HV_FAST_PCI_MSIQ_INFO 0xc1
1740 /* pci_msiq_getvalid()
1741 * TRAP: HV_FAST_TRAP
1742 * FUNCTION: HV_FAST_PCI_MSIQ_GETVALID
1746 * RET1: msiqvalid (HV_MSIQ_VALID or HV_MSIQ_INVALID)
1747 * ERRORS: EINVAL Invalid devhandle or msiqid
1749 * Get the valid state of the MSI-EQ described by the given devhandle and
1752 #define HV_FAST_PCI_MSIQ_GETVALID 0xc2
1754 /* pci_msiq_setvalid()
1755 * TRAP: HV_FAST_TRAP
1756 * FUNCTION: HV_FAST_PCI_MSIQ_SETVALID
1759 * ARG2: msiqvalid (HV_MSIQ_VALID or HV_MSIQ_INVALID)
1761 * ERRORS: EINVAL Invalid devhandle or msiqid or msiqvalid
1762 * value or MSI EQ is uninitialized
1764 * Set the valid state of the MSI-EQ described by the given devhandle and
1765 * msiqid to the given msiqvalid.
1767 #define HV_FAST_PCI_MSIQ_SETVALID 0xc3
1769 /* pci_msiq_getstate()
1770 * TRAP: HV_FAST_TRAP
1771 * FUNCTION: HV_FAST_PCI_MSIQ_GETSTATE
1775 * RET1: msiqstate (HV_MSIQSTATE_IDLE or HV_MSIQSTATE_ERROR)
1776 * ERRORS: EINVAL Invalid devhandle or msiqid
1778 * Get the state of the MSI-EQ described by the given devhandle and
1781 #define HV_FAST_PCI_MSIQ_GETSTATE 0xc4
1783 /* pci_msiq_getvalid()
1784 * TRAP: HV_FAST_TRAP
1785 * FUNCTION: HV_FAST_PCI_MSIQ_GETVALID
1788 * ARG2: msiqstate (HV_MSIQSTATE_IDLE or HV_MSIQSTATE_ERROR)
1790 * ERRORS: EINVAL Invalid devhandle or msiqid or msiqstate
1791 * value or MSI EQ is uninitialized
1793 * Set the state of the MSI-EQ described by the given devhandle and
1794 * msiqid to the given msiqvalid.
1796 #define HV_FAST_PCI_MSIQ_SETSTATE 0xc5
1798 /* pci_msiq_gethead()
1799 * TRAP: HV_FAST_TRAP
1800 * FUNCTION: HV_FAST_PCI_MSIQ_GETHEAD
1805 * ERRORS: EINVAL Invalid devhandle or msiqid
1807 * Get the current MSI EQ queue head for the MSI-EQ described by the
1808 * given devhandle and msiqid.
1810 #define HV_FAST_PCI_MSIQ_GETHEAD 0xc6
1812 /* pci_msiq_sethead()
1813 * TRAP: HV_FAST_TRAP
1814 * FUNCTION: HV_FAST_PCI_MSIQ_SETHEAD
1819 * ERRORS: EINVAL Invalid devhandle or msiqid or msiqhead,
1820 * or MSI EQ is uninitialized
1822 * Set the current MSI EQ queue head for the MSI-EQ described by the
1823 * given devhandle and msiqid.
1825 #define HV_FAST_PCI_MSIQ_SETHEAD 0xc7
1827 /* pci_msiq_gettail()
1828 * TRAP: HV_FAST_TRAP
1829 * FUNCTION: HV_FAST_PCI_MSIQ_GETTAIL
1834 * ERRORS: EINVAL Invalid devhandle or msiqid
1836 * Get the current MSI EQ queue tail for the MSI-EQ described by the
1837 * given devhandle and msiqid.
1839 #define HV_FAST_PCI_MSIQ_GETTAIL 0xc8
1841 /* pci_msi_getvalid()
1842 * TRAP: HV_FAST_TRAP
1843 * FUNCTION: HV_FAST_PCI_MSI_GETVALID
1847 * RET1: msivalidstate
1848 * ERRORS: EINVAL Invalid devhandle or msinum
1850 * Get the current valid/enabled state for the MSI defined by the
1851 * given devhandle and msinum.
1853 #define HV_FAST_PCI_MSI_GETVALID 0xc9
1855 /* pci_msi_setvalid()
1856 * TRAP: HV_FAST_TRAP
1857 * FUNCTION: HV_FAST_PCI_MSI_SETVALID
1860 * ARG2: msivalidstate
1862 * ERRORS: EINVAL Invalid devhandle or msinum or msivalidstate
1864 * Set the current valid/enabled state for the MSI defined by the
1865 * given devhandle and msinum.
1867 #define HV_FAST_PCI_MSI_SETVALID 0xca
1869 /* pci_msi_getmsiq()
1870 * TRAP: HV_FAST_TRAP
1871 * FUNCTION: HV_FAST_PCI_MSI_GETMSIQ
1876 * ERRORS: EINVAL Invalid devhandle or msinum or MSI is unbound
1878 * Get the MSI EQ that the MSI defined by the given devhandle and
1879 * msinum is bound to.
1881 #define HV_FAST_PCI_MSI_GETMSIQ 0xcb
1883 /* pci_msi_setmsiq()
1884 * TRAP: HV_FAST_TRAP
1885 * FUNCTION: HV_FAST_PCI_MSI_SETMSIQ
1891 * ERRORS: EINVAL Invalid devhandle or msinum or msiqid
1893 * Set the MSI EQ that the MSI defined by the given devhandle and
1894 * msinum is bound to.
1896 #define HV_FAST_PCI_MSI_SETMSIQ 0xcc
1898 /* pci_msi_getstate()
1899 * TRAP: HV_FAST_TRAP
1900 * FUNCTION: HV_FAST_PCI_MSI_GETSTATE
1905 * ERRORS: EINVAL Invalid devhandle or msinum
1907 * Get the state of the MSI defined by the given devhandle and msinum.
1908 * If not initialized, return HV_MSISTATE_IDLE.
1910 #define HV_FAST_PCI_MSI_GETSTATE 0xcd
1912 /* pci_msi_setstate()
1913 * TRAP: HV_FAST_TRAP
1914 * FUNCTION: HV_FAST_PCI_MSI_SETSTATE
1919 * ERRORS: EINVAL Invalid devhandle or msinum or msistate
1921 * Set the state of the MSI defined by the given devhandle and msinum.
1923 #define HV_FAST_PCI_MSI_SETSTATE 0xce
1925 /* pci_msg_getmsiq()
1926 * TRAP: HV_FAST_TRAP
1927 * FUNCTION: HV_FAST_PCI_MSG_GETMSIQ
1932 * ERRORS: EINVAL Invalid devhandle or msgtype
1934 * Get the MSI EQ of the MSG defined by the given devhandle and msgtype.
1936 #define HV_FAST_PCI_MSG_GETMSIQ 0xd0
1938 /* pci_msg_setmsiq()
1939 * TRAP: HV_FAST_TRAP
1940 * FUNCTION: HV_FAST_PCI_MSG_SETMSIQ
1945 * ERRORS: EINVAL Invalid devhandle, msgtype, or msiqid
1947 * Set the MSI EQ of the MSG defined by the given devhandle and msgtype.
1949 #define HV_FAST_PCI_MSG_SETMSIQ 0xd1
1951 /* pci_msg_getvalid()
1952 * TRAP: HV_FAST_TRAP
1953 * FUNCTION: HV_FAST_PCI_MSG_GETVALID
1957 * RET1: msgvalidstate
1958 * ERRORS: EINVAL Invalid devhandle or msgtype
1960 * Get the valid/enabled state of the MSG defined by the given
1961 * devhandle and msgtype.
1963 #define HV_FAST_PCI_MSG_GETVALID 0xd2
1965 /* pci_msg_setvalid()
1966 * TRAP: HV_FAST_TRAP
1967 * FUNCTION: HV_FAST_PCI_MSG_SETVALID
1970 * ARG2: msgvalidstate
1972 * ERRORS: EINVAL Invalid devhandle or msgtype or msgvalidstate
1974 * Set the valid/enabled state of the MSG defined by the given
1975 * devhandle and msgtype.
1977 #define HV_FAST_PCI_MSG_SETVALID 0xd3
1979 /* Performance counter services. */
1981 #define HV_PERF_JBUS_PERF_CTRL_REG 0x00
1982 #define HV_PERF_JBUS_PERF_CNT_REG 0x01
1983 #define HV_PERF_DRAM_PERF_CTRL_REG_0 0x02
1984 #define HV_PERF_DRAM_PERF_CNT_REG_0 0x03
1985 #define HV_PERF_DRAM_PERF_CTRL_REG_1 0x04
1986 #define HV_PERF_DRAM_PERF_CNT_REG_1 0x05
1987 #define HV_PERF_DRAM_PERF_CTRL_REG_2 0x06
1988 #define HV_PERF_DRAM_PERF_CNT_REG_2 0x07
1989 #define HV_PERF_DRAM_PERF_CTRL_REG_3 0x08
1990 #define HV_PERF_DRAM_PERF_CNT_REG_3 0x09
1993 * TRAP: HV_FAST_TRAP
1994 * FUNCTION: HV_FAST_GET_PERFREG
1995 * ARG0: performance reg number
1997 * RET1: performance reg value
1998 * ERRORS: EINVAL Invalid performance register number
1999 * ENOACCESS No access allowed to performance counters
2001 * Read the value of the given DRAM/JBUS performance counter/control register.
2003 #define HV_FAST_GET_PERFREG 0x100
2006 * TRAP: HV_FAST_TRAP
2007 * FUNCTION: HV_FAST_SET_PERFREG
2008 * ARG0: performance reg number
2009 * ARG1: performance reg value
2011 * ERRORS: EINVAL Invalid performance register number
2012 * ENOACCESS No access allowed to performance counters
2014 * Write the given performance reg value to the given DRAM/JBUS
2015 * performance counter/control register.
2017 #define HV_FAST_SET_PERFREG 0x101
2019 /* MMU statistics services.
2021 * The hypervisor maintains MMU statistics and privileged code provides
2022 * a buffer where these statistics can be collected. It is continually
2023 * updated once configured. The layout is as follows:
2025 #ifndef __ASSEMBLY__
2026 struct hv_mmu_statistics {
2027 unsigned long immu_tsb_hits_ctx0_8k_tte;
2028 unsigned long immu_tsb_ticks_ctx0_8k_tte;
2029 unsigned long immu_tsb_hits_ctx0_64k_tte;
2030 unsigned long immu_tsb_ticks_ctx0_64k_tte;
2031 unsigned long __reserved1[2];
2032 unsigned long immu_tsb_hits_ctx0_4mb_tte;
2033 unsigned long immu_tsb_ticks_ctx0_4mb_tte;
2034 unsigned long __reserved2[2];
2035 unsigned long immu_tsb_hits_ctx0_256mb_tte;
2036 unsigned long immu_tsb_ticks_ctx0_256mb_tte;
2037 unsigned long __reserved3[4];
2038 unsigned long immu_tsb_hits_ctxnon0_8k_tte;
2039 unsigned long immu_tsb_ticks_ctxnon0_8k_tte;
2040 unsigned long immu_tsb_hits_ctxnon0_64k_tte;
2041 unsigned long immu_tsb_ticks_ctxnon0_64k_tte;
2042 unsigned long __reserved4[2];
2043 unsigned long immu_tsb_hits_ctxnon0_4mb_tte;
2044 unsigned long immu_tsb_ticks_ctxnon0_4mb_tte;
2045 unsigned long __reserved5[2];
2046 unsigned long immu_tsb_hits_ctxnon0_256mb_tte;
2047 unsigned long immu_tsb_ticks_ctxnon0_256mb_tte;
2048 unsigned long __reserved6[4];
2049 unsigned long dmmu_tsb_hits_ctx0_8k_tte;
2050 unsigned long dmmu_tsb_ticks_ctx0_8k_tte;
2051 unsigned long dmmu_tsb_hits_ctx0_64k_tte;
2052 unsigned long dmmu_tsb_ticks_ctx0_64k_tte;
2053 unsigned long __reserved7[2];
2054 unsigned long dmmu_tsb_hits_ctx0_4mb_tte;
2055 unsigned long dmmu_tsb_ticks_ctx0_4mb_tte;
2056 unsigned long __reserved8[2];
2057 unsigned long dmmu_tsb_hits_ctx0_256mb_tte;
2058 unsigned long dmmu_tsb_ticks_ctx0_256mb_tte;
2059 unsigned long __reserved9[4];
2060 unsigned long dmmu_tsb_hits_ctxnon0_8k_tte;
2061 unsigned long dmmu_tsb_ticks_ctxnon0_8k_tte;
2062 unsigned long dmmu_tsb_hits_ctxnon0_64k_tte;
2063 unsigned long dmmu_tsb_ticks_ctxnon0_64k_tte;
2064 unsigned long __reserved10[2];
2065 unsigned long dmmu_tsb_hits_ctxnon0_4mb_tte;
2066 unsigned long dmmu_tsb_ticks_ctxnon0_4mb_tte;
2067 unsigned long __reserved11[2];
2068 unsigned long dmmu_tsb_hits_ctxnon0_256mb_tte;
2069 unsigned long dmmu_tsb_ticks_ctxnon0_256mb_tte;
2070 unsigned long __reserved12[4];
2075 * TRAP: HV_FAST_TRAP
2076 * FUNCTION: HV_FAST_MMUSTAT_CONF
2077 * ARG0: real address
2079 * RET1: real address
2080 * ERRORS: ENORADDR Invalid real address
2081 * EBADALIGN Real address not aligned on 64-byte boundary
2082 * EBADTRAP API not supported on this processor
2084 * Enable MMU statistic gathering using the buffer at the given real
2085 * address on the current virtual CPU. The new buffer real address
2086 * is given in ARG1, and the previously specified buffer real address
2087 * is returned in RET1, or is returned as zero for the first invocation.
2089 * If the passed in real address argument is zero, this will disable
2090 * MMU statistic collection on the current virtual CPU. If an error is
2091 * returned then no statistics are collected.
2093 * The buffer contents should be initialized to all zeros before being
2094 * given to the hypervisor or else the statistics will be meaningless.
2096 #define HV_FAST_MMUSTAT_CONF 0x102
2099 * TRAP: HV_FAST_TRAP
2100 * FUNCTION: HV_FAST_MMUSTAT_INFO
2102 * RET1: real address
2103 * ERRORS: EBADTRAP API not supported on this processor
2105 * Return the current state and real address of the currently configured
2106 * MMU statistics buffer on the current virtual CPU.
2108 #define HV_FAST_MMUSTAT_INFO 0x103
2110 /* Function numbers for HV_CORE_TRAP. */
2111 #define HV_CORE_VER 0x00
2112 #define HV_CORE_PUTCHAR 0x01
2113 #define HV_CORE_EXIT 0x02
2115 #endif /* !(_SPARC64_HYPERVISOR_H) */