1 #ifndef _ASM_X86_APICDEF_H
2 #define _ASM_X86_APICDEF_H
5 * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
7 * Alan Cox <Alan.Cox@linux.org>, 1995.
8 * Ingo Molnar <mingo@redhat.com>, 1999, 2000
11 #define APIC_DEFAULT_PHYS_BASE 0xfee00000
16 # define APIC_ID_MASK (0xFFu<<24)
17 # define GET_APIC_ID(x) (((x)>>24)&0xFFu)
18 # define SET_APIC_ID(x) (((x)<<24))
22 #define APIC_LVR_MASK 0xFF00FF
23 #define GET_APIC_VERSION(x) ((x)&0xFFu)
24 #define GET_APIC_MAXLVT(x) (((x)>>16)&0xFFu)
26 # define APIC_INTEGRATED(x) ((x)&0xF0u)
28 # define APIC_INTEGRATED(x) (1)
30 #define APIC_XAPIC(x) ((x) >= 0x14)
31 #define APIC_TASKPRI 0x80
32 #define APIC_TPRI_MASK 0xFFu
33 #define APIC_ARBPRI 0x90
34 #define APIC_ARBPRI_MASK 0xFFu
35 #define APIC_PROCPRI 0xA0
37 #define APIC_EIO_ACK 0x0
40 #define APIC_LDR_MASK (0xFFu<<24)
41 #define GET_APIC_LOGICAL_ID(x) (((x)>>24)&0xFFu)
42 #define SET_APIC_LOGICAL_ID(x) (((x)<<24))
43 #define APIC_ALL_CPUS 0xFFu
45 #define APIC_DFR_CLUSTER 0x0FFFFFFFul
46 #define APIC_DFR_FLAT 0xFFFFFFFFul
47 #define APIC_SPIV 0xF0
48 #define APIC_SPIV_FOCUS_DISABLED (1<<9)
49 #define APIC_SPIV_APIC_ENABLED (1<<8)
50 #define APIC_ISR 0x100
51 #define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */
52 #define APIC_TMR 0x180
53 #define APIC_IRR 0x200
54 #define APIC_ESR 0x280
55 #define APIC_ESR_SEND_CS 0x00001
56 #define APIC_ESR_RECV_CS 0x00002
57 #define APIC_ESR_SEND_ACC 0x00004
58 #define APIC_ESR_RECV_ACC 0x00008
59 #define APIC_ESR_SENDILL 0x00020
60 #define APIC_ESR_RECVILL 0x00040
61 #define APIC_ESR_ILLREGA 0x00080
62 #define APIC_ICR 0x300
63 #define APIC_DEST_SELF 0x40000
64 #define APIC_DEST_ALLINC 0x80000
65 #define APIC_DEST_ALLBUT 0xC0000
66 #define APIC_ICR_RR_MASK 0x30000
67 #define APIC_ICR_RR_INVALID 0x00000
68 #define APIC_ICR_RR_INPROG 0x10000
69 #define APIC_ICR_RR_VALID 0x20000
70 #define APIC_INT_LEVELTRIG 0x08000
71 #define APIC_INT_ASSERT 0x04000
72 #define APIC_ICR_BUSY 0x01000
73 #define APIC_DEST_LOGICAL 0x00800
74 #define APIC_DEST_PHYSICAL 0x00000
75 #define APIC_DM_FIXED 0x00000
76 #define APIC_DM_LOWEST 0x00100
77 #define APIC_DM_SMI 0x00200
78 #define APIC_DM_REMRD 0x00300
79 #define APIC_DM_NMI 0x00400
80 #define APIC_DM_INIT 0x00500
81 #define APIC_DM_STARTUP 0x00600
82 #define APIC_DM_EXTINT 0x00700
83 #define APIC_VECTOR_MASK 0x000FF
84 #define APIC_ICR2 0x310
85 #define GET_APIC_DEST_FIELD(x) (((x)>>24)&0xFF)
86 #define SET_APIC_DEST_FIELD(x) ((x)<<24)
87 #define APIC_LVTT 0x320
88 #define APIC_LVTTHMR 0x330
89 #define APIC_LVTPC 0x340
90 #define APIC_LVT0 0x350
91 #define APIC_LVT_TIMER_BASE_MASK (0x3<<18)
92 #define GET_APIC_TIMER_BASE(x) (((x)>>18)&0x3)
93 #define SET_APIC_TIMER_BASE(x) (((x)<<18))
94 #define APIC_TIMER_BASE_CLKIN 0x0
95 #define APIC_TIMER_BASE_TMBASE 0x1
96 #define APIC_TIMER_BASE_DIV 0x2
97 #define APIC_LVT_TIMER_PERIODIC (1<<17)
98 #define APIC_LVT_MASKED (1<<16)
99 #define APIC_LVT_LEVEL_TRIGGER (1<<15)
100 #define APIC_LVT_REMOTE_IRR (1<<14)
101 #define APIC_INPUT_POLARITY (1<<13)
102 #define APIC_SEND_PENDING (1<<12)
103 #define APIC_MODE_MASK 0x700
104 #define GET_APIC_DELIVERY_MODE(x) (((x)>>8)&0x7)
105 #define SET_APIC_DELIVERY_MODE(x, y) (((x)&~0x700)|((y)<<8))
106 #define APIC_MODE_FIXED 0x0
107 #define APIC_MODE_NMI 0x4
108 #define APIC_MODE_EXTINT 0x7
109 #define APIC_LVT1 0x360
110 #define APIC_LVTERR 0x370
111 #define APIC_TMICT 0x380
112 #define APIC_TMCCT 0x390
113 #define APIC_TDCR 0x3E0
114 #define APIC_TDR_DIV_TMBASE (1<<2)
115 #define APIC_TDR_DIV_1 0xB
116 #define APIC_TDR_DIV_2 0x0
117 #define APIC_TDR_DIV_4 0x1
118 #define APIC_TDR_DIV_8 0x2
119 #define APIC_TDR_DIV_16 0x3
120 #define APIC_TDR_DIV_32 0x8
121 #define APIC_TDR_DIV_64 0x9
122 #define APIC_TDR_DIV_128 0xA
123 #define APIC_EILVT0 0x500
124 #define APIC_EILVT_NR_AMD_K8 1 /* Number of extended interrupts */
125 #define APIC_EILVT_NR_AMD_10H 4
126 #define APIC_EILVT_LVTOFF(x) (((x)>>4)&0xF)
127 #define APIC_EILVT_MSG_FIX 0x0
128 #define APIC_EILVT_MSG_SMI 0x2
129 #define APIC_EILVT_MSG_NMI 0x4
130 #define APIC_EILVT_MSG_EXT 0x7
131 #define APIC_EILVT_MASKED (1<<16)
132 #define APIC_EILVT1 0x510
133 #define APIC_EILVT2 0x520
134 #define APIC_EILVT3 0x530
136 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
139 # define MAX_IO_APICS 64
141 # define MAX_IO_APICS 128
142 # define MAX_LOCAL_APIC 256
146 * All x86-64 systems are xAPIC compatible.
147 * In the following, "apicid" is a physical APIC ID.
149 #define XAPIC_DEST_CPUS_SHIFT 4
150 #define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
151 #define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
152 #define APIC_CLUSTER(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK)
153 #define APIC_CLUSTERID(apicid) (APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT)
154 #define APIC_CPUID(apicid) ((apicid) & XAPIC_DEST_CPUS_MASK)
155 #define NUM_APIC_CLUSTERS ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT)
158 * the local APIC register structure, memory mapped. Not terribly well
159 * tested, but we might eventually use this one in the future - the
160 * problem why we cannot use it right now is the P5 APIC, it has an
161 * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
163 #define u32 unsigned int
167 /*000*/ struct { u32 __reserved[4]; } __reserved_01;
169 /*010*/ struct { u32 __reserved[4]; } __reserved_02;
171 /*020*/ struct { /* APIC ID Register */
172 u32 __reserved_1 : 24,
179 struct { /* APIC Version Register */
187 /*040*/ struct { u32 __reserved[4]; } __reserved_03;
189 /*050*/ struct { u32 __reserved[4]; } __reserved_04;
191 /*060*/ struct { u32 __reserved[4]; } __reserved_05;
193 /*070*/ struct { u32 __reserved[4]; } __reserved_06;
195 /*080*/ struct { /* Task Priority Register */
202 struct { /* Arbitration Priority Register */
209 struct { /* Processor Priority Register */
215 /*0B0*/ struct { /* End Of Interrupt Register */
220 /*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
222 /*0D0*/ struct { /* Logical Destination Register */
223 u32 __reserved_1 : 24,
228 /*0E0*/ struct { /* Destination Format Register */
229 u32 __reserved_1 : 28,
234 /*0F0*/ struct { /* Spurious Interrupt Vector Register */
235 u32 spurious_vector : 8,
242 /*100*/ struct { /* In Service Register */
243 /*170*/ u32 bitfield;
247 /*180*/ struct { /* Trigger Mode Register */
248 /*1F0*/ u32 bitfield;
252 /*200*/ struct { /* Interrupt Request Register */
253 /*270*/ u32 bitfield;
257 /*280*/ union { /* Error Status Register */
259 u32 send_cs_error : 1,
260 receive_cs_error : 1,
261 send_accept_error : 1,
262 receive_accept_error : 1,
264 send_illegal_vector : 1,
265 receive_illegal_vector : 1,
266 illegal_register_address : 1,
276 /*290*/ struct { u32 __reserved[4]; } __reserved_08;
278 /*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
280 /*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
282 /*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
284 /*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
286 /*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
288 /*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
290 /*300*/ struct { /* Interrupt Command Register 1 */
293 destination_mode : 1,
304 /*310*/ struct { /* Interrupt Command Register 2 */
306 u32 __reserved_1 : 24,
309 u32 __reserved_3 : 24,
315 /*320*/ struct { /* LVT - Timer */
326 /*330*/ struct { /* LVT - Thermal Sensor */
337 /*340*/ struct { /* LVT - Performance Counter */
348 /*350*/ struct { /* LVT - LINT0 */
361 /*360*/ struct { /* LVT - LINT1 */
374 /*370*/ struct { /* LVT - Error */
384 /*380*/ struct { /* Timer Initial Count Register */
390 struct { /* Timer Current Count Register */
395 /*3A0*/ struct { u32 __reserved[4]; } __reserved_16;
397 /*3B0*/ struct { u32 __reserved[4]; } __reserved_17;
399 /*3C0*/ struct { u32 __reserved[4]; } __reserved_18;
401 /*3D0*/ struct { u32 __reserved[4]; } __reserved_19;
403 /*3E0*/ struct { /* Timer Divide Configuration Register */
409 /*3F0*/ struct { u32 __reserved[4]; } __reserved_20;
411 } __attribute__ ((packed));
415 #define BAD_APICID 0xFFu