5 #include <asm/segment.h>
6 #include <asm/desc_defs.h>
10 #include <linux/preempt.h>
11 #include <linux/smp.h>
12 #include <linux/percpu.h>
18 struct desc_struct gdt[GDT_ENTRIES];
19 } __attribute__((aligned(PAGE_SIZE)));
20 DECLARE_PER_CPU(struct gdt_page, gdt_page);
22 static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu)
24 return per_cpu(gdt_page, cpu).gdt;
27 extern struct desc_ptr idt_descr;
28 extern gate_desc idt_table[];
29 extern void set_intr_gate(unsigned int irq, void * addr);
31 static inline void pack_descriptor(struct desc_struct *desc,
32 unsigned long base, unsigned long limit, unsigned char type, unsigned char flags)
34 desc->a = ((base & 0xffff) << 16) | (limit & 0xffff);
35 desc->b = (base & 0xff000000) | ((base & 0xff0000) >> 16) |
36 (limit & 0x000f0000) | ((type & 0xff) << 8) | ((flags & 0xf) << 20);
40 static inline void pack_gate(gate_desc *gate,
41 unsigned long base, unsigned short seg, unsigned char type, unsigned char flags)
43 gate->a = (seg << 16) | (base & 0xffff);
44 gate->b = (base & 0xffff0000) | ((type & 0xff) << 8) | (flags & 0xff);
47 #define DESCTYPE_LDT 0x82 /* present, system, DPL-0, LDT */
48 #define DESCTYPE_TSS 0x89 /* present, system, DPL-0, 32-bit TSS */
49 #define DESCTYPE_TASK 0x85 /* present, system, DPL-0, task gate */
50 #define DESCTYPE_INT 0x8e /* present, system, DPL-0, interrupt gate */
51 #define DESCTYPE_TRAP 0x8f /* present, system, DPL-0, trap gate */
52 #define DESCTYPE_DPL3 0x60 /* DPL-3 */
53 #define DESCTYPE_S 0x10 /* !system */
55 #ifdef CONFIG_PARAVIRT
56 #include <asm/paravirt.h>
58 #define load_TR_desc() native_load_tr_desc()
59 #define load_gdt(dtr) native_load_gdt(dtr)
60 #define load_idt(dtr) native_load_idt(dtr)
61 #define load_tr(tr) __asm__ __volatile("ltr %0"::"m" (tr))
62 #define load_ldt(ldt) __asm__ __volatile("lldt %0"::"m" (ldt))
64 #define store_gdt(dtr) native_store_gdt(dtr)
65 #define store_idt(dtr) native_store_idt(dtr)
66 #define store_tr(tr) (tr = native_store_tr())
67 #define store_ldt(ldt) __asm__ ("sldt %0":"=m" (ldt))
69 #define load_TLS(t, cpu) native_load_tls(t, cpu)
70 #define set_ldt native_set_ldt
72 #define write_ldt_entry(dt, entry, a, b) write_dt_entry(dt, entry, a, b)
73 #define write_gdt_entry(dt, entry, desc, type) \
74 native_write_gdt_entry(dt, entry, desc, type)
75 #define write_idt_entry(dt, entry, g) native_write_idt_entry(dt, entry, g)
78 static inline void native_write_idt_entry(gate_desc *idt, int entry,
79 const gate_desc *gate)
81 memcpy(&idt[entry], gate, sizeof(*gate));
84 static inline void native_write_gdt_entry(struct desc_struct *gdt, int entry,
85 const void *desc, int type)
87 memcpy(&gdt[entry], desc, sizeof(struct desc_struct));
90 static inline void write_dt_entry(struct desc_struct *dt,
91 int entry, u32 entry_low, u32 entry_high)
93 dt[entry].a = entry_low;
94 dt[entry].b = entry_high;
98 static inline void native_set_ldt(const void *addr, unsigned int entries)
100 if (likely(entries == 0))
101 __asm__ __volatile__("lldt %w0"::"q" (0));
103 unsigned cpu = smp_processor_id();
106 pack_descriptor(&ldt, (unsigned long)addr,
107 entries * sizeof(struct desc_struct) - 1,
109 write_gdt_entry(get_cpu_gdt_table(cpu), GDT_ENTRY_LDT,
111 __asm__ __volatile__("lldt %w0"::"q" (GDT_ENTRY_LDT*8));
116 static inline void native_load_tr_desc(void)
118 asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
121 static inline void native_load_gdt(const struct desc_ptr *dtr)
123 asm volatile("lgdt %0"::"m" (*dtr));
126 static inline void native_load_idt(const struct desc_ptr *dtr)
128 asm volatile("lidt %0"::"m" (*dtr));
131 static inline void native_store_gdt(struct desc_ptr *dtr)
133 asm ("sgdt %0":"=m" (*dtr));
136 static inline void native_store_idt(struct desc_ptr *dtr)
138 asm ("sidt %0":"=m" (*dtr));
141 static inline unsigned long native_store_tr(void)
144 asm ("str %0":"=r" (tr));
148 static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)
151 struct desc_struct *gdt = get_cpu_gdt_table(cpu);
153 for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++)
154 gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];
157 static inline void _set_gate(int gate, unsigned int type, void *addr, unsigned short seg)
160 pack_gate(&g, (unsigned long)addr, seg, type, 0);
161 write_idt_entry(idt_table, gate, &g);
164 static inline void __set_tss_desc(unsigned int cpu, unsigned int entry, const void *addr)
167 pack_descriptor(&tss, (unsigned long)addr,
168 offsetof(struct tss_struct, __cacheline_filler) - 1,
170 write_gdt_entry(get_cpu_gdt_table(cpu), entry, &tss, DESC_TSS);
174 #define set_tss_desc(cpu,addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr)
176 #define LDT_empty(info) (\
177 (info)->base_addr == 0 && \
178 (info)->limit == 0 && \
179 (info)->contents == 0 && \
180 (info)->read_exec_only == 1 && \
181 (info)->seg_32bit == 0 && \
182 (info)->limit_in_pages == 0 && \
183 (info)->seg_not_present == 1 && \
184 (info)->useable == 0 )
186 static inline void clear_LDT(void)
192 * load one particular LDT into the current CPU
194 static inline void load_LDT_nolock(mm_context_t *pc)
196 set_ldt(pc->ldt, pc->size);
199 static inline void load_LDT(mm_context_t *pc)
206 static inline unsigned long get_desc_base(unsigned long *desc)
209 base = ((desc[0] >> 16) & 0x0000ffff) |
210 ((desc[1] << 16) & 0x00ff0000) |
211 (desc[1] & 0xff000000);
215 #else /* __ASSEMBLY__ */
218 * GET_DESC_BASE reads the descriptor base of the specified segment.
221 * idx - descriptor index
223 * base - 32bit register to which the base will be written
224 * lo_w - lo word of the "base" register
225 * lo_b - lo byte of the "base" register
226 * hi_b - hi byte of the low word of the "base" register
229 * GET_DESC_BASE(GDT_ENTRY_ESPFIX_SS, %ebx, %eax, %ax, %al, %ah)
230 * Will read the base address of GDT_ENTRY_ESPFIX_SS and put it into %eax.
232 #define GET_DESC_BASE(idx, gdt, base, lo_w, lo_b, hi_b) \
233 movb idx*8+4(gdt), lo_b; \
234 movb idx*8+7(gdt), hi_b; \
236 movw idx*8+2(gdt), lo_w;
238 #endif /* !__ASSEMBLY__ */