1 #ifndef __ASM_X86_PROCESSOR_H
2 #define __ASM_X86_PROCESSOR_H
4 #include <asm/processor-flags.h>
6 /* Forward declaration, a strange C thing */
11 #include <asm/percpu.h>
12 #include <asm/system.h>
15 * Default implementation of macro that returns current
16 * instruction pointer ("program counter").
18 static inline void *current_text_addr(void)
21 asm volatile("mov $1f,%0\n1:":"=r" (pc));
25 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
26 unsigned int *ecx, unsigned int *edx)
28 /* ecx is often an input as well as an output. */
34 : "0" (*eax), "2" (*ecx));
37 static inline void load_cr3(pgd_t *pgdir)
39 write_cr3(__pa(pgdir));
43 /* This is the TSS defined by the hardware. */
45 unsigned short back_link, __blh;
47 unsigned short ss0, __ss0h;
49 unsigned short ss1, __ss1h; /* ss1 caches MSR_IA32_SYSENTER_CS */
51 unsigned short ss2, __ss2h;
55 unsigned long ax, cx, dx, bx;
56 unsigned long sp, bp, si, di;
57 unsigned short es, __esh;
58 unsigned short cs, __csh;
59 unsigned short ss, __ssh;
60 unsigned short ds, __dsh;
61 unsigned short fs, __fsh;
62 unsigned short gs, __gsh;
63 unsigned short ldt, __ldth;
64 unsigned short trace, io_bitmap_base;
65 } __attribute__((packed));
78 } __attribute__((packed)) ____cacheline_aligned;
84 #define IO_BITMAP_BITS 65536
85 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
86 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
87 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
88 #define INVALID_IO_BITMAP_OFFSET 0x8000
89 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
92 struct x86_hw_tss x86_tss;
95 * The extra 1 is there because the CPU will access an
96 * additional byte beyond the end of the IO permission
97 * bitmap. The extra byte must be all 1 bits, and must
98 * be within the limit.
100 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
102 * Cache the current maximum and the last task that used the bitmap:
104 unsigned long io_bitmap_max;
105 struct thread_struct *io_bitmap_owner;
107 * pads the TSS to be cacheline-aligned (size is 0x100)
109 unsigned long __cacheline_filler[35];
111 * .. and then another 0x100 bytes for emergency kernel stack
113 unsigned long stack[64];
114 } __attribute__((packed));
116 DECLARE_PER_CPU(struct tss_struct, init_tss);
119 # include "processor_32.h"
121 # include "processor_64.h"
124 extern void print_cpu_info(struct cpuinfo_x86 *);
125 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
126 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
127 extern unsigned short num_cache_leaves;
129 struct thread_struct {
130 /* cached TLS descriptors. */
131 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
135 unsigned long sysenter_cs;
137 unsigned long usersp; /* Copy from PDA */
138 unsigned short es, ds, fsindex, gsindex;
143 /* Hardware debugging registers */
144 unsigned long debugreg0;
145 unsigned long debugreg1;
146 unsigned long debugreg2;
147 unsigned long debugreg3;
148 unsigned long debugreg6;
149 unsigned long debugreg7;
151 unsigned long cr2, trap_no, error_code;
152 /* floating point info */
153 union i387_union i387 __attribute__((aligned(16)));;
155 /* virtual 86 mode info */
156 struct vm86_struct __user *vm86_info;
157 unsigned long screen_bitmap;
158 unsigned long v86flags, v86mask, saved_sp0;
159 unsigned int saved_fs, saved_gs;
162 unsigned long *io_bitmap_ptr;
164 /* max allowed port in the bitmap, in bytes: */
165 unsigned io_bitmap_max;
166 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
167 unsigned long debugctlmsr;
168 /* Debug Store - if not 0 points to a DS Save Area configuration;
169 * goes into MSR_IA32_DS_AREA */
170 unsigned long ds_area_msr;
173 static inline unsigned long native_get_debugreg(int regno)
175 unsigned long val = 0; /* Damn you, gcc! */
179 asm("mov %%db0, %0" :"=r" (val)); break;
181 asm("mov %%db1, %0" :"=r" (val)); break;
183 asm("mov %%db2, %0" :"=r" (val)); break;
185 asm("mov %%db3, %0" :"=r" (val)); break;
187 asm("mov %%db6, %0" :"=r" (val)); break;
189 asm("mov %%db7, %0" :"=r" (val)); break;
196 static inline void native_set_debugreg(int regno, unsigned long value)
200 asm("mov %0,%%db0" : /* no output */ :"r" (value));
203 asm("mov %0,%%db1" : /* no output */ :"r" (value));
206 asm("mov %0,%%db2" : /* no output */ :"r" (value));
209 asm("mov %0,%%db3" : /* no output */ :"r" (value));
212 asm("mov %0,%%db6" : /* no output */ :"r" (value));
215 asm("mov %0,%%db7" : /* no output */ :"r" (value));
223 * Set IOPL bits in EFLAGS from given mask
225 static inline void native_set_iopl_mask(unsigned mask)
229 __asm__ __volatile__ ("pushfl;"
236 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
240 static inline void native_load_sp0(struct tss_struct *tss,
241 struct thread_struct *thread)
243 tss->x86_tss.sp0 = thread->sp0;
245 /* Only happens when SEP is enabled, no need to test "SEP"arately */
246 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
247 tss->x86_tss.ss1 = thread->sysenter_cs;
248 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
253 #ifdef CONFIG_PARAVIRT
254 #include <asm/paravirt.h>
256 #define __cpuid native_cpuid
257 #define paravirt_enabled() 0
260 * These special macros can be used to get or set a debugging register
262 #define get_debugreg(var, register) \
263 (var) = native_get_debugreg(register)
264 #define set_debugreg(value, register) \
265 native_set_debugreg(register, value)
267 static inline void load_sp0(struct tss_struct *tss,
268 struct thread_struct *thread)
270 native_load_sp0(tss, thread);
273 #define set_iopl_mask native_set_iopl_mask
274 #endif /* CONFIG_PARAVIRT */
277 * Save the cr4 feature set we're using (ie
278 * Pentium 4MB enable and PPro Global page
279 * enable), so that any CPU's that boot up
280 * after us can get the correct flags.
282 extern unsigned long mmu_cr4_features;
284 static inline void set_in_cr4(unsigned long mask)
287 mmu_cr4_features |= mask;
293 static inline void clear_in_cr4(unsigned long mask)
296 mmu_cr4_features &= ~mask;
302 struct microcode_header {
310 unsigned int datasize;
311 unsigned int totalsize;
312 unsigned int reserved[3];
316 struct microcode_header hdr;
317 unsigned int bits[0];
320 typedef struct microcode microcode_t;
321 typedef struct microcode_header microcode_header_t;
323 /* microcode format is extended from prescott processors */
324 struct extended_signature {
330 struct extended_sigtable {
333 unsigned int reserved[3];
334 struct extended_signature sigs[0];
338 * create a kernel thread without removing it from tasklists
340 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
342 /* Free all resources held by a thread. */
343 extern void release_thread(struct task_struct *);
345 /* Prepare to copy thread state - unlazy all lazy status */
346 extern void prepare_to_copy(struct task_struct *tsk);
348 unsigned long get_wchan(struct task_struct *p);
351 * Generic CPUID function
352 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
353 * resulting in stale register contents being returned.
355 static inline void cpuid(unsigned int op,
356 unsigned int *eax, unsigned int *ebx,
357 unsigned int *ecx, unsigned int *edx)
361 __cpuid(eax, ebx, ecx, edx);
364 /* Some CPUID calls want 'count' to be placed in ecx */
365 static inline void cpuid_count(unsigned int op, int count,
366 unsigned int *eax, unsigned int *ebx,
367 unsigned int *ecx, unsigned int *edx)
371 __cpuid(eax, ebx, ecx, edx);
375 * CPUID functions returning a single datum
377 static inline unsigned int cpuid_eax(unsigned int op)
379 unsigned int eax, ebx, ecx, edx;
381 cpuid(op, &eax, &ebx, &ecx, &edx);
384 static inline unsigned int cpuid_ebx(unsigned int op)
386 unsigned int eax, ebx, ecx, edx;
388 cpuid(op, &eax, &ebx, &ecx, &edx);
391 static inline unsigned int cpuid_ecx(unsigned int op)
393 unsigned int eax, ebx, ecx, edx;
395 cpuid(op, &eax, &ebx, &ecx, &edx);
398 static inline unsigned int cpuid_edx(unsigned int op)
400 unsigned int eax, ebx, ecx, edx;
402 cpuid(op, &eax, &ebx, &ecx, &edx);
406 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
407 static inline void rep_nop(void)
409 __asm__ __volatile__("rep;nop": : :"memory");
412 /* Stop speculative execution */
413 static inline void sync_core(void)
416 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
417 : "ebx", "ecx", "edx", "memory");
420 #define cpu_relax() rep_nop()
422 static inline void __monitor(const void *eax, unsigned long ecx,
425 /* "monitor %eax,%ecx,%edx;" */
427 ".byte 0x0f,0x01,0xc8;"
428 : :"a" (eax), "c" (ecx), "d"(edx));
431 static inline void __mwait(unsigned long eax, unsigned long ecx)
433 /* "mwait %eax,%ecx;" */
435 ".byte 0x0f,0x01,0xc9;"
436 : :"a" (eax), "c" (ecx));
439 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
441 /* "mwait %eax,%ecx;" */
443 "sti; .byte 0x0f,0x01,0xc9;"
444 : :"a" (eax), "c" (ecx));
447 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
449 extern int force_mwait;
451 extern void select_idle_routine(const struct cpuinfo_x86 *c);
453 extern unsigned long boot_option_idle_override;
455 /* Boot loader type from the setup header */
456 extern int bootloader_type;
457 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
459 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
460 #define ARCH_HAS_PREFETCHW
461 #define ARCH_HAS_SPINLOCK_PREFETCH
463 #define spin_lock_prefetch(x) prefetchw(x)
464 /* This decides where the kernel will search for a free chunk of vm
465 * space during mmap's.
467 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
469 #define KSTK_EIP(task) (task_pt_regs(task)->ip)