2 * Copyright (C) 1994 Linus Torvalds
5 #ifndef __ASM_I386_PROCESSOR_H
6 #define __ASM_I386_PROCESSOR_H
9 #include <asm/math_emu.h>
10 #include <asm/segment.h>
12 #include <asm/types.h>
13 #include <asm/sigcontext.h>
14 #include <asm/cpufeature.h>
16 #include <asm/system.h>
17 #include <linux/cache.h>
18 #include <linux/threads.h>
19 #include <asm/percpu.h>
20 #include <linux/cpumask.h>
21 #include <linux/init.h>
22 #include <asm/desc_defs.h>
25 * Default implementation of macro that returns current
26 * instruction pointer ("program counter").
28 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
31 * CPU type and hardware bug flags. Kept separately for each CPU.
32 * Members of this structure are referenced in head.S, so think twice
33 * before touching them. [mj]
37 __u8 x86; /* CPU family */
38 __u8 x86_vendor; /* CPU vendor */
41 char wp_works_ok; /* It doesn't on 386's */
42 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
45 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
46 unsigned long x86_capability[NCAPINTS];
47 char x86_vendor_id[16];
48 char x86_model_id[64];
49 int x86_cache_size; /* in KB - valid for CPUS which support this
51 int x86_cache_alignment; /* In bytes */
57 unsigned long loops_per_jiffy;
59 cpumask_t llc_shared_map; /* cpus sharing the last level cache */
61 unsigned char x86_max_cores; /* cpuid returned max cores value */
63 unsigned short x86_clflush_size;
65 unsigned char booted_cores; /* number of cores as seen by OS */
66 __u8 phys_proc_id; /* Physical processor id. */
67 __u8 cpu_core_id; /* Core id */
68 __u8 cpu_index; /* index into per_cpu list */
70 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
72 #define X86_VENDOR_INTEL 0
73 #define X86_VENDOR_CYRIX 1
74 #define X86_VENDOR_AMD 2
75 #define X86_VENDOR_UMC 3
76 #define X86_VENDOR_NEXGEN 4
77 #define X86_VENDOR_CENTAUR 5
78 #define X86_VENDOR_TRANSMETA 7
79 #define X86_VENDOR_NSC 8
80 #define X86_VENDOR_NUM 9
81 #define X86_VENDOR_UNKNOWN 0xff
84 * capabilities of CPUs
87 extern struct cpuinfo_x86 boot_cpu_data;
88 extern struct cpuinfo_x86 new_cpu_data;
89 extern struct tss_struct doublefault_tss;
90 DECLARE_PER_CPU(struct tss_struct, init_tss);
93 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
94 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
95 #define current_cpu_data cpu_data(smp_processor_id())
97 #define cpu_data(cpu) boot_cpu_data
98 #define current_cpu_data boot_cpu_data
102 * the following now lives in the per cpu area:
103 * extern int cpu_llc_id[NR_CPUS];
105 DECLARE_PER_CPU(u8, cpu_llc_id);
106 extern char ignore_fpu_irq;
108 void __init cpu_detect(struct cpuinfo_x86 *c);
110 extern void identify_boot_cpu(void);
111 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
112 extern void print_cpu_info(struct cpuinfo_x86 *);
113 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
114 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
115 extern unsigned short num_cache_leaves;
118 extern void detect_ht(struct cpuinfo_x86 *c);
120 static inline void detect_ht(struct cpuinfo_x86 *c) {}
123 /* Stop speculative execution */
124 static inline void sync_core(void)
127 asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
130 static inline void __monitor(const void *eax, unsigned long ecx,
133 /* "monitor %eax,%ecx,%edx;" */
135 ".byte 0x0f,0x01,0xc8;"
136 : :"a" (eax), "c" (ecx), "d"(edx));
139 static inline void __mwait(unsigned long eax, unsigned long ecx)
141 /* "mwait %eax,%ecx;" */
143 ".byte 0x0f,0x01,0xc9;"
144 : :"a" (eax), "c" (ecx));
147 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
149 /* from system description table in BIOS. Mostly for MCA use, but
150 others may find it useful. */
151 extern unsigned int machine_id;
152 extern unsigned int machine_submodel_id;
153 extern unsigned int BIOS_revision;
154 extern unsigned int mca_pentium_flag;
156 /* Boot loader type from the setup header */
157 extern int bootloader_type;
160 * User space process size: 3GB (default).
162 #define TASK_SIZE (PAGE_OFFSET)
164 /* This decides where the kernel will search for a free chunk of vm
165 * space during mmap's.
167 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
169 #define HAVE_ARCH_PICK_MMAP_LAYOUT
174 #define IO_BITMAP_BITS 65536
175 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
176 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
177 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
178 #define INVALID_IO_BITMAP_OFFSET 0x8000
179 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
181 struct i387_fsave_struct {
189 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
190 long status; /* software status information */
193 struct i387_fxsave_struct {
204 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
205 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
207 } __attribute__ ((aligned (16)));
209 struct i387_soft_struct {
217 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
218 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
220 unsigned long entry_eip;
224 struct i387_fsave_struct fsave;
225 struct i387_fxsave_struct fxsave;
226 struct i387_soft_struct soft;
233 struct thread_struct;
235 /* This is the TSS defined by the hardware. */
237 unsigned short back_link,__blh;
239 unsigned short ss0,__ss0h;
241 unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
243 unsigned short ss2,__ss2h;
247 unsigned long ax, cx, dx, bx;
248 unsigned long sp, bp, si, di;
249 unsigned short es, __esh;
250 unsigned short cs, __csh;
251 unsigned short ss, __ssh;
252 unsigned short ds, __dsh;
253 unsigned short fs, __fsh;
254 unsigned short gs, __gsh;
255 unsigned short ldt, __ldth;
256 unsigned short trace, io_bitmap_base;
257 } __attribute__((packed));
260 struct i386_hw_tss x86_tss;
263 * The extra 1 is there because the CPU will access an
264 * additional byte beyond the end of the IO permission
265 * bitmap. The extra byte must be all 1 bits, and must
266 * be within the limit.
268 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
270 * Cache the current maximum and the last task that used the bitmap:
272 unsigned long io_bitmap_max;
273 struct thread_struct *io_bitmap_owner;
275 * pads the TSS to be cacheline-aligned (size is 0x100)
277 unsigned long __cacheline_filler[35];
279 * .. and then another 0x100 bytes for emergency kernel stack
281 unsigned long stack[64];
282 } __attribute__((packed));
284 #define ARCH_MIN_TASKALIGN 16
286 struct thread_struct {
287 /* cached TLS descriptors. */
288 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
290 unsigned long sysenter_cs;
295 /* Hardware debugging registers */
296 unsigned long debugreg0;
297 unsigned long debugreg1;
298 unsigned long debugreg2;
299 unsigned long debugreg3;
300 unsigned long debugreg6;
301 unsigned long debugreg7;
303 unsigned long cr2, trap_no, error_code;
304 /* floating point info */
305 union i387_union i387;
306 /* virtual 86 mode info */
307 struct vm86_struct __user * vm86_info;
308 unsigned long screen_bitmap;
309 unsigned long v86flags, v86mask, saved_sp0;
310 unsigned int saved_fs, saved_gs;
312 unsigned long *io_bitmap_ptr;
314 /* max allowed port in the bitmap, in bytes: */
315 unsigned long io_bitmap_max;
316 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
317 unsigned long debugctlmsr;
318 /* Debug Store - if not 0 points to a DS Save Area configuration;
319 * goes into MSR_IA32_DS_AREA */
320 unsigned long ds_area_msr;
323 #define INIT_THREAD { \
324 .sp0 = sizeof(init_stack) + (long)&init_stack, \
326 .sysenter_cs = __KERNEL_CS, \
327 .io_bitmap_ptr = NULL, \
328 .fs = __KERNEL_PERCPU, \
332 * Note that the .io_bitmap member must be extra-big. This is because
333 * the CPU will access an additional byte beyond the end of the IO
334 * permission bitmap. The extra byte must be all 1 bits, and must
335 * be within the limit.
339 .sp0 = sizeof(init_stack) + (long)&init_stack, \
340 .ss0 = __KERNEL_DS, \
341 .ss1 = __KERNEL_CS, \
342 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
344 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
347 #define start_thread(regs, new_eip, new_esp) do { \
348 __asm__("movl %0,%%gs": :"r" (0)); \
351 regs->ds = __USER_DS; \
352 regs->es = __USER_DS; \
353 regs->ss = __USER_DS; \
354 regs->cs = __USER_CS; \
355 regs->ip = new_eip; \
356 regs->sp = new_esp; \
359 /* Forward declaration, a strange C thing */
363 /* Free all resources held by a thread. */
364 extern void release_thread(struct task_struct *);
366 /* Prepare to copy thread state - unlazy all lazy status */
367 extern void prepare_to_copy(struct task_struct *tsk);
370 * create a kernel thread without removing it from tasklists
372 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
374 extern unsigned long thread_saved_pc(struct task_struct *tsk);
376 unsigned long get_wchan(struct task_struct *p);
378 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
379 #define KSTK_TOP(info) \
381 unsigned long *__ptr = (unsigned long *)(info); \
382 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
386 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
387 * This is necessary to guarantee that the entire "struct pt_regs"
388 * is accessable even if the CPU haven't stored the SS/ESP registers
389 * on the stack (interrupt gate does not save these registers
390 * when switching to the same priv ring).
391 * Therefore beware: accessing the ss/esp fields of the
392 * "struct pt_regs" is possible, but they may contain the
393 * completely wrong values.
395 #define task_pt_regs(task) \
397 struct pt_regs *__regs__; \
398 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
402 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
403 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
406 struct microcode_header {
414 unsigned int datasize;
415 unsigned int totalsize;
416 unsigned int reserved[3];
420 struct microcode_header hdr;
421 unsigned int bits[0];
424 typedef struct microcode microcode_t;
425 typedef struct microcode_header microcode_header_t;
427 /* microcode format is extended from prescott processors */
428 struct extended_signature {
434 struct extended_sigtable {
437 unsigned int reserved[3];
438 struct extended_signature sigs[0];
441 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
442 static inline void rep_nop(void)
444 __asm__ __volatile__("rep;nop": : :"memory");
447 #define cpu_relax() rep_nop()
449 static inline void native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
451 tss->x86_tss.sp0 = thread->sp0;
452 /* This can only happen when SEP is enabled, no need to test "SEP"arately */
453 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
454 tss->x86_tss.ss1 = thread->sysenter_cs;
455 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
459 * Set IOPL bits in EFLAGS from given mask
461 static inline void native_set_iopl_mask(unsigned mask)
464 __asm__ __volatile__ ("pushfl;"
471 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
474 #ifdef CONFIG_PARAVIRT
475 #include <asm/paravirt.h>
478 static inline void load_sp0(struct tss_struct *tss, struct thread_struct *thread)
480 native_load_sp0(tss, thread);
483 #define set_iopl_mask native_set_iopl_mask
484 #endif /* CONFIG_PARAVIRT */
486 /* generic versions from gas */
487 #define GENERIC_NOP1 ".byte 0x90\n"
488 #define GENERIC_NOP2 ".byte 0x89,0xf6\n"
489 #define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
490 #define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
491 #define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
492 #define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
493 #define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
494 #define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
497 #define K8_NOP1 GENERIC_NOP1
498 #define K8_NOP2 ".byte 0x66,0x90\n"
499 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
500 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
501 #define K8_NOP5 K8_NOP3 K8_NOP2
502 #define K8_NOP6 K8_NOP3 K8_NOP3
503 #define K8_NOP7 K8_NOP4 K8_NOP3
504 #define K8_NOP8 K8_NOP4 K8_NOP4
507 /* uses eax dependencies (arbitary choice) */
508 #define K7_NOP1 GENERIC_NOP1
509 #define K7_NOP2 ".byte 0x8b,0xc0\n"
510 #define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
511 #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
512 #define K7_NOP5 K7_NOP4 ASM_NOP1
513 #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
514 #define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
515 #define K7_NOP8 K7_NOP7 ASM_NOP1
518 /* uses eax dependencies (Intel-recommended choice) */
519 #define P6_NOP1 GENERIC_NOP1
520 #define P6_NOP2 ".byte 0x66,0x90\n"
521 #define P6_NOP3 ".byte 0x0f,0x1f,0x00\n"
522 #define P6_NOP4 ".byte 0x0f,0x1f,0x40,0\n"
523 #define P6_NOP5 ".byte 0x0f,0x1f,0x44,0x00,0\n"
524 #define P6_NOP6 ".byte 0x66,0x0f,0x1f,0x44,0x00,0\n"
525 #define P6_NOP7 ".byte 0x0f,0x1f,0x80,0,0,0,0\n"
526 #define P6_NOP8 ".byte 0x0f,0x1f,0x84,0x00,0,0,0,0\n"
529 #define ASM_NOP1 K8_NOP1
530 #define ASM_NOP2 K8_NOP2
531 #define ASM_NOP3 K8_NOP3
532 #define ASM_NOP4 K8_NOP4
533 #define ASM_NOP5 K8_NOP5
534 #define ASM_NOP6 K8_NOP6
535 #define ASM_NOP7 K8_NOP7
536 #define ASM_NOP8 K8_NOP8
537 #elif defined(CONFIG_MK7)
538 #define ASM_NOP1 K7_NOP1
539 #define ASM_NOP2 K7_NOP2
540 #define ASM_NOP3 K7_NOP3
541 #define ASM_NOP4 K7_NOP4
542 #define ASM_NOP5 K7_NOP5
543 #define ASM_NOP6 K7_NOP6
544 #define ASM_NOP7 K7_NOP7
545 #define ASM_NOP8 K7_NOP8
546 #elif defined(CONFIG_M686) || defined(CONFIG_MPENTIUMII) || \
547 defined(CONFIG_MPENTIUMIII) || defined(CONFIG_MPENTIUMM) || \
548 defined(CONFIG_MCORE2) || defined(CONFIG_PENTIUM4)
549 #define ASM_NOP1 P6_NOP1
550 #define ASM_NOP2 P6_NOP2
551 #define ASM_NOP3 P6_NOP3
552 #define ASM_NOP4 P6_NOP4
553 #define ASM_NOP5 P6_NOP5
554 #define ASM_NOP6 P6_NOP6
555 #define ASM_NOP7 P6_NOP7
556 #define ASM_NOP8 P6_NOP8
558 #define ASM_NOP1 GENERIC_NOP1
559 #define ASM_NOP2 GENERIC_NOP2
560 #define ASM_NOP3 GENERIC_NOP3
561 #define ASM_NOP4 GENERIC_NOP4
562 #define ASM_NOP5 GENERIC_NOP5
563 #define ASM_NOP6 GENERIC_NOP6
564 #define ASM_NOP7 GENERIC_NOP7
565 #define ASM_NOP8 GENERIC_NOP8
568 #define ASM_NOP_MAX 8
570 /* Prefetch instructions for Pentium III and AMD Athlon */
571 /* It's not worth to care about 3dnow! prefetches for the K6
572 because they are microcoded there and very slow.
573 However we don't do prefetches for pre XP Athlons currently
574 That should be fixed. */
575 #define ARCH_HAS_PREFETCH
576 static inline void prefetch(const void *x)
578 alternative_input(ASM_NOP4,
584 #define ARCH_HAS_PREFETCH
585 #define ARCH_HAS_PREFETCHW
586 #define ARCH_HAS_SPINLOCK_PREFETCH
588 /* 3dnow! prefetch to get an exclusive cache line. Useful for
589 spinlocks to avoid one state transition in the cache coherency protocol. */
590 static inline void prefetchw(const void *x)
592 alternative_input(ASM_NOP4,
597 #define spin_lock_prefetch(x) prefetchw(x)
599 extern void select_idle_routine(const struct cpuinfo_x86 *c);
601 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
603 extern unsigned long boot_option_idle_override;
604 extern void enable_sep_cpu(void);
605 extern int sysenter_setup(void);
607 /* Defined in head.S */
608 extern struct desc_ptr early_gdt_descr;
610 extern void cpu_set_gdt(int);
611 extern void switch_to_new_gdt(void);
612 extern void cpu_init(void);
613 extern void init_gdt(int cpu);
615 extern int force_mwait;
617 #endif /* __ASM_I386_PROCESSOR_H */