6 * Access to machine-specific registers (available on 586 and better only)
7 * Note: the rd* operations modify the parameters directly (without using
8 * pointer indirection), this allows gcc to optimize better
11 #define rdmsr(msr,val1,val2) \
12 __asm__ __volatile__("rdmsr" \
13 : "=a" (val1), "=d" (val2) \
17 #define rdmsrl(msr,val) do { unsigned long a__,b__; \
18 __asm__ __volatile__("rdmsr" \
19 : "=a" (a__), "=d" (b__) \
21 val = a__ | (b__<<32); \
24 #define wrmsr(msr,val1,val2) \
25 __asm__ __volatile__("wrmsr" \
27 : "c" (msr), "a" (val1), "d" (val2))
29 #define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32)
31 /* wrmsr with exception handling */
32 #define wrmsr_safe(msr,a,b) ({ int ret__; \
33 asm volatile("2: wrmsr ; xorl %0,%0\n" \
35 ".section .fixup,\"ax\"\n\t" \
36 "3: movl %4,%0 ; jmp 1b\n\t" \
38 ".section __ex_table,\"a\"\n" \
43 : "c" (msr), "0" (a), "d" (b), "i" (-EFAULT)); \
46 #define checking_wrmsrl(msr,val) wrmsr_safe(msr,(u32)(val),(u32)((val)>>32))
48 #define rdmsr_safe(msr,a,b) \
50 asm volatile ("1: rdmsr\n" \
52 ".section .fixup,\"ax\"\n" \
56 ".section __ex_table,\"a\"\n" \
59 ".previous":"=&bDS" (ret__), "=a"(*(a)), "=d"(*(b))\
60 :"c"(msr), "i"(-EIO), "0"(0)); \
63 #define rdtsc(low,high) \
64 __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
67 __asm__ __volatile__ ("rdtsc" : "=a" (low) : : "edx")
69 #define rdtscp(low,high,aux) \
70 asm volatile (".byte 0x0f,0x01,0xf9" : "=a" (low), "=d" (high), "=c" (aux))
72 #define rdtscll(val) do { \
73 unsigned int __a,__d; \
74 asm volatile("rdtsc" : "=a" (__a), "=d" (__d)); \
75 (val) = ((unsigned long)__a) | (((unsigned long)__d)<<32); \
78 #define rdtscpll(val, aux) do { \
79 unsigned long __a, __d; \
80 asm volatile (".byte 0x0f,0x01,0xf9" : "=a" (__a), "=d" (__d), "=c" (aux)); \
81 (val) = (__d << 32) | __a; \
84 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
86 #define write_rdtscp_aux(val) wrmsr(0xc0000103, val, 0)
88 #define rdpmc(counter,low,high) \
89 __asm__ __volatile__("rdpmc" \
90 : "=a" (low), "=d" (high) \
93 static inline void cpuid(int op, unsigned int *eax, unsigned int *ebx,
94 unsigned int *ecx, unsigned int *edx)
104 /* Some CPUID calls want 'count' to be placed in ecx */
105 static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
113 : "0" (op), "c" (count));
117 * CPUID functions returning a single datum
119 static inline unsigned int cpuid_eax(unsigned int op)
129 static inline unsigned int cpuid_ebx(unsigned int op)
131 unsigned int eax, ebx;
134 : "=a" (eax), "=b" (ebx)
139 static inline unsigned int cpuid_ecx(unsigned int op)
141 unsigned int eax, ecx;
144 : "=a" (eax), "=c" (ecx)
149 static inline unsigned int cpuid_edx(unsigned int op)
151 unsigned int eax, edx;
154 : "=a" (eax), "=d" (edx)
160 #define MSR_IA32_UCODE_WRITE 0x79
161 #define MSR_IA32_UCODE_REV 0x8b
163 void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
164 void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
168 /* AMD/K8 specific MSRs */
169 #define MSR_EFER 0xc0000080 /* extended feature register */
170 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
171 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
172 #define MSR_CSTAR 0xc0000083 /* compatibility mode SYSCALL target */
173 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
174 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
175 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
176 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow (or USER_GS from kernel) */
178 #define _EFER_SCE 0 /* SYSCALL/SYSRET */
179 #define _EFER_LME 8 /* Long mode enable */
180 #define _EFER_LMA 10 /* Long mode active (read-only) */
181 #define _EFER_NX 11 /* No execute enable */
183 #define EFER_SCE (1<<_EFER_SCE)
184 #define EFER_LME (1<<_EFER_LME)
185 #define EFER_LMA (1<<_EFER_LMA)
186 #define EFER_NX (1<<_EFER_NX)
188 /* Intel MSRs. Some also available on other CPUs */
189 #define MSR_IA32_TSC 0x10
190 #define MSR_IA32_PLATFORM_ID 0x17
192 #define MSR_IA32_PERFCTR0 0xc1
193 #define MSR_IA32_PERFCTR1 0xc2
194 #define MSR_FSB_FREQ 0xcd
196 #define MSR_MTRRcap 0x0fe
197 #define MSR_IA32_BBL_CR_CTL 0x119
199 #define MSR_IA32_SYSENTER_CS 0x174
200 #define MSR_IA32_SYSENTER_ESP 0x175
201 #define MSR_IA32_SYSENTER_EIP 0x176
203 #define MSR_IA32_MCG_CAP 0x179
204 #define MSR_IA32_MCG_STATUS 0x17a
205 #define MSR_IA32_MCG_CTL 0x17b
207 #define MSR_IA32_EVNTSEL0 0x186
208 #define MSR_IA32_EVNTSEL1 0x187
210 #define MSR_IA32_DEBUGCTLMSR 0x1d9
211 #define MSR_IA32_LASTBRANCHFROMIP 0x1db
212 #define MSR_IA32_LASTBRANCHTOIP 0x1dc
213 #define MSR_IA32_LASTINTFROMIP 0x1dd
214 #define MSR_IA32_LASTINTTOIP 0x1de
216 #define MSR_IA32_PEBS_ENABLE 0x3f1
217 #define MSR_IA32_DS_AREA 0x600
218 #define MSR_IA32_PERF_CAPABILITIES 0x345
220 #define MSR_MTRRfix64K_00000 0x250
221 #define MSR_MTRRfix16K_80000 0x258
222 #define MSR_MTRRfix16K_A0000 0x259
223 #define MSR_MTRRfix4K_C0000 0x268
224 #define MSR_MTRRfix4K_C8000 0x269
225 #define MSR_MTRRfix4K_D0000 0x26a
226 #define MSR_MTRRfix4K_D8000 0x26b
227 #define MSR_MTRRfix4K_E0000 0x26c
228 #define MSR_MTRRfix4K_E8000 0x26d
229 #define MSR_MTRRfix4K_F0000 0x26e
230 #define MSR_MTRRfix4K_F8000 0x26f
231 #define MSR_MTRRdefType 0x2ff
233 #define MSR_IA32_MC0_CTL 0x400
234 #define MSR_IA32_MC0_STATUS 0x401
235 #define MSR_IA32_MC0_ADDR 0x402
236 #define MSR_IA32_MC0_MISC 0x403
238 #define MSR_P6_PERFCTR0 0xc1
239 #define MSR_P6_PERFCTR1 0xc2
240 #define MSR_P6_EVNTSEL0 0x186
241 #define MSR_P6_EVNTSEL1 0x187
243 /* K7/K8 MSRs. Not complete. See the architecture manual for a more complete list. */
244 #define MSR_K7_EVNTSEL0 0xC0010000
245 #define MSR_K7_PERFCTR0 0xC0010004
246 #define MSR_K7_EVNTSEL1 0xC0010001
247 #define MSR_K7_PERFCTR1 0xC0010005
248 #define MSR_K7_EVNTSEL2 0xC0010002
249 #define MSR_K7_PERFCTR2 0xC0010006
250 #define MSR_K7_EVNTSEL3 0xC0010003
251 #define MSR_K7_PERFCTR3 0xC0010007
252 #define MSR_K8_TOP_MEM1 0xC001001A
253 #define MSR_K8_TOP_MEM2 0xC001001D
254 #define MSR_K8_SYSCFG 0xC0010010
255 #define MSR_K8_HWCR 0xC0010015
258 #define MSR_K6_EFER 0xC0000080
259 #define MSR_K6_STAR 0xC0000081
260 #define MSR_K6_WHCR 0xC0000082
261 #define MSR_K6_UWCCR 0xC0000085
262 #define MSR_K6_PSOR 0xC0000087
263 #define MSR_K6_PFIR 0xC0000088
265 /* Centaur-Hauls/IDT defined MSRs. */
266 #define MSR_IDT_FCR1 0x107
267 #define MSR_IDT_FCR2 0x108
268 #define MSR_IDT_FCR3 0x109
269 #define MSR_IDT_FCR4 0x10a
271 #define MSR_IDT_MCR0 0x110
272 #define MSR_IDT_MCR1 0x111
273 #define MSR_IDT_MCR2 0x112
274 #define MSR_IDT_MCR3 0x113
275 #define MSR_IDT_MCR4 0x114
276 #define MSR_IDT_MCR5 0x115
277 #define MSR_IDT_MCR6 0x116
278 #define MSR_IDT_MCR7 0x117
279 #define MSR_IDT_MCR_CTRL 0x120
281 /* VIA Cyrix defined MSRs*/
282 #define MSR_VIA_FCR 0x1107
283 #define MSR_VIA_LONGHAUL 0x110a
284 #define MSR_VIA_RNG 0x110b
285 #define MSR_VIA_BCR2 0x1147
287 /* Intel defined MSRs. */
288 #define MSR_IA32_P5_MC_ADDR 0
289 #define MSR_IA32_P5_MC_TYPE 1
290 #define MSR_IA32_PLATFORM_ID 0x17
291 #define MSR_IA32_EBL_CR_POWERON 0x2a
293 #define MSR_IA32_APICBASE 0x1b
294 #define MSR_IA32_APICBASE_BSP (1<<8)
295 #define MSR_IA32_APICBASE_ENABLE (1<<11)
296 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
298 /* P4/Xeon+ specific */
299 #define MSR_IA32_MCG_EAX 0x180
300 #define MSR_IA32_MCG_EBX 0x181
301 #define MSR_IA32_MCG_ECX 0x182
302 #define MSR_IA32_MCG_EDX 0x183
303 #define MSR_IA32_MCG_ESI 0x184
304 #define MSR_IA32_MCG_EDI 0x185
305 #define MSR_IA32_MCG_EBP 0x186
306 #define MSR_IA32_MCG_ESP 0x187
307 #define MSR_IA32_MCG_EFLAGS 0x188
308 #define MSR_IA32_MCG_EIP 0x189
309 #define MSR_IA32_MCG_RESERVED 0x18A
311 #define MSR_P6_EVNTSEL0 0x186
312 #define MSR_P6_EVNTSEL1 0x187
314 #define MSR_IA32_PERF_STATUS 0x198
315 #define MSR_IA32_PERF_CTL 0x199
317 #define MSR_IA32_MPERF 0xE7
318 #define MSR_IA32_APERF 0xE8
320 #define MSR_IA32_THERM_CONTROL 0x19a
321 #define MSR_IA32_THERM_INTERRUPT 0x19b
322 #define MSR_IA32_THERM_STATUS 0x19c
323 #define MSR_IA32_MISC_ENABLE 0x1a0
325 #define MSR_IA32_DEBUGCTLMSR 0x1d9
326 #define MSR_IA32_LASTBRANCHFROMIP 0x1db
327 #define MSR_IA32_LASTBRANCHTOIP 0x1dc
328 #define MSR_IA32_LASTINTFROMIP 0x1dd
329 #define MSR_IA32_LASTINTTOIP 0x1de
331 #define MSR_IA32_MC0_CTL 0x400
332 #define MSR_IA32_MC0_STATUS 0x401
333 #define MSR_IA32_MC0_ADDR 0x402
334 #define MSR_IA32_MC0_MISC 0x403
336 /* Pentium IV performance counter MSRs */
337 #define MSR_P4_BPU_PERFCTR0 0x300
338 #define MSR_P4_BPU_PERFCTR1 0x301
339 #define MSR_P4_BPU_PERFCTR2 0x302
340 #define MSR_P4_BPU_PERFCTR3 0x303
341 #define MSR_P4_MS_PERFCTR0 0x304
342 #define MSR_P4_MS_PERFCTR1 0x305
343 #define MSR_P4_MS_PERFCTR2 0x306
344 #define MSR_P4_MS_PERFCTR3 0x307
345 #define MSR_P4_FLAME_PERFCTR0 0x308
346 #define MSR_P4_FLAME_PERFCTR1 0x309
347 #define MSR_P4_FLAME_PERFCTR2 0x30a
348 #define MSR_P4_FLAME_PERFCTR3 0x30b
349 #define MSR_P4_IQ_PERFCTR0 0x30c
350 #define MSR_P4_IQ_PERFCTR1 0x30d
351 #define MSR_P4_IQ_PERFCTR2 0x30e
352 #define MSR_P4_IQ_PERFCTR3 0x30f
353 #define MSR_P4_IQ_PERFCTR4 0x310
354 #define MSR_P4_IQ_PERFCTR5 0x311
355 #define MSR_P4_BPU_CCCR0 0x360
356 #define MSR_P4_BPU_CCCR1 0x361
357 #define MSR_P4_BPU_CCCR2 0x362
358 #define MSR_P4_BPU_CCCR3 0x363
359 #define MSR_P4_MS_CCCR0 0x364
360 #define MSR_P4_MS_CCCR1 0x365
361 #define MSR_P4_MS_CCCR2 0x366
362 #define MSR_P4_MS_CCCR3 0x367
363 #define MSR_P4_FLAME_CCCR0 0x368
364 #define MSR_P4_FLAME_CCCR1 0x369
365 #define MSR_P4_FLAME_CCCR2 0x36a
366 #define MSR_P4_FLAME_CCCR3 0x36b
367 #define MSR_P4_IQ_CCCR0 0x36c
368 #define MSR_P4_IQ_CCCR1 0x36d
369 #define MSR_P4_IQ_CCCR2 0x36e
370 #define MSR_P4_IQ_CCCR3 0x36f
371 #define MSR_P4_IQ_CCCR4 0x370
372 #define MSR_P4_IQ_CCCR5 0x371
373 #define MSR_P4_ALF_ESCR0 0x3ca
374 #define MSR_P4_ALF_ESCR1 0x3cb
375 #define MSR_P4_BPU_ESCR0 0x3b2
376 #define MSR_P4_BPU_ESCR1 0x3b3
377 #define MSR_P4_BSU_ESCR0 0x3a0
378 #define MSR_P4_BSU_ESCR1 0x3a1
379 #define MSR_P4_CRU_ESCR0 0x3b8
380 #define MSR_P4_CRU_ESCR1 0x3b9
381 #define MSR_P4_CRU_ESCR2 0x3cc
382 #define MSR_P4_CRU_ESCR3 0x3cd
383 #define MSR_P4_CRU_ESCR4 0x3e0
384 #define MSR_P4_CRU_ESCR5 0x3e1
385 #define MSR_P4_DAC_ESCR0 0x3a8
386 #define MSR_P4_DAC_ESCR1 0x3a9
387 #define MSR_P4_FIRM_ESCR0 0x3a4
388 #define MSR_P4_FIRM_ESCR1 0x3a5
389 #define MSR_P4_FLAME_ESCR0 0x3a6
390 #define MSR_P4_FLAME_ESCR1 0x3a7
391 #define MSR_P4_FSB_ESCR0 0x3a2
392 #define MSR_P4_FSB_ESCR1 0x3a3
393 #define MSR_P4_IQ_ESCR0 0x3ba
394 #define MSR_P4_IQ_ESCR1 0x3bb
395 #define MSR_P4_IS_ESCR0 0x3b4
396 #define MSR_P4_IS_ESCR1 0x3b5
397 #define MSR_P4_ITLB_ESCR0 0x3b6
398 #define MSR_P4_ITLB_ESCR1 0x3b7
399 #define MSR_P4_IX_ESCR0 0x3c8
400 #define MSR_P4_IX_ESCR1 0x3c9
401 #define MSR_P4_MOB_ESCR0 0x3aa
402 #define MSR_P4_MOB_ESCR1 0x3ab
403 #define MSR_P4_MS_ESCR0 0x3c0
404 #define MSR_P4_MS_ESCR1 0x3c1
405 #define MSR_P4_PMH_ESCR0 0x3ac
406 #define MSR_P4_PMH_ESCR1 0x3ad
407 #define MSR_P4_RAT_ESCR0 0x3bc
408 #define MSR_P4_RAT_ESCR1 0x3bd
409 #define MSR_P4_SAAT_ESCR0 0x3ae
410 #define MSR_P4_SAAT_ESCR1 0x3af
411 #define MSR_P4_SSU_ESCR0 0x3be
412 #define MSR_P4_SSU_ESCR1 0x3bf /* guess: not defined in manual */
413 #define MSR_P4_TBPU_ESCR0 0x3c2
414 #define MSR_P4_TBPU_ESCR1 0x3c3
415 #define MSR_P4_TC_ESCR0 0x3c4
416 #define MSR_P4_TC_ESCR1 0x3c5
417 #define MSR_P4_U2L_ESCR0 0x3b0
418 #define MSR_P4_U2L_ESCR1 0x3b1
420 /* Intel Core-based CPU performance counters */
421 #define MSR_CORE_PERF_FIXED_CTR0 0x309
422 #define MSR_CORE_PERF_FIXED_CTR1 0x30a
423 #define MSR_CORE_PERF_FIXED_CTR2 0x30b
424 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d
425 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e
426 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f
427 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390