1 #ifndef _X8664_TLBFLUSH_H
2 #define _X8664_TLBFLUSH_H
5 #include <asm/processor.h>
6 #include <asm/system.h>
8 static inline void __flush_tlb(void)
10 write_cr3(read_cr3());
13 static inline void __flush_tlb_all(void)
15 unsigned long cr4 = read_cr4();
16 write_cr4(cr4 & ~X86_CR4_PGE); /* clear PGE */
17 write_cr4(cr4); /* write old PGE again and flush TLBs */
20 #define __flush_tlb_one(addr) \
21 __asm__ __volatile__("invlpg (%0)" :: "r" (addr) : "memory")
27 * - flush_tlb() flushes the current mm struct TLBs
28 * - flush_tlb_all() flushes all processes TLBs
29 * - flush_tlb_mm(mm) flushes the specified mm context TLB's
30 * - flush_tlb_page(vma, vmaddr) flushes one page
31 * - flush_tlb_range(vma, start, end) flushes a range of pages
32 * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
33 * - flush_tlb_pgtables(mm, start, end) flushes a range of page tables
35 * x86-64 can only flush individual pages or full VMs. For a range flush
36 * we always do the full VM. Might be worth trying if for a small
37 * range a few INVLPGs in a row are a win.
42 #define flush_tlb() __flush_tlb()
43 #define flush_tlb_all() __flush_tlb_all()
44 #define local_flush_tlb() __flush_tlb()
46 static inline void flush_tlb_mm(struct mm_struct *mm)
48 if (mm == current->active_mm)
52 static inline void flush_tlb_page(struct vm_area_struct *vma,
55 if (vma->vm_mm == current->active_mm)
56 __flush_tlb_one(addr);
59 static inline void flush_tlb_range(struct vm_area_struct *vma,
60 unsigned long start, unsigned long end)
62 if (vma->vm_mm == current->active_mm)
70 #define local_flush_tlb() \
73 extern void flush_tlb_all(void);
74 extern void flush_tlb_current_task(void);
75 extern void flush_tlb_mm(struct mm_struct *);
76 extern void flush_tlb_page(struct vm_area_struct *, unsigned long);
78 #define flush_tlb() flush_tlb_current_task()
80 static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long start, unsigned long end)
82 flush_tlb_mm(vma->vm_mm);
86 #define TLBSTATE_LAZY 2
88 /* Roughly an IPI every 20MB with 4k pages for freeing page table
89 ranges. Cost is about 42k of memory for each CPU. */
90 #define ARCH_FREE_PTE_NR 5350
94 #define flush_tlb_kernel_range(start, end) flush_tlb_all()
96 static inline void flush_tlb_pgtables(struct mm_struct *mm,
97 unsigned long start, unsigned long end)
99 /* x86_64 does not keep any page table caches in a software TLB.
100 The CPUs do in their hardware TLBs, but they are handled
101 by the normal TLB flushing algorithms. */
104 #endif /* _X8664_TLBFLUSH_H */