3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
28 /*************************************************************************
29 * (c) 2002 Datentechnik AG - Project: Dino
32 * $Id: DB64360.h,v 1.3 2003/04/26 04:58:13 brad Exp $
34 ************************************************************************/
36 /*************************************************************************
41 * Revision 1.3 2003/04/26 04:58:13 brad
42 * Cosmetic changes and compiler warning cleanups
44 * Revision 1.2 2003/04/23 15:48:15 ingo
45 * mem. map output added
47 * Revision 1.1 2003/04/17 09:31:42 ias
48 * keymile changes 17_04_2003
50 * Revision 1.10 2003/03/06 12:25:04 ias
51 * 750 FX CPU HID settings updated
53 * Revision 1.9 2003/03/03 16:14:36 ias
54 * cleanup compiler warnings of printf fuctions
56 * Revision 1.8 2003/03/03 15:11:44 ias
57 * Marvell MPSC-UART is working
59 * Revision 1.7 2003/02/26 12:15:45 ssu
60 * adapted default parameters to new board flash address
62 * Revision 1.6 2003/02/25 14:55:42 ssu
63 * changed default environment parameters
65 * Revision 1.5 2003/02/21 17:14:23 ias
66 * added extended SPD handling
68 * Revision 1.4 2003/01/14 09:16:08 ias
69 * PPCBoot for Marvel Beta 0.9
71 * Revision 1.3 2002/12/03 13:56:26 ias
72 * Environment in flash support added
74 * Revision 1.2 2002/11/29 16:53:29 ias
75 * Flash support for STM added
77 * Revision 1.1 2002/11/29 13:36:31 ias
78 * Revision 0.1 of PPCBOOT (1.1.5) for Marvell DB64360 IBM750FX Board
79 * - working DDRRAM (only 32MByte of 128MB Modul)
80 * - working I2C Driver for SPD EEPROM read
81 * - working DUART 16650 for Serial Console
86 ************************************************************************/
91 #include <asm/processor.h>
93 /* This define must be before the core.h include */
94 #define CONFIG_DB64360 1 /* this is an DB64360 board */
97 #include "../board/Marvell/include/core.h"
100 /*-----------------------------------------------------*/
101 /* #include "../board/db64360/local.h" */
106 #define CONFIG_ETHADDR 64:36:00:00:00:01
107 /* next two ethernet hwaddrs */
108 #define CONFIG_ETH1ADDR 64:36:00:00:00:02
109 /* in the atlantis 64360 we have only 2 ETH port on the board,
110 if we use PCI it has its own MAC addr */
112 #define CONFIG_ENV_OVERWRITE
113 #endif /* __CONFIG_H */
116 * High Level Configuration Options
120 #define CONFIG_74xx /* we have a 750FX (override local.h) */
122 #define CONFIG_DB64360 1 /* this is an DB64360 board */
124 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */
125 /*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the
126 DRAM for ECC in the phase we are relocating to it, which isn't so sufficient.
127 so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase,
129 #undef CONFIG_ECC /* enable ECC support */
130 #define CONFIG_MV64360_ECC
132 /* which initialization functions to call for this board */
133 #define CONFIG_MISC_INIT_R /* initialize the icache L1 */
134 #define CONFIG_BOARD_PRE_INIT
136 #define CFG_BOARD_NAME "DB64360"
137 #define CONFIG_IDENT_STRING "Marvell DB64360 (1.1)"
139 /*#define CFG_HUSH_PARSER */
140 #undef CFG_HUSH_PARSER
142 #define CFG_PROMPT_HUSH_PS2 "> "
145 * The following defines let you select what serial you want to use
146 * for your console driver.
149 * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial
150 * cable onto the second DUART channel, change the CFG_DUART port from 1
153 * to use the MPSC, #define CONFIG_MPSC. If you have wired up another
154 * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
157 #define CONFIG_MPSC_PORT 0
159 /* to change the default ethernet port, use this define (options: 0, 1, 2) */
160 #define CONFIG_NET_MULTI
161 #define MV_ETH_DEVS 2
163 /* #undef CONFIG_ETHER_PORT_MII */
165 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
167 #define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
169 #define CONFIG_ZERO_BOOTDELAY_CHECK
172 #undef CONFIG_BOOTARGS
173 /*#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" */
175 /* ronen - autoboot using tftp */
176 #if (CONFIG_BOOTDELAY >= 0)
177 #define CONFIG_BOOTCOMMAND "tftpboot 0x400000 uImage;\
178 setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \
179 ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; "
181 #define CONFIG_BOOTARGS "console=ttyS0,115200"
185 /* ronen - the u-boot.bin should be ~0x30000 bytes */
186 #define CONFIG_EXTRA_ENV_SETTINGS \
187 "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \
188 cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \
189 "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \
190 cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \
191 "bootargs_root=root=/dev/nfs rw\0" \
192 "bootargs_end=:::DB64360:eth0:none \0"\
193 "ethprime=mv_enet0\0"\
194 "standalone=fsload 0x400000 uImage;setenv bootargs $(bootargs) root=/dev/mtdblock/0 rw \
195 ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000;\0"
197 /* --------------------------------------------------------------------------------------------------------------- */
198 /* New bootcommands for Marvell DB64360 c 2002 Ingo Assmus */
200 #define CONFIG_IPADDR 10.2.40.90
202 #define CONFIG_SERIAL "No. 1"
203 #define CONFIG_SERVERIP 10.2.1.126
204 #define CONFIG_ROOTPATH /mnt/yellow_dog_mini
207 #define CONFIG_TESTDRAMDATA y
208 #define CONFIG_TESTDRAMADDRESS n
209 #define CONFIG_TESETDRAMWALK n
211 /* --------------------------------------------------------------------------------------------------------------- */
213 #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
214 #define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
216 #undef CONFIG_WATCHDOG /* watchdog disabled */
217 #undef CONFIG_ALTIVEC /* undef to disable */
219 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
220 CONFIG_BOOTP_BOOTFILESIZE)
222 /* Flash banks JFFS2 should use */
223 #define CFG_JFFS2_FIRST_BANK 1
224 #define CFG_JFFS2_NUM_BANKS 1
226 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
235 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
236 #include <cmd_confdefs.h>
239 * Miscellaneous configurable options
241 #define CFG_I2C_EEPROM_ADDR_LEN 1
242 #define CFG_I2C_MULTI_EEPROMS
243 #define CFG_I2C_SPEED 40000 /* I2C speed default */
245 /* #define CFG_GT_DUAL_CPU also for JTAG even with one cpu */
246 #define CFG_LONGHELP /* undef to save memory */
247 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
248 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
249 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
251 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
253 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
254 #define CFG_MAXARGS 16 /* max number of command args */
255 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
257 /*#define CFG_MEMTEST_START 0x00400000 memtest works on */
258 /*#define CFG_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */
259 /*#define CFG_MEMTEST_END 0x07c00000 4 ... 124 MB in DRAM */
262 #define CFG_DRAM_TEST
264 * CFG_DRAM_TEST - enables the following tests.
266 * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
267 * Environment variable 'test_dram_data' must be
269 * CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
270 * addressable. Environment variable
271 * 'test_dram_address' must be set to 'y'.
272 * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
273 * This test takes about 6 minutes to test 64 MB.
274 * Environment variable 'test_dram_walk' must be
277 #define CFG_DRAM_TEST
278 #if defined(CFG_DRAM_TEST)
279 #define CFG_MEMTEST_START 0x00400000 /* memtest works on */
280 /* #define CFG_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */
281 #define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */
282 #define CFG_DRAM_TEST_DATA
283 #define CFG_DRAM_TEST_ADDRESS
284 #define CFG_DRAM_TEST_WALK
285 #endif /* CFG_DRAM_TEST */
287 #undef CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */
288 #undef CFG_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */
290 #define CFG_LOAD_ADDR 0x00400000 /* default load address */
292 #define CFG_HZ 1000 /* decr freq: 1ms ticks */
293 /*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */
294 #define CFG_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */
295 #define CFG_BUS_CLK CFG_BUS_HZ
297 #define CFG_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */
298 #define CFG_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 400MHZ -> 5.0 ns, for 133MHZ -> 7.50 ns */
300 /*ronen - this is the Tclk (MV64360 core) */
301 #define CFG_TCLK 133000000
304 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
306 #define CFG_750FX_HID0 0x8000c084
307 #define CFG_750FX_HID1 0x54800000
308 #define CFG_750FX_HID2 0x00000000
311 * Low Level Configuration Settings
312 * (address mappings, register initial values, etc.)
313 * You should know what you are doing if you make changes here.
316 /*-----------------------------------------------------------------------
317 * Definitions for initial stack pointer and data area
321 * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
322 * To an unused memory region. The stack will remain in cache until RAM
325 #define CFG_INIT_RAM_LOCK
326 #define CFG_INIT_RAM_ADDR 0x40000000 /* unused memory region */
327 #define CFG_INIT_RAM_END 0x1000
328 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
329 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
331 #define RELOCATE_INTERNAL_RAM_ADDR
332 #ifdef RELOCATE_INTERNAL_RAM_ADDR
333 #define CFG_INTERNAL_RAM_ADDR 0xf8000000
336 /*-----------------------------------------------------------------------
337 * Start addresses for the final memory configuration
338 * (Set up by the startup code)
339 * Please note that CFG_SDRAM_BASE _must_ start at 0
341 #define CFG_SDRAM_BASE 0x00000000
342 /* Dummies for BAT 4-7 */
343 #define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */
344 #define CFG_SDRAM2_BASE 0x20000000
345 #define CFG_SDRAM3_BASE 0x30000000
346 #define CFG_SDRAM4_BASE 0x40000000
347 #define CFG_FLASH_BASE 0xfff00000
349 #define CFG_DFL_BOOTCS_BASE 0xff800000
350 #define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS*/
352 #define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */
353 #define UART_BASE_BOOTM 0xfbb00000 /* in order to be sync with the kernel parameters. */
354 #define PCI0_IO_BASE_BOOTM 0xfd000000
356 #define CFG_RESET_ADDRESS 0xfff00100
357 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
358 #define CFG_MONITOR_BASE CFG_FLASH_BASE
359 #define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
361 /* areas to map different things with the GT in physical space */
362 #define CFG_DRAM_BANKS 4
364 /* What to put in the bats. */
365 #define CFG_MISC_REGION_BASE 0xf0000000
367 /* Peripheral Device section */
369 /*******************************************************/
370 /* We have on the db64360 Board : */
371 /* GT-Chipset Register Area */
372 /* GT-Chipset internal SRAM 256k */
373 /* SRAM on external device module */
374 /* Real time clock on external device module */
375 /* dobble UART on external device module */
376 /* Data flash on external device module */
377 /* Boot flash on external device module */
378 /*******************************************************/
379 #define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
380 #define CFG_DB64360_RESET_ADDR 0x14000000 /* After power on Reset the DB64360 is here */
382 /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
383 #define CFG_GT_REGS 0xf1000000 /* GT Registers will be mapped here */
384 #define CFG_DEV_BASE 0xfc000000 /* GT Devices CS start here */
386 #define CFG_DEV0_SPACE CFG_DEV_BASE /* DEV_CS0 device modul sram */
387 #define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE) /* DEV_CS1 device modul real time clock (rtc) */
388 #define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE) /* DEV_CS2 device modul doubel uart (duart) */
389 #define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE) /* DEV_CS3 device modul large flash */
391 #define CFG_DEV0_SIZE _8M /* db64360 sram @ 0xfc00.0000 */
392 #define CFG_DEV1_SIZE _8M /* db64360 rtc @ 0xfc80.0000 */
393 #define CFG_DEV2_SIZE _16M /* db64360 duart @ 0xfd00.0000 */
394 #define CFG_DEV3_SIZE _16M /* db64360 flash @ 0xfe00.0000 */
395 /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
397 /* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
398 #define CFG_DEV0_PAR 0x8FEFFFFF /* 32Bit sram */
399 #define CFG_DEV1_PAR 0x8FCFFFFF /* 8Bit rtc */
400 #define CFG_DEV2_PAR 0x8FCFFFFF /* 8Bit duart */
401 #define CFG_8BIT_BOOT_PAR 0x8FCFFFFF /* 8Bit flash */
402 #define CFG_32BIT_BOOT_PAR 0x8FEFFFFF /* 32Bit flash */
404 /* c 4 a 8 2 4 1 c */
405 /* 33 22|2222|22 22|111 1|11 11|1 1 | | */
406 /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
407 /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */
408 /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */
411 /* ronen - update MPP Control MV64360*/
412 #define CFG_MPP_CONTROL_0 0x02222222
413 #define CFG_MPP_CONTROL_1 0x11333011
414 #define CFG_MPP_CONTROL_2 0x40431111
415 #define CFG_MPP_CONTROL_3 0x00000044
417 /*# define CFG_SERIAL_PORT_MUX 0x00000102 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */
420 # define CFG_GPP_LEVEL_CONTROL 0x2c600000 /* 1111 1001 0000 1111 1100 0000 0000 0000*/
421 /* gpp[31] gpp[30] gpp[29] gpp[28] */
425 /* setup new config_value for MV64360 DDR-RAM !! */
426 # define CFG_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/
428 #define CFG_DUART_IO CFG_DEV2_SPACE
429 #define CFG_DUART_CHAN 1 /* channel to use for console */
430 #define CFG_INIT_CHAN1
431 #define CFG_INIT_CHAN2
433 #define SRAM_BASE CFG_DEV0_SPACE
434 #define SRAM_SIZE 0x00100000 /* 1 MB of sram */
437 /*-----------------------------------------------------------------------
439 *-----------------------------------------------------------------------
442 #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
443 #define PCI_HOST_FORCE 1 /* configure as pci host */
444 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
446 #define CONFIG_PCI /* include pci support */
447 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
448 #define CONFIG_PCI_PNP /* do pci plug-and-play */
449 #define CONFIG_EEPRO100 /* ronen - Support for Intel 82557/82559/82559ER chips */
451 /* PCI MEMORY MAP section */
452 #define CFG_PCI0_MEM_BASE 0x80000000
453 #define CFG_PCI0_MEM_SIZE _128M
454 #define CFG_PCI1_MEM_BASE 0x88000000
455 #define CFG_PCI1_MEM_SIZE _128M
457 #define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE)
458 #define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE)
460 /* PCI I/O MAP section */
461 #define CFG_PCI0_IO_BASE 0xfa000000
462 #define CFG_PCI0_IO_SIZE _16M
463 #define CFG_PCI1_IO_BASE 0xfb000000
464 #define CFG_PCI1_IO_SIZE _16M
466 #define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE)
467 #define CFG_PCI0_IO_SPACE_PCI (CFG_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */
468 #define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE)
469 #define CFG_PCI1_IO_SPACE_PCI (CFG_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */
471 #if defined (CONFIG_750CX)
472 #define CFG_PCI_IDSEL 0x0
474 #define CFG_PCI_IDSEL 0x30
476 /*----------------------------------------------------------------------
477 * Initial BAT mappings
481 * 1) GUARDED and WRITE_THRU not allowed in IBATS
482 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
486 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
487 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
488 #define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
489 #define CFG_DBAT0U CFG_IBAT0U
492 #define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
493 #define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
494 #define CFG_DBAT1L CFG_IBAT1L
495 #define CFG_DBAT1U CFG_IBAT1U
497 /* PCI0, PCI1 in one BAT */
498 #define CFG_IBAT2L BATL_NO_ACCESS
499 #define CFG_IBAT2U CFG_DBAT2U
500 #define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
501 #define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
503 /* GT regs, bootrom, all the devices, PCI I/O */
504 #define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
505 #define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
506 #define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
507 #define CFG_DBAT3U CFG_IBAT3U
509 /* I2C addresses for the two DIMM SPD chips */
510 #define DIMM0_I2C_ADDR 0x56
511 #define DIMM1_I2C_ADDR 0x54
514 * For booting Linux, the board info and command line data
515 * have to be in the first 8 MB of memory, since this is
516 * the maximum mapped by the Linux kernel during initialization.
518 #define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
520 /*-----------------------------------------------------------------------
523 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
524 #define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
526 #define CFG_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */
527 #define CFG_EXTRA_FLASH_WIDTH 4 /* 32 bit */
528 #define CFG_BOOT_FLASH_WIDTH 1 /* 8 bit */
530 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
531 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
532 #define CFG_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */
533 #define CFG_FLASH_CFI 1
535 #define CFG_ENV_IS_IN_FLASH 1
536 #define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
537 #define CFG_ENV_SECT_SIZE 0x10000
538 #define CFG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
539 /* #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */
541 /*-----------------------------------------------------------------------
542 * Cache Configuration
544 #define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
545 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
546 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
549 /*-----------------------------------------------------------------------
550 * L2CR setup -- make sure this is right for your board!
551 * look in include/mpc74xx.h for the defines used here
557 #if defined (CONFIG_750CX) || defined (CONFIG_750FX)
563 #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
564 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
568 #define L2_ENABLE (L2_INIT | L2CR_L2E)
571 * Internal Definitions
575 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
576 #define BOOTFLAG_WARM 0x02 /* Software reboot */
578 #define CFG_BOARD_ASM_INIT 1
580 #endif /* __CONFIG_H */