3 * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
37 #define CONFIG_MPC8272_FAMILY 1
38 #define CONFIG_IDS8247 1
39 #define CPU_ID_STR "MPC8247"
40 #define CONFIG_CPM2 1 /* Has a CPM2 */
42 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
44 #define CONFIG_BOOTCOUNT_LIMIT
46 #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
48 #undef CONFIG_BOOTARGS
50 #define CONFIG_EXTRA_ENV_SETTINGS \
52 "nfsargs=setenv bootargs root=/dev/nfs rw " \
53 "nfsroot=${serverip}:${rootpath}\0" \
54 "ramargs=setenv bootargs root=/dev/ram rw " \
55 "console=ttyS0,115200\0" \
56 "addip=setenv bootargs ${bootargs} " \
57 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
58 ":${hostname}:${netdev}:off panic=1\0" \
59 "flash_nfs=run nfsargs addip;" \
60 "bootm ${kernel_addr}\0" \
61 "flash_self=run ramargs addip;" \
62 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
63 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
64 "rootpath=/opt/eldk/ppc_82xx\0" \
65 "bootfile=/tftpboot/IDS8247/uImage\0" \
66 "kernel_addr=ff800000\0" \
67 "ramdisk_addr=ffa00000\0" \
69 #define CONFIG_BOOTCOMMAND "run flash_self"
71 #define CONFIG_MISC_INIT_R 1
73 /* enable I2C and select the hardware/software driver */
74 #undef CONFIG_HARD_I2C /* I2C with hardware support */
75 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
76 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
77 #define CFG_I2C_SLAVE 0x7F
80 * Software (bit-bang) I2C driver configuration
83 #define I2C_PORT 0 /* Port A=0, B=1, C=2, D=3 */
84 #define I2C_ACTIVE (iop->pdir |= 0x00000080)
85 #define I2C_TRISTATE (iop->pdir &= ~0x00000080)
86 #define I2C_READ ((iop->pdat & 0x00000080) != 0)
87 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000080; \
88 else iop->pdat &= ~0x00000080
89 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000100; \
90 else iop->pdat &= ~0x00000100
91 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
94 #define CFG_I2C_EEPROM_ADDR 0x50
95 #define CFG_I2C_EEPROM_ADDR_LEN 2
96 #define CFG_EEPROM_PAGE_WRITE_BITS 4
97 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
103 * select serial console configuration
104 * use the extern UART for the console
106 #define CONFIG_CONS_INDEX 1
107 #define CONFIG_BAUDRATE 115200
109 * NS16550 Configuration
112 #define CFG_NS16550_SERIAL
114 #define CFG_NS16550_REG_SIZE 1
116 #define CFG_NS16550_CLK 14745600
118 #define CFG_UART_BASE 0xE0000000
119 #define CFG_UART_SIZE 0x10000
121 #define CFG_NS16550_COM1 (CFG_UART_BASE + 0x8000)
124 * select ethernet configuration
126 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
127 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
130 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
131 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
133 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
134 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
135 #undef CONFIG_ETHER_NONE /* define if ether on something else */
136 #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
141 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
142 * - Enable Full Duplex in FSMR
144 # define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
145 # define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
146 # define CFG_CPMFCR_RAMTYPE 0
147 # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
150 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
151 #define CONFIG_8260_CLKIN 66666666 /* in Hz */
153 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
154 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
156 #undef CONFIG_WATCHDOG /* watchdog disabled */
158 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
160 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
164 * Command line configuration.
166 #include <config_cmd_default.h>
168 #define CONFIG_CMD_DHCP
169 #define CONFIG_CMD_NFS
170 #define CONFIG_CMD_NAND
171 #define CONFIG_CMD_I2C
172 #define CONFIG_CMD_SNTP
176 * Miscellaneous configurable options
178 #define CFG_LONGHELP /* undef to save memory */
179 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
180 #if defined(CONFIG_CMD_KGDB)
181 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
183 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
185 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
186 #define CFG_MAXARGS 16 /* max number of command args */
187 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
189 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
190 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
192 #define CFG_LOAD_ADDR 0x100000 /* default load address */
194 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
196 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
198 #define CFG_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
201 * For booting Linux, the board info and command line data
202 * have to be in the first 8 MB of memory, since this is
203 * the maximum mapped by the Linux kernel during initialization.
205 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
208 /* What should the base address of the main FLASH be and how big is
209 * it (in MBytes)? This must contain TEXT_BASE from board/ids8247/config.mk
210 * The main FLASH is whichever is connected to *CS0.
212 #define CFG_FLASH0_BASE 0xFFF00000
213 #define CFG_FLASH0_SIZE 8
215 /* Flash bank size (for preliminary settings)
217 #define CFG_FLASH_SIZE CFG_FLASH0_SIZE
219 /*-----------------------------------------------------------------------
222 #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
223 #define CFG_MAX_FLASH_SECT 64 /* max num of sects on one chip */
225 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
226 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
228 /* Environment in flash */
229 #define CFG_ENV_IS_IN_FLASH 1
230 #define CFG_ENV_ADDR (CFG_FLASH_BASE+0x60000)
231 #define CFG_ENV_SIZE 0x20000
232 #define CFG_ENV_SECT_SIZE 0x20000
234 /*-----------------------------------------------------------------------
236 *-----------------------------------------------------------------------
238 #if defined(CONFIG_CMD_NAND)
240 #define CFG_NAND_LEGACY
241 #define CFG_NAND0_BASE 0xE1000000
243 #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
244 #define SECTORSIZE 512
247 #define ADDR_COLUMN 1
249 #define ADDR_COLUMN_PAGE 3
251 #define NAND_ChipID_UNKNOWN 0x00
252 #define NAND_MAX_FLOORS 1
253 #define NAND_MAX_CHIPS 1
255 #define NAND_DISABLE_CE(nand) do \
257 *(((volatile __u8 *)(nand->IO_ADDR)) + 0xc) = 0; \
260 #define NAND_ENABLE_CE(nand) do \
262 *(((volatile __u8 *)(nand->IO_ADDR)) + 0x8) = 0; \
265 #define NAND_CTL_CLRALE(nandptr) do \
267 *(((volatile __u8 *)nandptr) + 0x8) = 0; \
270 #define NAND_CTL_SETALE(nandptr) do \
272 *(((volatile __u8 *)nandptr) + 0x9) = 0; \
275 #define NAND_CTL_CLRCLE(nandptr) do \
277 *(((volatile __u8 *)nandptr) + 0x8) = 0; \
280 #define NAND_CTL_SETCLE(nandptr) do \
282 *(((volatile __u8 *)nandptr) + 0xa) = 0; \
286 /* constant delay (see also tR in the datasheet) */
287 #define NAND_WAIT_READY(nand) do { \
291 /* use the R/B pin */
294 #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x2)) = (__u8)(d); } while(0)
295 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x1)) = (__u8)(d); } while(0)
296 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x0)) = (__u8)d; } while(0)
297 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr + 0x0)))
299 #endif /* CFG_CMD_NAND */
301 /*-----------------------------------------------------------------------
302 * Hard Reset Configuration Words
304 * if you change bits in the HRCW, you must also change the CFG_*
305 * defines for the various registers affected by the HRCW e.g. changing
306 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
308 #define CFG_HRCW_MASTER (HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000)
310 /* no slaves so just fill with zeros */
311 #define CFG_HRCW_SLAVE1 0
312 #define CFG_HRCW_SLAVE2 0
313 #define CFG_HRCW_SLAVE3 0
314 #define CFG_HRCW_SLAVE4 0
315 #define CFG_HRCW_SLAVE5 0
316 #define CFG_HRCW_SLAVE6 0
317 #define CFG_HRCW_SLAVE7 0
319 /*-----------------------------------------------------------------------
320 * Internal Memory Mapped Register
322 #define CFG_IMMR 0xF0000000
324 /*-----------------------------------------------------------------------
325 * Definitions for initial stack pointer and data area (in DPRAM)
327 #define CFG_INIT_RAM_ADDR CFG_IMMR
328 #define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
329 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
330 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
331 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
333 /*-----------------------------------------------------------------------
334 * Start addresses for the final memory configuration
335 * (Set up by the startup code)
336 * Please note that CFG_SDRAM_BASE _must_ start at 0
338 * 60x SDRAM is mapped at CFG_SDRAM_BASE
340 #define CFG_SDRAM_BASE 0x00000000
341 #define CFG_FLASH_BASE CFG_FLASH0_BASE
342 #define CFG_MONITOR_BASE TEXT_BASE
343 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
344 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
347 * Internal Definitions
351 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
352 #define BOOTFLAG_WARM 0x02 /* Software reboot */
355 /*-----------------------------------------------------------------------
356 * Cache Configuration
358 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
359 #if defined(CONFIG_CMD_KGDB)
360 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
363 /*-----------------------------------------------------------------------
364 * HIDx - Hardware Implementation-dependent Registers 2-11
365 *-----------------------------------------------------------------------
366 * HID0 also contains cache control - initially enable both caches and
367 * invalidate contents, then the final state leaves only the instruction
368 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
369 * but Soft reset does not.
371 * HID1 has only read-only information - nothing to set.
374 #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI)
375 #define CFG_HID0_FINAL 0
378 /*-----------------------------------------------------------------------
379 * RMR - Reset Mode Register 5-5
380 *-----------------------------------------------------------------------
381 * turn on Checkstop Reset Enable
385 /*-----------------------------------------------------------------------
386 * BCR - Bus Configuration 4-25
387 *-----------------------------------------------------------------------
391 /*-----------------------------------------------------------------------
392 * SIUMCR - SIU Module Configuration 4-31
393 *-----------------------------------------------------------------------
395 #define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01)
397 /*-----------------------------------------------------------------------
398 * SYPCR - System Protection Control 4-35
399 * SYPCR can only be written once after reset!
400 *-----------------------------------------------------------------------
401 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
403 #if defined(CONFIG_WATCHDOG)
404 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
405 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
407 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
408 SYPCR_SWRI|SYPCR_SWP)
409 #endif /* CONFIG_WATCHDOG */
411 /*-----------------------------------------------------------------------
412 * TMCNTSC - Time Counter Status and Control 4-40
413 *-----------------------------------------------------------------------
414 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
415 * and enable Time Counter
417 #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
419 /*-----------------------------------------------------------------------
420 * PISCR - Periodic Interrupt Status and Control 4-42
421 *-----------------------------------------------------------------------
422 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
425 #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
427 /*-----------------------------------------------------------------------
428 * SCCR - System Clock Control 9-8
429 *-----------------------------------------------------------------------
430 * Ensure DFBRG is Divide by 16
432 #define CFG_SCCR (0x00000028 | SCCR_DFBRG01)
434 /*-----------------------------------------------------------------------
435 * RCCR - RISC Controller Configuration 13-7
436 *-----------------------------------------------------------------------
441 * Init Memory Controller:
443 * Bank Bus Machine PortSz Device
444 * ---- --- ------- ------ ------
445 * 0 60x GPCM 16 bit FLASH
446 * 1 60x GPCM 8 bit NAND
447 * 2 60x SDRAM 32 bit SDRAM
448 * 3 60x GPCM 8 bit UART
452 #define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
454 /* Minimum mask to separate preliminary
455 * address ranges for CS[0:2]
457 #define CFG_GLOBAL_SDRAM_LIMIT (32<<20) /* less than 32 MB */
459 #define CFG_MPTPR 0x6600
461 /*-----------------------------------------------------------------------------
462 * Address for Mode Register Set (MRS) command
463 *-----------------------------------------------------------------------------
465 #define CFG_MRS_OFFS 0x00000110
470 #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
475 #define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\
478 #if defined(CONFIG_CMD_NAND)
479 /* Bank 1 - NAND Flash
481 #define CFG_NAND_BASE CFG_NAND0_BASE
482 #define CFG_NAND_SIZE 0x8000
484 #define CFG_OR_TIMING_NAND 0x000036
486 #define CFG_BR1_PRELIM ((CFG_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V )
487 #define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_NAND_SIZE) | CFG_OR_TIMING_NAND )
490 /* Bank 2 - 60x bus SDRAM
492 #define CFG_PSRT 0x20
493 #define CFG_LSRT 0x20
495 #define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
500 #define CFG_OR2_PRELIM CFG_OR2
503 /* SDRAM initialization values
505 #define CFG_OR2 ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
507 ORxS_ROWST_PBI0_A10 |\
510 #define CFG_PSDMR (PSDMR_SDAM_A13_IS_A5 |\
511 PSDMR_BSMA_A15_A17 |\
512 PSDMR_SDA10_PBI0_A11 |\
524 #define CFG_BR3_PRELIM ((CFG_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V )
525 #define CFG_OR3_PRELIM (((-CFG_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX )
527 #endif /* __CONFIG_H */