2 * (C) Copyright 2003 Picture Elements, Inc.
3 * Stephen Williams <steve@icarus.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options for the JSE board
33 * (Theoretically easy to change, but the board is fixed.)
37 /* JSE has a PPC405GPr */
38 #define CONFIG_405GP 1
39 /* ... which is a 4xxx series */
41 /* ... with a 33MHz OSC. connected to the SysCLK input */
42 #define CONFIG_SYS_CLK_FREQ 33333333
43 /* ... with on-chip memory here (4KBytes) */
44 #define CONFIG_SYS_OCM_DATA_ADDR 0xF4000000
45 #define CONFIG_SYS_OCM_DATA_SIZE 0x00001000
46 /* Do not set up locked dcache as init ram. */
47 #undef CONFIG_SYS_INIT_DCACHE_CS
49 /* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */
50 #define CONFIG_SYSTEMACE 1
51 #define CONFIG_SYS_SYSTEMACE_BASE 0xf0000000
52 #define CONFIG_SYS_SYSTEMACE_WIDTH 8
53 #define CONFIG_DOS_PARTITION 1
55 /* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
56 #define CONFIG_SYS_TEMP_STACK_OCM 1
57 /* ... place INIT RAM in the OCM address */
58 # define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
59 /* ... give it the whole init ram */
60 # define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE
61 /* ... Shave a bit off the end for global data */
62 # define CONFIG_SYS_GBL_DATA_SIZE 128
63 # define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
64 /* ... and place the stack pointer at the top of what's left. */
65 # define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
67 /* Enable board_pre_init function */
68 #define CONFIG_BOARD_PRE_INIT 1
69 #define CONFIG_BOARD_EARLY_INIT_F 1
70 /* Disable post-clk setup init function */
71 #undef CONFIG_BOARD_POSTCLK_INIT
72 /* Disable call to post_init_f: late init function. */
74 /* Enable DRAM test. */
75 #define CONFIG_SYS_DRAM_TEST 1
76 /* Enable misc_init_r function. */
77 #define CONFIG_MISC_INIT_R 1
79 /* JSE has EEPROM chips that are good for environment. */
80 #undef CONFIG_ENV_IS_IN_NVRAM
81 #undef CONFIG_ENV_IS_IN_FLASH
82 #define CONFIG_ENV_IS_IN_EEPROM 1
83 #undef CONFIG_ENV_IS_NOWHERE
85 /* This is the 7bit address of the device, not including P. */
86 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
87 /* After the device address, need one more address byte. */
88 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
89 /* The EEPROM is 512 bytes. */
90 #define CONFIG_SYS_EEPROM_SIZE 512
91 /* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
92 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
93 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
94 /* Put the environment in the second half. */
95 #define CONFIG_ENV_OFFSET 0x00
96 #define CONFIG_ENV_SIZE 512
98 /* The JSE connects UART1 to the console tap connector. */
99 #define CONFIG_CONS_INDEX 2
100 #define CONFIG_SYS_NS16550
101 #define CONFIG_SYS_NS16550_SERIAL
102 #define CONFIG_SYS_NS16550_REG_SIZE 1
103 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
105 /* Set console baudrate to 9600 */
106 #define CONFIG_BAUDRATE 9600
108 /* Size (bytes) of interrupt driven serial port buffer.
109 * Set to 0 to use polling instead of interrupts.
110 * Setting to 0 will also disable RTS/CTS handshaking.
112 #undef CONFIG_SERIAL_SOFTWARE_FIFO
115 * Configuration related to auto-boot.
117 * CONFIG_BOOTDELAY sets the delay (in seconds) that U-Boot will wait
118 * before resorting to autoboot. This value can be overridden by the
119 * bootdelay environment variable.
121 * CONFIG_AUTOBOOT_PROMPT is the string that U-Boot emits to warn the
122 * user that an autoboot will happen.
124 * CONFIG_BOOTCOMMAND is the sequence of commands that U-Boot will
125 * execute to boot the JSE. This loads the uimage and initrd.img files
126 * from CompactFlash into memory, then boots them from memory.
128 * CONFIG_BOOTARGS is the arguments passed to the Linux kernel to get
129 * it going on the JSE.
131 #define CONFIG_BOOTDELAY 5
132 #define CONFIG_BOOTARGS "root=/dev/ram0 init=/linuxrc rw"
133 #define CONFIG_BOOTCOMMAND "fatload ace 0 2000000 uimage; fatload ace 0 2100000 initrd.img; bootm 2000000 2100000"
136 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
137 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
139 #define CONFIG_PPC4xx_EMAC
140 #define CONFIG_MII 1 /* MII PHY management */
141 #define CONFIG_PHY_ADDR 1 /* PHY address */
142 #define CONFIG_NET_MULTI
148 #define CONFIG_BOOTP_BOOTFILESIZE
149 #define CONFIG_BOOTP_BOOTPATH
150 #define CONFIG_BOOTP_GATEWAY
151 #define CONFIG_BOOTP_HOSTNAME
155 * Command line configuration.
157 #include <config_cmd_default.h>
159 #define CONFIG_CMD_DHCP
160 #define CONFIG_CMD_EEPROM
161 #define CONFIG_CMD_ELF
162 #define CONFIG_CMD_FAT
163 #define CONFIG_CMD_FLASH
164 #define CONFIG_CMD_IRQ
165 #define CONFIG_CMD_MII
166 #define CONFIG_CMD_NET
167 #define CONFIG_CMD_PCI
168 #define CONFIG_CMD_PING
171 /* watchdog disabled */
172 #undef CONFIG_WATCHDOG
173 /* SPD EEPROM (sdram speed config) disabled */
174 #undef CONFIG_SPD_EEPROM
175 #undef SPD_EEPROM_ADDRESS
178 * Miscellaneous configurable options
180 #define CONFIG_SYS_LONGHELP /* undef to save memory */
181 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
183 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
184 #ifdef CONFIG_SYS_HUSH_PARSER
185 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
188 #if defined(CONFIG_CMD_KGDB)
189 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
191 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
193 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
194 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
195 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
197 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
198 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
201 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
202 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
203 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
204 * The Linux BASE_BAUD define should match this configuration.
205 * baseBaud = cpuClock/(uartDivisor*16)
206 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
207 * set Linux BASE_BAUD to 403200.
209 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
210 #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
211 #define CONFIG_SYS_BASE_BAUD 691200
213 /* The following table includes the supported baudrates */
214 #define CONFIG_SYS_BAUDRATE_TABLE \
215 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
217 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
218 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
220 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
222 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
223 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
224 #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
225 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
226 #define CONFIG_SYS_I2C_SLAVE 0x7F
229 /*-----------------------------------------------------------------------
231 *-----------------------------------------------------------------------
233 #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
234 #define PCI_HOST_FORCE 1 /* configure as pci host */
235 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
237 #define CONFIG_PCI /* include pci support */
238 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
239 #undef CONFIG_PCI_PNP /* do pci plug-and-play */
240 /* resource configuration */
242 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
243 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
244 #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
245 #define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
246 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
247 #define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
248 #define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
249 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
251 /*-----------------------------------------------------------------------
252 * External peripheral base address
253 *-----------------------------------------------------------------------
255 #undef CONFIG_IDE_LED /* no led for ide supported */
256 #undef CONFIG_IDE_RESET /* no reset for ide supported */
258 #define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000
259 #define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000
260 #define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000
262 /*-----------------------------------------------------------------------
263 * Start addresses for the final memory configuration
264 * (Set up by the startup code)
265 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
267 #define CONFIG_SYS_SDRAM_BASE 0x00000000
268 #define CONFIG_SYS_FLASH_BASE 0xFFF80000
269 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
270 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
271 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
274 * For booting Linux, the board info and command line data
275 * have to be in the first 8 MB of memory, since this is
276 * the maximum mapped by the Linux kernel during initialization.
278 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
280 /*-----------------------------------------------------------------------
283 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
284 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
286 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
287 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
290 * Init Memory Controller:
292 * BR0/1 and OR0/1 (FLASH)
295 #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
296 #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
299 /* Configuration Port location */
300 #define CONFIG_PORT_ADDR 0xF0000500
304 * Internal Definitions
308 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
309 #define BOOTFLAG_WARM 0x02 /* Software reboot */
311 #if defined(CONFIG_CMD_KGDB)
312 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
313 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
315 #endif /* __CONFIG_H */