2 * Configuation settings for the Freescale MCF5208EVBe.
4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * SPDX-License-Identifier: GPL-2.0+
14 * High Level Configuration Options
17 #define CONFIG_MCFUART
18 #define CONFIG_SYS_UART_PORT (0)
19 #define CONFIG_BAUDRATE 115200
21 #undef CONFIG_WATCHDOG
22 #define CONFIG_WATCHDOG_TIMEOUT 5000
24 /* Command line configuration */
25 #include <config_cmd_default.h>
27 #define CONFIG_CMD_CACHE
28 #define CONFIG_CMD_ELF
29 #define CONFIG_CMD_FLASH
31 #define CONFIG_CMD_MEMORY
32 #define CONFIG_CMD_MISC
33 #define CONFIG_CMD_MII
34 #define CONFIG_CMD_PING
35 #define CONFIG_CMD_REGINFO
40 # define CONFIG_MII_INIT 1
41 # define CONFIG_SYS_DISCOVER_PHY
42 # define CONFIG_SYS_RX_ETH_BUFFER 8
43 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
44 # define CONFIG_HAS_ETH1
46 # define CONFIG_SYS_FEC0_PINMUX 0
47 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
48 # define MCFFEC_TOUT_LOOP 50000
49 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
50 # ifndef CONFIG_SYS_DISCOVER_PHY
51 # define FECDUPLEX FULL
52 # define FECSPEED _100BASET
54 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
55 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
57 # endif /* CONFIG_SYS_DISCOVER_PHY */
65 #define CONFIG_SYS_I2C
66 #define CONFIG_SYS_I2C_FSL
67 #define CONFIG_SYS_FSL_I2C_SPEED 80000
68 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
69 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
70 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
72 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
73 #define CONFIG_UDP_CHECKSUM
76 # define CONFIG_IPADDR 192.162.1.2
77 # define CONFIG_NETMASK 255.255.255.0
78 # define CONFIG_SERVERIP 192.162.1.1
79 # define CONFIG_GATEWAYIP 192.162.1.1
80 #endif /* CONFIG_MCFFEC */
82 #define CONFIG_HOSTNAME M5208EVBe
83 #define CONFIG_EXTRA_ENV_SETTINGS \
85 "loadaddr=40010000\0" \
86 "u-boot=u-boot.bin\0" \
87 "load=tftp ${loadaddr) ${u-boot}\0" \
88 "upd=run load; run prog\0" \
89 "prog=prot off 0 3ffff;" \
91 "cp.b ${loadaddr} 0 ${filesize};" \
95 #define CONFIG_PRAM 512 /* 512 KB */
96 #define CONFIG_SYS_PROMPT "-> "
97 #define CONFIG_SYS_LONGHELP /* undef to save memory */
99 #ifdef CONFIG_CMD_KGDB
100 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
102 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
105 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
106 #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
107 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */
108 #define CONFIG_SYS_LOAD_ADDR 0x40010000
110 #define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */
111 #define CONFIG_SYS_PLL_ODR 0x36
112 #define CONFIG_SYS_PLL_FDR 0x7D
114 #define CONFIG_SYS_MBAR 0xFC000000
117 * Low Level Configuration Settings
118 * (address mappings, register initial values, etc.)
119 * You should know what you are doing if you make changes here.
121 /* Definitions for initial stack pointer and data area (in DPRAM) */
122 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
123 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */
124 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
125 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
126 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
129 * Start addresses for the final memory configuration
130 * (Set up by the startup code)
131 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
133 #define CONFIG_SYS_SDRAM_BASE 0x40000000
134 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
135 #define CONFIG_SYS_SDRAM_CFG1 0x43711630
136 #define CONFIG_SYS_SDRAM_CFG2 0x56670000
137 #define CONFIG_SYS_SDRAM_CTRL 0xE1002000
138 #define CONFIG_SYS_SDRAM_EMOD 0x80010000
139 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000
141 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
142 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
144 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
145 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
147 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
148 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
151 * For booting Linux, the board info and command line data
152 * have to be in the first 8 MB of memory, since this is
153 * the maximum mapped by the Linux kernel during initialization ??
155 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
156 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
158 /* FLASH organization */
159 #define CONFIG_SYS_FLASH_CFI
160 #ifdef CONFIG_SYS_FLASH_CFI
161 # define CONFIG_FLASH_CFI_DRIVER 1
162 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
163 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
164 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
165 # define CONFIG_SYS_MAX_FLASH_SECT 254 /* max number of sectors on one chip */
166 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
169 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
172 * Configuration for environment
173 * Environment is embedded in u-boot in the second sector of the flash
175 #define CONFIG_ENV_OFFSET 0x2000
176 #define CONFIG_ENV_SIZE 0x1000
177 #define CONFIG_ENV_SECT_SIZE 0x2000
178 #define CONFIG_ENV_IS_IN_FLASH 1
180 #define LDS_BOARD_TEXT \
181 . = DEFINED(env_offset) ? env_offset : .; \
182 common/env_embedded.o (.text*);
184 /* Cache Configuration */
185 #define CONFIG_SYS_CACHELINE_SIZE 16
187 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
188 CONFIG_SYS_INIT_RAM_SIZE - 8)
189 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
190 CONFIG_SYS_INIT_RAM_SIZE - 4)
191 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
192 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
193 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
194 CF_ACR_EN | CF_ACR_SM_ALL)
195 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
196 CF_CACR_DISD | CF_CACR_INVI | \
197 CF_CACR_CEIB | CF_CACR_DCM | \
200 /* Chipselect bank definitions */
209 #define CONFIG_SYS_CS0_BASE 0
210 #define CONFIG_SYS_CS0_MASK 0x007F0001
211 #define CONFIG_SYS_CS0_CTRL 0x00001FA0
213 #endif /* _M5208EVBE_H */