2 * Configuation settings for the Freescale MCF5329 FireEngine board.
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * SPDX-License-Identifier: GPL-2.0+
11 * board/config.h - configuration options, board specific
18 * High Level Configuration Options
22 #define CONFIG_MCFUART
23 #define CONFIG_SYS_UART_PORT (0)
24 #define CONFIG_BAUDRATE 115200
26 #undef CONFIG_WATCHDOG
27 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
32 #define CONFIG_BOOTP_BOOTFILESIZE
33 #define CONFIG_BOOTP_BOOTPATH
34 #define CONFIG_BOOTP_GATEWAY
35 #define CONFIG_BOOTP_HOSTNAME
37 /* Command line configuration */
38 #include <config_cmd_default.h>
40 #define CONFIG_CMD_BOOTD
41 #define CONFIG_CMD_CACHE
42 #define CONFIG_CMD_DHCP
43 #define CONFIG_CMD_ELF
44 #define CONFIG_CMD_FLASH
45 #define CONFIG_CMD_I2C
46 #define CONFIG_CMD_MEMORY
47 #define CONFIG_CMD_MISC
48 #define CONFIG_CMD_MII
49 #define CONFIG_CMD_PCI
50 #define CONFIG_CMD_PING
51 #define CONFIG_CMD_REGINFO
53 #undef CONFIG_CMD_LOADB
54 #undef CONFIG_CMD_LOADS
59 # define CONFIG_MII_INIT 1
60 # define CONFIG_SYS_DISCOVER_PHY
61 # define CONFIG_SYS_RX_ETH_BUFFER 8
62 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
64 # define CONFIG_SYS_FEC0_PINMUX 0
65 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
66 # define MCFFEC_TOUT_LOOP 50000
67 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
68 # ifndef CONFIG_SYS_DISCOVER_PHY
69 # define FECDUPLEX FULL
70 # define FECSPEED _100BASET
72 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
73 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
75 # endif /* CONFIG_SYS_DISCOVER_PHY */
83 #define CONFIG_SYS_I2C
84 #define CONFIG_SYS_i2C_FSL
85 #define CONFIG_SYS_FSL_I2C_SPEED 80000
86 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
87 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
88 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
89 #define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
90 #define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
91 #define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
93 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
94 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
95 #define CONFIG_BOOTFILE "u-boot.bin"
97 # define CONFIG_IPADDR 192.162.1.2
98 # define CONFIG_NETMASK 255.255.255.0
99 # define CONFIG_SERVERIP 192.162.1.1
100 # define CONFIG_GATEWAYIP 192.162.1.1
101 #endif /* FEC_ENET */
103 #define CONFIG_HOSTNAME M5235EVB
104 #define CONFIG_EXTRA_ENV_SETTINGS \
107 "u-boot=u-boot.bin\0" \
108 "load=tftp ${loadaddr) ${u-boot}\0" \
109 "upd=run load; run prog\0" \
110 "prog=prot off ffe00000 ffe3ffff;" \
111 "era ffe00000 ffe3ffff;" \
112 "cp.b ${loadaddr} ffe00000 ${filesize};"\
116 #define CONFIG_PRAM 512 /* 512 KB */
117 #define CONFIG_SYS_PROMPT "-> "
118 #define CONFIG_SYS_LONGHELP /* undef to save memory */
120 #if defined(CONFIG_KGDB)
121 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
123 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
126 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
127 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
128 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
129 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000)
131 #define CONFIG_SYS_CLK 75000000
132 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
134 #define CONFIG_SYS_MBAR 0x40000000
137 * Low Level Configuration Settings
138 * (address mappings, register initial values, etc.)
139 * You should know what you are doing if you make changes here.
141 /*-----------------------------------------------------------------------
142 * Definitions for initial stack pointer and data area (in DPRAM)
144 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
145 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
146 #define CONFIG_SYS_INIT_RAM_CTRL 0x21
147 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
148 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
150 /*-----------------------------------------------------------------------
151 * Start addresses for the final memory configuration
152 * (Set up by the startup code)
153 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
155 #define CONFIG_SYS_SDRAM_BASE 0x00000000
156 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
158 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
159 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
161 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
162 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
164 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
165 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
168 * For booting Linux, the board info and command line data
169 * have to be in the first 8 MB of memory, since this is
170 * the maximum mapped by the Linux kernel during initialization ??
172 /* Initial Memory map for Linux */
173 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
174 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
176 /*-----------------------------------------------------------------------
179 #define CONFIG_SYS_FLASH_CFI
180 #ifdef CONFIG_SYS_FLASH_CFI
181 # define CONFIG_FLASH_CFI_DRIVER 1
182 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
183 #ifdef NORFLASH_PS32BIT
184 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
186 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
188 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
189 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
190 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
193 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
195 /* Configuration for environment
196 * Environment is embedded in u-boot in the second sector of the flash
198 #define CONFIG_ENV_IS_IN_FLASH 1
200 #define LDS_BOARD_TEXT \
201 . = DEFINED(env_offset) ? env_offset : .; \
202 common/env_embedded.o (.text);
204 #ifdef NORFLASH_PS32BIT
205 # define CONFIG_ENV_OFFSET (0x8000)
206 # define CONFIG_ENV_SIZE 0x4000
207 # define CONFIG_ENV_SECT_SIZE 0x4000
209 # define CONFIG_ENV_OFFSET (0x4000)
210 # define CONFIG_ENV_SIZE 0x2000
211 # define CONFIG_ENV_SECT_SIZE 0x2000
214 /*-----------------------------------------------------------------------
215 * Cache Configuration
217 #define CONFIG_SYS_CACHELINE_SIZE 16
219 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
220 CONFIG_SYS_INIT_RAM_SIZE - 8)
221 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
222 CONFIG_SYS_INIT_RAM_SIZE - 4)
223 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV)
224 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
225 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
226 CF_ACR_EN | CF_ACR_SM_ALL)
227 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
228 CF_CACR_CEIB | CF_CACR_DCM | \
231 /*-----------------------------------------------------------------------
232 * Chipselect bank definitions
235 * CS0 - NOR Flash 1, 2, 4, or 8MB
244 #ifdef NORFLASH_PS32BIT
245 # define CONFIG_SYS_CS0_BASE 0xFFC00000
246 # define CONFIG_SYS_CS0_MASK 0x003f0001
247 # define CONFIG_SYS_CS0_CTRL 0x00001D00
249 # define CONFIG_SYS_CS0_BASE 0xFFE00000
250 # define CONFIG_SYS_CS0_MASK 0x001f0001
251 # define CONFIG_SYS_CS0_CTRL 0x00001D80
254 #endif /* _M5329EVB_H */