include/configs/M54455EVB.h

   1 /*
   2  * Configuation settings for the Freescale MCF54455 EVB board.
   3  *
   4  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M54455EVB_H
  15 #define _M54455EVB_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21 #define CONFIG_MCF5445x         /* define processor family */
  22 #define CONFIG_M54455           /* define processor type */
  23 #define CONFIG_M54455EVB        /* M54455EVB board */
  24
  25 #define CONFIG_MCFUART
  26 #define CONFIG_SYS_UART_PORT            (0)
  27 #define CONFIG_BAUDRATE         115200
  28
  29 #undef CONFIG_WATCHDOG
  30
  31 #define CONFIG_TIMESTAMP        /* Print image info with timestamp */
  32
  33 /*
  34  * BOOTP options
  35  */
  36 #define CONFIG_BOOTP_BOOTFILESIZE
  37 #define CONFIG_BOOTP_BOOTPATH
  38 #define CONFIG_BOOTP_GATEWAY
  39 #define CONFIG_BOOTP_HOSTNAME
  40
  41 /* Command line configuration */
  42 #include <config_cmd_default.h>
  43
  44 #define CONFIG_CMD_BOOTD
  45 #define CONFIG_CMD_CACHE
  46 #define CONFIG_CMD_DATE
  47 #define CONFIG_CMD_DHCP
  48 #define CONFIG_CMD_ELF
  49 #define CONFIG_CMD_EXT2
  50 #define CONFIG_CMD_FAT
  51 #define CONFIG_CMD_FLASH
  52 #define CONFIG_CMD_I2C
  53 #define CONFIG_CMD_IDE
  54 #define CONFIG_CMD_JFFS2
  55 #define CONFIG_CMD_MEMORY
  56 #define CONFIG_CMD_MISC
  57 #define CONFIG_CMD_MII
  58 #define CONFIG_CMD_NET
  59 #undef CONFIG_CMD_PCI
  60 #define CONFIG_CMD_PING
  61 #define CONFIG_CMD_REGINFO
  62 #define CONFIG_CMD_SPI
  63 #define CONFIG_CMD_SF
  64
  65 #undef CONFIG_CMD_LOADB
  66 #undef CONFIG_CMD_LOADS
  67
  68 /* Network configuration */
  69 #define CONFIG_MCFFEC
  70 #ifdef CONFIG_MCFFEC
  71 #       define CONFIG_MII               1
  72 #       define CONFIG_MII_INIT          1
  73 #       define CONFIG_SYS_DISCOVER_PHY
  74 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  75 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  76
  77 #       define CONFIG_SYS_FEC0_PINMUX   0
  78 #       define CONFIG_SYS_FEC1_PINMUX   0
  79 #       define CONFIG_SYS_FEC0_MIIBASE  CONFIG_SYS_FEC0_IOBASE
  80 #       define CONFIG_SYS_FEC1_MIIBASE  CONFIG_SYS_FEC0_IOBASE
  81 #       define MCFFEC_TOUT_LOOP 50000
  82 #       define CONFIG_HAS_ETH1
  83
  84 #       define CONFIG_BOOTDELAY 1       /* autoboot after 5 seconds */
  85 #       define CONFIG_BOOTARGS          "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
  86 #       define CONFIG_ETHADDR           00:e0:0c:bc:e5:60
  87 #       define CONFIG_ETH1ADDR          00:e0:0c:bc:e5:61
  88 #       define CONFIG_ETHPRIME          "FEC0"
  89 #       define CONFIG_IPADDR            192.162.1.2
  90 #       define CONFIG_NETMASK           255.255.255.0
  91 #       define CONFIG_SERVERIP          192.162.1.1
  92 #       define CONFIG_GATEWAYIP         192.162.1.1
  93 #       define CONFIG_OVERWRITE_ETHADDR_ONCE
  94
  95 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  96 #       ifndef CONFIG_SYS_DISCOVER_PHY
  97 #               define FECDUPLEX        FULL
  98 #               define FECSPEED         _100BASET
  99 #       else
 100 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 101 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 102 #               endif
 103 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
 104 #endif
 105
 106 #define CONFIG_HOSTNAME         M54455EVB
 107 #ifdef CONFIG_SYS_STMICRO_BOOT
 108 /* ST Micro serial flash */
 109 #define CONFIG_SYS_LOAD_ADDR2           0x40010013
 110 #define CONFIG_EXTRA_ENV_SETTINGS               \
 111         "netdev=eth0\0"                         \
 112         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
 113         "loadaddr=0x40010000\0"                 \
 114         "sbfhdr=sbfhdr.bin\0"                   \
 115         "uboot=u-boot.bin\0"                    \
 116         "load=tftp ${loadaddr} ${sbfhdr};"      \
 117         "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"       \
 118         "upd=run load; run prog\0"              \
 119         "prog=sf probe 0:1 1000000 3;"          \
 120         "sf erase 0 30000;"                     \
 121         "sf write ${loadaddr} 0 0x30000;"       \
 122         "save\0"                                \
 123         ""
 124 #else
 125 /* Atmel and Intel */
 126 #ifdef CONFIG_SYS_ATMEL_BOOT
 127 #       define CONFIG_SYS_UBOOT_END     0x0403FFFF
 128 #elif defined(CONFIG_SYS_INTEL_BOOT)
 129 #       define CONFIG_SYS_UBOOT_END     0x3FFFF
 130 #endif
 131 #define CONFIG_EXTRA_ENV_SETTINGS               \
 132         "netdev=eth0\0"                         \
 133         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
 134         "loadaddr=0x40010000\0"                 \
 135         "uboot=u-boot.bin\0"                    \
 136         "load=tftp ${loadaddr} ${uboot}\0"      \
 137         "upd=run load; run prog\0"              \
 138         "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE)     \
 139         " " __stringify(CONFIG_SYS_UBOOT_END) ";"               \
 140         "era " __stringify(CONFIG_SYS_FLASH_BASE) " "           \
 141         __stringify(CONFIG_SYS_UBOOT_END) ";"                   \
 142         "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE)  \
 143         " ${filesize}; save\0"                  \
 144         ""
 145 #endif
 146
 147 /* ATA configuration */
 148 #define CONFIG_ISO_PARTITION
 149 #define CONFIG_DOS_PARTITION
 150 #define CONFIG_IDE_RESET        1
 151 #define CONFIG_IDE_PREINIT      1
 152 #define CONFIG_ATAPI
 153 #undef CONFIG_LBA48
 154
 155 #define CONFIG_SYS_IDE_MAXBUS           1
 156 #define CONFIG_SYS_IDE_MAXDEVICE        2
 157
 158 #define CONFIG_SYS_ATA_BASE_ADDR        0x90000000
 159 #define CONFIG_SYS_ATA_IDE0_OFFSET      0
 160
 161 #define CONFIG_SYS_ATA_DATA_OFFSET      0xA0    /* Offset for data I/O                            */
 162 #define CONFIG_SYS_ATA_REG_OFFSET       0xA0    /* Offset for normal register accesses */
 163 #define CONFIG_SYS_ATA_ALT_OFFSET       0xC0    /* Offset for alternate registers           */
 164 #define CONFIG_SYS_ATA_STRIDE           4       /* Interval between registers                 */
 165
 166 /* Realtime clock */
 167 #define CONFIG_MCFRTC
 168 #undef RTC_DEBUG
 169 #define CONFIG_SYS_RTC_OSCILLATOR       (32 * CONFIG_SYS_HZ)
 170
 171 /* Timer */
 172 #define CONFIG_MCFTMR
 173 #undef CONFIG_MCFPIT
 174
 175 /* I2c */
 176 #define CONFIG_FSL_I2C
 177 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 178 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged               */
 179 #define CONFIG_SYS_I2C_SPEED            80000   /* I2C speed and slave address  */
 180 #define CONFIG_SYS_I2C_SLAVE            0x7F
 181 #define CONFIG_SYS_I2C_OFFSET           0x58000
 182 #define CONFIG_SYS_IMMR         CONFIG_SYS_MBAR
 183
 184 /* DSPI and Serial Flash */
 185 #define CONFIG_CF_SPI
 186 #define CONFIG_CF_DSPI
 187 #define CONFIG_HARD_SPI
 188 #define CONFIG_SYS_SBFHDR_SIZE          0x13
 189 #ifdef CONFIG_CMD_SPI
 190 #       define CONFIG_SPI_FLASH
 191 #       define CONFIG_SPI_FLASH_STMICRO
 192
 193 #       define CONFIG_SYS_DSPI_CTAR0            (DSPI_CTAR_TRSZ(7) | \
 194                                          DSPI_CTAR_PCSSCK_1CLK | \
 195                                          DSPI_CTAR_PASC(0) | \
 196                                          DSPI_CTAR_PDT(0) | \
 197                                          DSPI_CTAR_CSSCK(0) | \
 198                                          DSPI_CTAR_ASC(0) | \
 199                                          DSPI_CTAR_DT(1))
 200 #endif
 201
 202 /* PCI */
 203 #ifdef CONFIG_CMD_PCI
 204 #define CONFIG_PCI              1
 205 #define CONFIG_PCI_PNP          1
 206 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
 207
 208 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE  4
 209
 210 #define CONFIG_SYS_PCI_MEM_BUS          0xA0000000
 211 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
 212 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
 213
 214 #define CONFIG_SYS_PCI_IO_BUS           0xB1000000
 215 #define CONFIG_SYS_PCI_IO_PHYS          CONFIG_SYS_PCI_IO_BUS
 216 #define CONFIG_SYS_PCI_IO_SIZE          0x01000000
 217
 218 #define CONFIG_SYS_PCI_CFG_BUS          0xB0000000
 219 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
 220 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
 221 #endif
 222
 223 /* FPGA - Spartan 2 */
 224 /* experiment
 225 #define CONFIG_FPGA
 226 #define CONFIG_FPGA_COUNT       1
 227 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 228 #define CONFIG_SYS_FPGA_CHECK_CTRLC
 229 */
 230
 231 /* Input, PCI, Flexbus, and VCO */
 232 #define CONFIG_EXTRA_CLOCK
 233
 234 #define CONFIG_PRAM             2048    /* 2048 KB */
 235
 236 #define CONFIG_SYS_PROMPT               "-> "
 237 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 238
 239 #if defined(CONFIG_CMD_KGDB)
 240 #define CONFIG_SYS_CBSIZE                       1024    /* Console I/O Buffer Size */
 241 #else
 242 #define CONFIG_SYS_CBSIZE                       256     /* Console I/O Buffer Size */
 243 #endif
 244 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 245 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 246 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 247
 248 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + 0x10000)
 249
 250 #define CONFIG_SYS_HZ                   1000
 251
 252 #define CONFIG_SYS_MBAR         0xFC000000
 253
 254 /*
 255  * Low Level Configuration Settings
 256  * (address mappings, register initial values, etc.)
 257  * You should know what you are doing if you make changes here.
 258  */
 259
 260 /*-----------------------------------------------------------------------
 261  * Definitions for initial stack pointer and data area (in DPRAM)
 262  */
 263 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
 264 #define CONFIG_SYS_INIT_RAM_SIZE                0x8000  /* Size of used area in internal SRAM */
 265 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 266 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
 267 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 268 #define CONFIG_SYS_SBFHDR_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - 32)
 269
 270 /*-----------------------------------------------------------------------
 271  * Start addresses for the final memory configuration
 272  * (Set up by the startup code)
 273  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 274  */
 275 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 276 #define CONFIG_SYS_SDRAM_BASE1          0x48000000
 277 #define CONFIG_SYS_SDRAM_SIZE           256     /* SDRAM size in MB */
 278 #define CONFIG_SYS_SDRAM_CFG1           0x65311610
 279 #define CONFIG_SYS_SDRAM_CFG2           0x59670000
 280 #define CONFIG_SYS_SDRAM_CTRL           0xEA0B2000
 281 #define CONFIG_SYS_SDRAM_EMOD           0x40010000
 282 #define CONFIG_SYS_SDRAM_MODE           0x00010033
 283 #define CONFIG_SYS_SDRAM_DRV_STRENGTH   0xAA
 284
 285 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 286 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 287
 288 #ifdef CONFIG_CF_SBF
 289 #       define CONFIG_SERIAL_BOOT
 290 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_TEXT_BASE + 0x400)
 291 #else
 292 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_FLASH_BASE + 0x400)
 293 #endif
 294 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 295 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 296
 297 /* Reserve 256 kB for malloc() */
 298 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 299
 300 /*
 301  * For booting Linux, the board info and command line data
 302  * have to be in the first 8 MB of memory, since this is
 303  * the maximum mapped by the Linux kernel during initialization ??
 304  */
 305 /* Initial Memory map for Linux */
 306 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 307
 308 /*
 309  * Configuration for environment
 310  * Environment is not embedded in u-boot. First time runing may have env
 311  * crc error warning if there is no correct environment on the flash.
 312  */
 313 #ifdef CONFIG_CF_SBF
 314 #       define CONFIG_ENV_IS_IN_SPI_FLASH
 315 #       define CONFIG_ENV_SPI_CS                1
 316 #else
 317 #       define CONFIG_ENV_IS_IN_FLASH   1
 318 #endif
 319 #undef CONFIG_ENV_OVERWRITE
 320
 321 /*-----------------------------------------------------------------------
 322  * FLASH organization
 323  */
 324 #ifdef CONFIG_SYS_STMICRO_BOOT
 325 #       define CONFIG_SYS_FLASH_BASE            CONFIG_SYS_CS0_BASE
 326 #       define CONFIG_SYS_FLASH0_BASE           CONFIG_SYS_CS1_BASE
 327 #       define CONFIG_ENV_OFFSET                0x30000
 328 #       define CONFIG_ENV_SIZE          0x2000
 329 #       define CONFIG_ENV_SECT_SIZE     0x10000
 330 #endif
 331 #ifdef CONFIG_SYS_ATMEL_BOOT
 332 #       define CONFIG_SYS_FLASH_BASE            CONFIG_SYS_CS0_BASE
 333 #       define CONFIG_SYS_FLASH0_BASE           CONFIG_SYS_CS0_BASE
 334 #       define CONFIG_SYS_FLASH1_BASE           CONFIG_SYS_CS1_BASE
 335 #       define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x40000)
 336 #       define CONFIG_ENV_SIZE          0x2000
 337 #       define CONFIG_ENV_SECT_SIZE     0x10000
 338 #endif
 339 #ifdef CONFIG_SYS_INTEL_BOOT
 340 #       define CONFIG_SYS_FLASH_BASE            CONFIG_SYS_CS0_BASE
 341 #       define CONFIG_SYS_FLASH0_BASE           CONFIG_SYS_CS0_BASE
 342 #       define CONFIG_SYS_FLASH1_BASE           CONFIG_SYS_CS1_BASE
 343 #       define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x40000)
 344 #       define CONFIG_ENV_SIZE          0x2000
 345 #       define CONFIG_ENV_SECT_SIZE     0x20000
 346 #endif
 347
 348 #define CONFIG_SYS_FLASH_CFI
 349 #ifdef CONFIG_SYS_FLASH_CFI
 350
 351 #       define CONFIG_FLASH_CFI_DRIVER  1
 352 #       define CONFIG_SYS_FLASH_USE_BUFFER_WRITE        1
 353 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 354 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_8BIT
 355 #       define CONFIG_SYS_MAX_FLASH_BANKS       2       /* max number of memory banks */
 356 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 357 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 358 #       define CONFIG_SYS_FLASH_CHECKSUM
 359 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
 360 #       define CONFIG_FLASH_CFI_LEGACY
 361
 362 #ifdef CONFIG_FLASH_CFI_LEGACY
 363 #       define CONFIG_SYS_ATMEL_REGION          4
 364 #       define CONFIG_SYS_ATMEL_TOTALSECT       11
 365 #       define CONFIG_SYS_ATMEL_SECT            {1, 2, 1, 7}
 366 #       define CONFIG_SYS_ATMEL_SECTSZ          {0x4000, 0x2000, 0x8000, 0x10000}
 367 #endif
 368 #endif
 369
 370 /*
 371  * This is setting for JFFS2 support in u-boot.
 372  * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 373  */
 374 #ifdef CONFIG_CMD_JFFS2
 375 #ifdef CF_STMICRO_BOOT
 376 #       define CONFIG_JFFS2_DEV         "nor1"
 377 #       define CONFIG_JFFS2_PART_SIZE   0x01000000
 378 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000)
 379 #endif
 380 #ifdef CONFIG_SYS_ATMEL_BOOT
 381 #       define CONFIG_JFFS2_DEV         "nor1"
 382 #       define CONFIG_JFFS2_PART_SIZE   0x01000000
 383 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000)
 384 #endif
 385 #ifdef CONFIG_SYS_INTEL_BOOT
 386 #       define CONFIG_JFFS2_DEV         "nor0"
 387 #       define CONFIG_JFFS2_PART_SIZE   (0x01000000 - 0x500000)
 388 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
 389 #endif
 390 #endif
 391
 392 /*-----------------------------------------------------------------------
 393  * Cache Configuration
 394  */
 395 #define CONFIG_SYS_CACHELINE_SIZE               16
 396
 397 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 398                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 399 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 400                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 401 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_BCINVA + CF_CACR_ICINVA)
 402 #define CONFIG_SYS_DCACHE_INV           (CF_CACR_DCINVA)
 403 #define CONFIG_SYS_CACHE_ACR2           (CONFIG_SYS_SDRAM_BASE | \
 404                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 405                                          CF_ACR_EN | CF_ACR_SM_ALL)
 406 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_BEC | CF_CACR_IEC | \
 407                                          CF_CACR_ICINVA | CF_CACR_EUSP)
 408 #define CONFIG_SYS_CACHE_DCACR          ((CONFIG_SYS_CACHE_ICACR | \
 409                                          CF_CACR_DEC | CF_CACR_DDCM_P | \
 410                                          CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
 411
 412 /*-----------------------------------------------------------------------
 413  * Memory bank definitions
 414  */
 415 /*
 416  * CS0 - NOR Flash 1, 2, 4, or 8MB
 417  * CS1 - CompactFlash and registers
 418  * CS2 - CPLD
 419  * CS3 - FPGA
 420  * CS4 - Available
 421  * CS5 - Available
 422  */
 423
 424 #if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT)
 425  /* Atmel Flash */
 426 #define CONFIG_SYS_CS0_BASE             0x04000000
 427 #define CONFIG_SYS_CS0_MASK             0x00070001
 428 #define CONFIG_SYS_CS0_CTRL             0x00001140
 429 /* Intel Flash */
 430 #define CONFIG_SYS_CS1_BASE             0x00000000
 431 #define CONFIG_SYS_CS1_MASK             0x01FF0001
 432 #define CONFIG_SYS_CS1_CTRL             0x00000D60
 433
 434 #define CONFIG_SYS_ATMEL_BASE           CONFIG_SYS_CS0_BASE
 435 #else
 436 /* Intel Flash */
 437 #define CONFIG_SYS_CS0_BASE             0x00000000
 438 #define CONFIG_SYS_CS0_MASK             0x01FF0001
 439 #define CONFIG_SYS_CS0_CTRL             0x00000D60
 440  /* Atmel Flash */
 441 #define CONFIG_SYS_CS1_BASE             0x04000000
 442 #define CONFIG_SYS_CS1_MASK             0x00070001
 443 #define CONFIG_SYS_CS1_CTRL             0x00001140
 444
 445 #define CONFIG_SYS_ATMEL_BASE           CONFIG_SYS_CS1_BASE
 446 #endif
 447
 448 /* CPLD */
 449 #define CONFIG_SYS_CS2_BASE             0x08000000
 450 #define CONFIG_SYS_CS2_MASK             0x00070001
 451 #define CONFIG_SYS_CS2_CTRL             0x003f1140
 452
 453 /* FPGA */
 454 #define CONFIG_SYS_CS3_BASE             0x09000000
 455 #define CONFIG_SYS_CS3_MASK             0x00070001
 456 #define CONFIG_SYS_CS3_CTRL             0x00000020
 457
 458 #endif                          /* _M54455EVB_H */