2 * (C) Copyright 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
31 /***********************************************************
32 * High Level Configuration Options
34 ***********************************************************/
35 #define CONFIG_405GP 1 /* This is a PPC405 CPU */
36 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
37 #define CONFIG_MIP405 1 /* ...on a MIP405 board */
38 /***********************************************************
40 ***********************************************************/
41 #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
43 /***********************************************************
45 ***********************************************************/
46 #define CONFIG_COMMANDS \
65 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
66 #include <cmd_confdefs.h>
68 #define CFG_HUSH_PARSER
69 #define CFG_PROMPT_HUSH_PS2 "> "
70 /**************************************************************
72 * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
74 * The Atmel EEPROM uses 16Bit addressing.
75 ***************************************************************/
77 #define CONFIG_HARD_I2C /* I2c with hardware support */
78 #define CFG_I2C_SPEED 50000 /* I2C speed and slave address */
79 #define CFG_I2C_SLAVE 0x7F
81 #define CFG_I2C_EEPROM_ADDR 0x53 /* EEPROM 24C128/256 */
82 #define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
83 /* mask of address bits that overflow into the "EEPROM chip address" */
84 #undef CFG_I2C_EEPROM_ADDR_OVERFLOW
85 #define CFG_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
86 /* 64 byte page write mode using*/
87 /* last 6 bits of the address */
88 #define CFG_EEPROM_PAGE_WRITE_ENABLE /* enable Page write */
89 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
92 #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
93 #define CFG_ENV_OFFSET 0x00000 /* environment starts at the beginning of the EEPROM */
94 #define CFG_ENV_SIZE 0x00800 /* 2k bytes may be used for env vars */
96 /***************************************************************
97 * Definitions for Serial Presence Detect EEPROM address
98 * (to get SDRAM settings)
99 ***************************************************************/
100 #define SDRAM_EEPROM_WRITE_ADDRESS 0xA0
101 #define SDRAM_EEPROM_READ_ADDRESS 0xA1
103 /**************************************************************
104 * Environment definitions
105 **************************************************************/
106 #define CONFIG_BAUDRATE 9600 /* STD Baudrate */
107 #define CONFIG_BOOTDELAY 5
108 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
109 #define CONFIG_BOOT_RETRY_TIME -10 /* feature is avaiable but not enabled */
110 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
112 #define CONFIG_BOOTCOMMAND "diskboot 200000 0:1; bootm" /* autoboot command */
113 #define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
115 #define CONFIG_IPADDR 10.0.0.100
116 #define CONFIG_SERVERIP 10.0.0.1
117 #define CONFIG_PREBOOT
118 /***************************************************************
119 * defines if the console is stored in the environment
120 ***************************************************************/
121 #define CFG_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
122 /***************************************************************
123 * defines if an overwrite_console function exists
124 *************************************************************/
125 #define CFG_CONSOLE_OVERWRITE_ROUTINE
126 #define CFG_CONSOLE_INFO_QUIET
127 /***************************************************************
128 * defines if the overwrite_console should be stored in the
130 **************************************************************/
131 #undef CFG_CONSOLE_ENV_OVERWRITE
133 /**************************************************************
135 *************************************************************/
136 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
137 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
139 #define CONFIG_MISC_INIT_R
140 /***********************************************************
141 * Miscellaneous configurable options
142 **********************************************************/
143 #define CFG_LONGHELP /* undef to save memory */
144 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
145 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
146 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
148 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
150 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
151 #define CFG_MAXARGS 16 /* max number of command args */
152 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
154 #define CFG_MEMTEST_START 0x0100000 /* memtest works on */
155 #define CFG_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
157 #undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
158 #define CFG_BASE_BAUD 916667
160 /* The following table includes the supported baudrates */
161 #define CFG_BAUDRATE_TABLE \
162 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
163 57600, 115200, 230400, 460800, 921600 }
165 #define CFG_LOAD_ADDR 0x200000 /* default load address */
166 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
168 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
170 /*-----------------------------------------------------------------------
172 *-----------------------------------------------------------------------
174 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
175 #define PCI_HOST_FORCE 1 /* configure as pci host */
176 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
178 #define CONFIG_PCI /* include pci support */
179 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
180 #define CONFIG_PCI_PNP /* pci plug-and-play */
181 /* resource configuration */
182 #define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
183 #define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
184 #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
185 #define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
186 #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
187 #define CFG_PCI_PTM2LA 0x00000000 /* disabled */
188 #define CFG_PCI_PTM2MS 0x00000000 /* disabled */
189 #define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
191 /*-----------------------------------------------------------------------
192 * Start addresses for the final memory configuration
193 * (Set up by the startup code)
194 * Please note that CFG_SDRAM_BASE _must_ start at 0
196 #define CFG_SDRAM_BASE 0x00000000
197 #define CFG_FLASH_BASE 0xFFF80000
198 #define CFG_MONITOR_BASE CFG_FLASH_BASE
199 #define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
200 #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
203 * For booting Linux, the board info and command line data
204 * have to be in the first 8 MB of memory, since this is
205 * the maximum mapped by the Linux kernel during initialization.
207 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
208 /*-----------------------------------------------------------------------
211 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
212 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
214 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
215 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
217 /*-----------------------------------------------------------------------
218 * Cache Configuration
220 #define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
221 #define CFG_CACHELINE_SIZE 32 /* ... */
222 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
223 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
227 * Init Memory Controller:
230 #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
231 #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
233 #define CONFIG_BOARD_PRE_INIT
235 /* Peripheral Bus Mapping */
236 #define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/
237 #define PER_UART0_ADDR 0xF4100000 /* smallest window is 1MByte 0x10 0000*/
238 #define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/
240 #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
241 #define CONFIG_PORT_ADDR PER_PLD_ADDR + 5
245 /*-----------------------------------------------------------------------
246 * Definitions for initial stack pointer and data area (in On Chip SRAM)
248 #define CFG_TEMP_STACK_OCM 1
249 #define CFG_OCM_DATA_ADDR 0xF0000000
250 #define CFG_OCM_DATA_SIZE 0x1000
251 #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */
252 #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */
253 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
254 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
255 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
258 * Internal Definitions
262 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
263 #define BOOTFLAG_WARM 0x02 /* Software reboot */
266 /***********************************************************************
267 * External peripheral base address
268 ***********************************************************************/
269 #define CFG_ISA_IO_BASE_ADDRESS 0xE8000000
271 /***********************************************************************
273 ***********************************************************************/
274 #define CONFIG_LAST_STAGE_INIT
275 /************************************************************
277 ***********************************************************/
278 #define CONFIG_MII 1 /* MII PHY management */
279 #define CONFIG_PHY_ADDR 1 /* PHY address */
281 /************************************************************
283 ***********************************************************/
284 #define CONFIG_RTC_MC146818
285 #undef CONFIG_WATCHDOG /* watchdog disabled */
287 /************************************************************
289 ************************************************************/
290 #define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */
291 #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
293 #define CFG_ATA_BASE_ADDR CFG_ISA_IO_BASE_ADDRESS /* base address */
294 #define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
295 #define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
296 #define CFG_ATA_DATA_OFFSET 0 /* data reg offset */
297 #define CFG_ATA_REG_OFFSET 0 /* reg offset */
298 #define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
300 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
301 #undef CONFIG_IDE_LED /* no led for ide supported */
302 #define CONFIG_IDE_RESET /* reset for ide supported... */
303 #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
305 /************************************************************
306 * ATAPI support (experimental)
307 ************************************************************/
308 #define CONFIG_ATAPI /* enable ATAPI Support */
310 /************************************************************
311 * SCSI support (experimental) only SYM53C8xx supported
312 ************************************************************/
313 #undef CONFIG_SCSI_SYM53C8XX
315 #ifdef CONFIG_SCSI_SYM53C8XX
316 #define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */
317 #define CFG_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */
318 #define CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */
319 #define CFG_SCSI_SPIN_UP_TIME 2
320 #endif /* CONFIG_SCSI_SYM53C8XX */
321 /************************************************************
322 * DISK Partition support
323 ************************************************************/
324 #define CONFIG_DOS_PARTITION
325 #define CONFIG_MAC_PARTITION
326 #define CONFIG_ISO_PARTITION /* Experimental */
328 /************************************************************
329 * Disk-On-Chip configuration
330 ************************************************************/
331 #define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
332 #define CFG_DOC_SHORT_TIMEOUT
333 #define CFG_DOC_SUPPORT_2000
334 #define CFG_DOC_SUPPORT_MILLENNIUM
335 /************************************************************
337 ************************************************************/
338 #undef CONFIG_ISA_KEYBOARD
340 /************************************************************
342 ************************************************************/
343 #define CONFIG_VIDEO /*To enable video controller support */
344 #define CONFIG_VIDEO_CT69000
345 #define CONFIG_CFB_CONSOLE
346 #define CONFIG_VIDEO_LOGO
347 #define CONFIG_CONSOLE_EXTRA_INFO
348 #define CONFIG_VGA_AS_SINGLE_DEVICE
349 #define CONFIG_VIDEO_SW_CURSOR
350 #undef CONFIG_VIDEO_ONBOARD
351 /************************************************************
352 * USB support EXPERIMENTAL
353 ************************************************************/
354 #define CONFIG_USB_UHCI
355 #define CONFIG_USB_KEYBOARD
356 #define CONFIG_USB_STORAGE
358 /* Enable needed helper functions */
359 #define CFG_DEVICE_DEREGISTER /* needs device_deregister */
361 /************************************************************
363 ************************************************************/
364 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
365 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
366 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
369 /************************************************************
371 ************************************************************/
372 #define VERSION_TAG "released"
373 #define CONFIG_IDENT_STRING "\n(c) 2002 by MPL AG Switzerland, MEV-10072-001 " VERSION_TAG
376 #endif /* __CONFIG_H */