2 * Copyright 2004 Freescale Semiconductor.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * mpc8555cds board configuration file
26 * Please refer to doc/README.mpc85xxcds for more info.
32 /* High Level Configuration Options */
33 #define CONFIG_BOOKE 1 /* BOOKE */
34 #define CONFIG_E500 1 /* BOOKE e500 family */
35 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
36 #define CONFIG_CPM2 1 /* has CPM2 */
37 #define CONFIG_MPC8555 1 /* MPC8555 specific */
38 #define CONFIG_MPC8555CDS 1 /* MPC8555CDS board specific */
41 #define CONFIG_TSEC_ENET /* tsec ethernet support */
42 #define CONFIG_ENV_OVERWRITE
43 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
44 #define CONFIG_DDR_ECC /* only for ECC DDR module */
45 #define CONFIG_DDR_DLL /* possible DLL fix needed */
46 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
49 * When initializing flash, if we cannot find the manufacturer ID,
50 * assume this is the AMD flash associated with the CDS board.
51 * This allows booting from a promjet.
53 #define CONFIG_ASSUME_AMD_FLASH
55 #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
58 extern unsigned long get_clock_freq(void);
60 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
63 * These can be toggled for performance analysis, otherwise use default.
65 #define CONFIG_L2_CACHE /* toggle L2 cache */
66 #define CONFIG_BTB /* toggle branch predition */
67 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
69 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
71 #undef CFG_DRAM_TEST /* memory test, takes time */
72 #define CFG_MEMTEST_START 0x00200000 /* memtest works on */
73 #define CFG_MEMTEST_END 0x00400000
76 * Base addresses -- Note these are effective addresses where the
77 * actual resources get mapped (not physical addresses)
79 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
80 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
81 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
86 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
87 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
89 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
92 * Make sure required options are set
94 #ifndef CONFIG_SPD_EEPROM
95 #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
98 #undef CONFIG_CLOCKS_IN_MHZ
102 * Local Bus Definitions
106 * FLASH on the Local Bus
107 * Two banks, 8M each, using the CFI driver.
108 * Boot from BR0/OR0 bank at 0xff00_0000
109 * Alternate BR1/OR1 bank at 0xff80_0000
112 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
113 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
114 * Port Size = 16 bits = BRx[19:20] = 10
115 * Use GPCM = BRx[24:26] = 000
116 * Valid = BRx[31] = 1
118 * 0 4 8 12 16 20 24 28
119 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
120 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
123 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
124 * Reserved ORx[17:18] = 11, confusion here?
126 * ACS = half cycle delay = ORx[21:22] = 11
127 * SCY = 6 = ORx[24:27] = 0110
128 * TRLX = use relaxed timing = ORx[29] = 1
129 * EAD = use external address latch delay = OR[31] = 1
131 * 0 4 8 12 16 20 24 28
132 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
135 #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */
137 #define CFG_BR0_PRELIM 0xff801001
138 #define CFG_BR1_PRELIM 0xff001001
140 #define CFG_OR0_PRELIM 0xff806e65
141 #define CFG_OR1_PRELIM 0xff806e65
143 #define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE}
144 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */
145 #define CFG_MAX_FLASH_SECT 128 /* sectors per device */
146 #undef CFG_FLASH_CHECKSUM
147 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
148 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
150 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
152 #define CFG_FLASH_CFI_DRIVER
153 #define CFG_FLASH_CFI
154 #define CFG_FLASH_EMPTY_INFO
158 * SDRAM on the Local Bus
160 #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
161 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
164 * Base Register 2 and Option Register 2 configure SDRAM.
165 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
168 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
169 * port-size = 32-bits = BR2[19:20] = 11
170 * no parity checking = BR2[21:22] = 00
171 * SDRAM for MSEL = BR2[24:26] = 011
174 * 0 4 8 12 16 20 24 28
175 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
177 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
178 * FIXME: the top 17 bits of BR2.
181 #define CFG_BR2_PRELIM 0xf0001861
184 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
187 * 64MB mask for AM, OR2[0:7] = 1111 1100
188 * XAM, OR2[17:18] = 11
189 * 9 columns OR2[19-21] = 010
190 * 13 rows OR2[23-25] = 100
191 * EAD set for extra time OR[31] = 1
193 * 0 4 8 12 16 20 24 28
194 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
197 #define CFG_OR2_PRELIM 0xfc006901
199 #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
200 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */
201 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
202 #define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
207 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
208 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
209 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
210 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
211 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
212 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
213 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
214 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
215 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
216 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
218 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
219 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
220 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
221 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
222 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
223 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
224 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
225 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
228 * Common settings for all Local Bus SDRAM commands.
229 * At run time, either BSMA1516 (for CPU 1.1)
230 * or BSMA1617 (for CPU 1.0) (old)
233 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \
234 | CFG_LBC_LSDMR_PRETOACT7 \
235 | CFG_LBC_LSDMR_ACTTORW7 \
236 | CFG_LBC_LSDMR_BL8 \
237 | CFG_LBC_LSDMR_WRC4 \
238 | CFG_LBC_LSDMR_CL3 \
239 | CFG_LBC_LSDMR_RFEN \
243 * The CADMUS registers are connected to CS3 on CDS.
244 * The new memory map places CADMUS at 0xf8000000.
247 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
248 * port-size = 8-bits = BR[19:20] = 01
249 * no parity checking = BR[21:22] = 00
250 * GPMC for MSEL = BR[24:26] = 000
253 * 0 4 8 12 16 20 24 28
254 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
257 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
258 * disable buffer ctrl OR[19] = 0
262 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
266 * EAD extra time OR[31] = 1
268 * 0 4 8 12 16 20 24 28
269 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
272 #define CADMUS_BASE_ADDR 0xf8000000
273 #define CFG_BR3_PRELIM 0xf8000801
274 #define CFG_OR3_PRELIM 0xfff00ff7
276 #define CONFIG_L1_INIT_RAM
277 #define CFG_INIT_RAM_LOCK 1
278 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
279 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
281 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
282 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
283 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
285 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
286 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
289 #define CONFIG_CONS_INDEX 2
290 #undef CONFIG_SERIAL_SOFTWARE_FIFO
292 #define CFG_NS16550_SERIAL
293 #define CFG_NS16550_REG_SIZE 1
294 #define CFG_NS16550_CLK get_bus_freq(0)
296 #define CFG_BAUDRATE_TABLE \
297 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
299 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
300 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
302 /* Use the HUSH parser */
303 #define CFG_HUSH_PARSER
304 #ifdef CFG_HUSH_PARSER
305 #define CFG_PROMPT_HUSH_PS2 "> "
309 #define CONFIG_HARD_I2C /* I2C with hardware support */
310 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
311 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
312 #define CFG_I2C_EEPROM_ADDR 0x57
313 #define CFG_I2C_SLAVE 0x7F
314 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
318 * Addresses are mapped 1-1.
320 #define CFG_PCI1_MEM_BASE 0x80000000
321 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
322 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
323 #define CFG_PCI1_IO_BASE 0xe2000000
324 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
325 #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
327 #define CFG_PCI2_MEM_BASE 0xa0000000
328 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
329 #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
330 #define CFG_PCI2_IO_BASE 0xe3000000
331 #define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE
332 #define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
335 #if defined(CONFIG_PCI)
337 #define CONFIG_NET_MULTI
338 #define CONFIG_PCI_PNP /* do pci plug-and-play */
340 #undef CONFIG_EEPRO100
343 #if !defined(CONFIG_PCI_PNP)
344 #define PCI_ENET0_IOADDR 0xe0000000
345 #define PCI_ENET0_MEMADDR 0xe0000000
346 #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/
349 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
350 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
352 #endif /* CONFIG_PCI */
355 #if defined(CONFIG_TSEC_ENET)
357 #ifndef CONFIG_NET_MULTI
358 #define CONFIG_NET_MULTI 1
361 #define CONFIG_MII 1 /* MII PHY management */
362 #define CONFIG_MPC85XX_TSEC1 1
363 #define CONFIG_MPC85XX_TSEC2 1
364 #undef CONFIG_MPC85XX_FEC
365 #define TSEC1_PHY_ADDR 0
366 #define TSEC2_PHY_ADDR 1
367 #define FEC_PHY_ADDR 3
368 #define TSEC1_PHYIDX 0
369 #define TSEC2_PHYIDX 0
371 #define CONFIG_ETHPRIME "MOTO ENET0"
373 #endif /* CONFIG_TSEC_ENET */
378 #define CFG_ENV_IS_IN_FLASH 1
379 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
380 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
381 #define CFG_ENV_SIZE 0x2000
383 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
384 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
386 #if defined(CONFIG_PCI)
387 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
393 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
398 #include <cmd_confdefs.h>
400 #undef CONFIG_WATCHDOG /* watchdog disabled */
403 * Miscellaneous configurable options
405 #define CFG_LONGHELP /* undef to save memory */
406 #define CFG_LOAD_ADDR 0x2000000 /* default load address */
407 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
408 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
409 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
411 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
413 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
414 #define CFG_MAXARGS 16 /* max number of command args */
415 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
416 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
419 * For booting Linux, the board info and command line data
420 * have to be in the first 8 MB of memory, since this is
421 * the maximum mapped by the Linux kernel during initialization.
423 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
425 /* Cache Configuration */
426 #define CFG_DCACHE_SIZE 32768
427 #define CFG_CACHELINE_SIZE 32
428 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
429 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
433 * Internal Definitions
437 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
438 #define BOOTFLAG_WARM 0x02 /* Software reboot */
440 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
441 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
442 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
446 * Environment Configuration
449 /* The mac addresses for all ethernet interface */
450 #if defined(CONFIG_TSEC_ENET)
451 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD
452 #define CONFIG_HAS_ETH1
453 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
454 #define CONFIG_HAS_ETH2
455 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
458 #define CONFIG_IPADDR 192.168.1.253
460 #define CONFIG_HOSTNAME unknown
461 #define CONFIG_ROOTPATH /nfsroot
462 #define CONFIG_BOOTFILE your.uImage
464 #define CONFIG_SERVERIP 192.168.1.1
465 #define CONFIG_GATEWAYIP 192.168.1.1
466 #define CONFIG_NETMASK 255.255.255.0
468 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
470 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
471 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
473 #define CONFIG_BAUDRATE 115200
475 #define CONFIG_EXTRA_ENV_SETTINGS \
477 "consoledev=ttyS1\0" \
478 "ramdiskaddr=400000\0" \
479 "ramdiskfile=your.ramdisk.u-boot\0"
481 #define CONFIG_NFSBOOTCOMMAND \
482 "setenv bootargs root=/dev/nfs rw " \
483 "nfsroot=$serverip:$rootpath " \
484 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
485 "console=$consoledev,$baudrate $othbootargs;" \
486 "tftp $loadaddr $bootfile;" \
489 #define CONFIG_RAMBOOTCOMMAND \
490 "setenv bootargs root=/dev/ram rw " \
491 "console=$consoledev,$baudrate $othbootargs;" \
492 "tftp $ramdiskaddr $ramdiskfile;" \
493 "tftp $loadaddr $bootfile;" \
494 "bootm $loadaddr $ramdiskaddr"
496 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
498 #endif /* __CONFIG_H */