2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * P010 RDB board configuration file
31 #define CONFIG_PHYS_64BIT
34 #ifdef CONFIG_P1010RDB
36 #define CONFIG_NAND_FSL_IFC
40 #define CONFIG_RAMBOOT_SDCARD
41 #define CONFIG_SYS_TEXT_BASE 0x11000000
42 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
45 #ifdef CONFIG_SPIFLASH
46 #define CONFIG_RAMBOOT_SPIFLASH
47 #define CONFIG_SYS_TEXT_BASE 0x11000000
48 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
51 #ifdef CONFIG_NAND /* NAND Boot */
52 #define CONFIG_RAMBOOT_NAND
53 #define CONFIG_NAND_U_BOOT
54 #define CONFIG_SYS_TEXT_BASE_SPL 0xff800000
55 #ifdef CONFIG_NAND_SPL
56 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL
58 #define CONFIG_SYS_TEXT_BASE 0x11001000
59 #endif /* CONFIG_NAND_SPL */
62 #ifndef CONFIG_SYS_TEXT_BASE
63 #define CONFIG_SYS_TEXT_BASE 0xeff80000
66 #ifndef CONFIG_RESET_VECTOR_ADDRESS
67 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
70 #ifndef CONFIG_SYS_MONITOR_BASE
71 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
74 /* High Level Configuration Options */
75 #define CONFIG_BOOKE /* BOOKE */
76 #define CONFIG_E500 /* BOOKE e500 family */
77 #define CONFIG_MPC85xx
78 #define CONFIG_FSL_IFC /* Enable IFC Support */
79 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
81 #define CONFIG_PCI /* Enable PCI/PCIE */
82 #if defined(CONFIG_PCI)
83 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
84 #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
85 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
86 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
87 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
89 #define CONFIG_CMD_NET
90 #define CONFIG_CMD_PCI
92 #define CONFIG_E1000 /* E1000 pci Ethernet card*/
96 * Memory space is mapped 1-1, but I/O space must start from 0.
98 /* controller 1, Slot 1, tgtid 1, Base address a000 */
99 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot"
100 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
101 #ifdef CONFIG_PHYS_64BIT
102 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
103 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
105 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
106 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
108 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
109 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
110 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
111 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
112 #ifdef CONFIG_PHYS_64BIT
113 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
115 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
118 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
119 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot"
120 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
121 #ifdef CONFIG_PHYS_64BIT
122 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
123 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
125 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
126 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
128 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
129 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
130 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
131 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
132 #ifdef CONFIG_PHYS_64BIT
133 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
135 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
138 #define CONFIG_PCI_PNP /* do pci plug-and-play */
140 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
141 #define CONFIG_DOS_PARTITION
144 #define CONFIG_FSL_LAW /* Use common FSL init code */
145 #define CONFIG_TSEC_ENET
146 #define CONFIG_ENV_OVERWRITE
148 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */
149 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */
151 #ifndef CONFIG_SDCARD
152 #define CONFIG_MISC_INIT_R
155 #define CONFIG_HWCONFIG
157 * These can be toggled for performance analysis, otherwise use default.
159 #define CONFIG_L2_CACHE /* toggle L2 cache */
160 #define CONFIG_BTB /* toggle branch predition */
162 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
164 #define CONFIG_ENABLE_36BIT_PHYS
166 #ifdef CONFIG_PHYS_64BIT
167 #define CONFIG_ADDR_MAP 1
168 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
171 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
172 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
173 #define CONFIG_PANIC_HANG /* do not reset board on panic */
176 #define CONFIG_FSL_DDR3
177 #define CONFIG_DDR_RAW_TIMING
178 #define CONFIG_DDR_SPD
179 #define CONFIG_SYS_SPD_BUS_NUM 1
180 #define SPD_EEPROM_ADDRESS 0x52
182 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
185 extern unsigned long get_sdram_size(void);
187 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
188 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
189 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
191 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
192 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
194 /* DDR3 Controller Settings */
195 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
196 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
197 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
198 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
199 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
200 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
201 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
203 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
204 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
205 #define CONFIG_SYS_DDR_RCW_1 0x00000000
206 #define CONFIG_SYS_DDR_RCW_2 0x00000000
207 #define CONFIG_SYS_DDR_CONTROL 0x470C0000 /* Type = DDR3 */
208 #define CONFIG_SYS_DDR_CONTROL_2 0x04401010
209 #define CONFIG_SYS_DDR_TIMING_4 0x00000001
210 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
212 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
213 #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004
214 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4644
215 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
216 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
217 #define CONFIG_SYS_DDR_MODE_1_800 0x40461520
218 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
219 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
220 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608
222 /* settings for DDR3 at 667MT/s */
223 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
224 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
225 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
226 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
227 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
228 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210
229 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000
230 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
231 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
233 #define CONFIG_SYS_CCSRBAR 0xffe00000
234 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
236 /* Don't relocate CCSRBAR while in NAND_SPL */
237 #ifdef CONFIG_NAND_SPL
238 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
244 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable
245 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable
246 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
248 * Localbus non-cacheable
249 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable
250 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
251 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
252 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
255 /* In case of SD card boot, IFC interface is not available because of muxing */
257 #define CONFIG_SYS_NO_FLASH
262 /* NOR Flash on IFC */
263 #define CONFIG_SYS_FLASH_BASE 0xee000000
264 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
266 #ifdef CONFIG_PHYS_64BIT
267 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
269 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
272 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
273 CSPR_PORT_SIZE_16 | \
276 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
277 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
278 /* NOR Flash Timing Params */
279 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
280 FTIM0_NOR_TEADC(0x5) | \
282 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
283 FTIM1_NOR_TRAD_NOR(0x0f)
284 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
285 FTIM2_NOR_TCH(0x4) | \
287 #define CONFIG_SYS_NOR_FTIM3 0x0
289 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
290 #define CONFIG_SYS_FLASH_QUIET_TEST
291 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
292 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
294 #undef CONFIG_SYS_FLASH_CHECKSUM
295 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
296 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
298 /* CFI for NOR Flash */
299 #define CONFIG_FLASH_CFI_DRIVER
300 #define CONFIG_SYS_FLASH_CFI
301 #define CONFIG_SYS_FLASH_EMPTY_INFO
302 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
304 /* NAND Flash on IFC */
305 #define CONFIG_SYS_NAND_BASE 0xff800000
306 #ifdef CONFIG_PHYS_64BIT
307 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
309 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
312 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
316 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
317 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
318 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
319 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
320 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
321 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \
322 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
323 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */
325 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
326 #define CONFIG_SYS_MAX_NAND_DEVICE 1
327 #define CONFIG_MTD_NAND_VERIFY_WRITE
328 #define CONFIG_CMD_NAND
329 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
331 /* NAND Flash Timing Params */
332 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
333 FTIM0_NAND_TWP(0x0C) | \
334 FTIM0_NAND_TWCHT(0x04) | \
336 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
337 FTIM1_NAND_TWBE(0x1d) | \
338 FTIM1_NAND_TRR(0x07) | \
340 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
341 FTIM2_NAND_TREH(0x05) | \
342 FTIM2_NAND_TWHRE(0x0f)
343 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
345 #define CONFIG_SYS_NAND_DDR_LAW 11
347 /* Set up IFC registers for boot location NOR/NAND */
348 #ifdef CONFIG_NAND_U_BOOT
349 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
350 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
351 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
352 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
353 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
354 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
355 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
356 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
357 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
358 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
359 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
360 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
361 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
362 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
364 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
365 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
366 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
367 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
368 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
369 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
370 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
371 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
372 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
373 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
374 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
375 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
376 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
377 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
380 /* NAND boot: 8K NAND loader config */
381 #define CONFIG_SYS_NAND_SPL_SIZE 0x2000
382 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
383 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE)
384 #define CONFIG_SYS_NAND_U_BOOT_START 0x11000000
385 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
386 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x10000
387 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
390 #define CONFIG_SYS_CPLD_BASE 0xffb00000
392 #ifdef CONFIG_PHYS_64BIT
393 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
395 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
398 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
402 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
403 #define CONFIG_SYS_CSOR3 0x0
404 /* CPLD Timing parameters for IFC CS3 */
405 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
406 FTIM0_GPCM_TEADC(0x0e) | \
407 FTIM0_GPCM_TEAHC(0x0e))
408 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
409 FTIM1_GPCM_TRAD(0x1f))
410 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
411 FTIM2_GPCM_TCH(0x0) | \
412 FTIM2_GPCM_TWP(0x1f))
413 #define CONFIG_SYS_CS3_FTIM3 0x0
414 #endif /* CONFIG_SDCARD */
416 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
417 defined(CONFIG_RAMBOOT_NAND)
418 #define CONFIG_SYS_RAMBOOT
419 #define CONFIG_SYS_EXTRA_ENV_RELOC
421 #undef CONFIG_SYS_RAMBOOT
424 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
425 #define CONFIG_BOARD_EARLY_INIT_R
427 #define CONFIG_SYS_INIT_RAM_LOCK
428 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
429 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
431 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
432 - GENERATED_GBL_DATA_SIZE)
433 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
435 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
436 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
439 #define CONFIG_CONS_INDEX 1
440 #undef CONFIG_SERIAL_SOFTWARE_FIFO
441 #define CONFIG_SYS_NS16550
442 #define CONFIG_SYS_NS16550_SERIAL
443 #define CONFIG_SYS_NS16550_REG_SIZE 1
444 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
445 #ifdef CONFIG_NAND_SPL
446 #define CONFIG_NS16550_MIN_FUNCTIONS
449 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */
450 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
452 #define CONFIG_SYS_BAUDRATE_TABLE \
453 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
455 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
456 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
458 /* Use the HUSH parser */
459 #define CONFIG_SYS_HUSH_PARSER
460 #ifdef CONFIG_SYS_HUSH_PARSER
461 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
465 * Pass open firmware flat tree
467 #define CONFIG_OF_LIBFDT
468 #define CONFIG_OF_BOARD_SETUP
469 #define CONFIG_OF_STDOUT_VIA_ALIAS
471 /* new uImage format support */
473 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
475 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
476 #define CONFIG_HARD_I2C /* I2C with hardware support */
477 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
478 #define CONFIG_I2C_MULTI_BUS
479 #define CONFIG_I2C_CMD_TREE
480 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
481 #define CONFIG_SYS_I2C_SLAVE 0x7F
482 #define CONFIG_SYS_I2C_OFFSET 0x3000
483 #define CONFIG_SYS_I2C2_OFFSET 0x3100
486 #undef CONFIG_ID_EEPROM
487 /* enable read and write access to EEPROM */
488 #define CONFIG_CMD_EEPROM
489 #define CONFIG_SYS_I2C_MULTI_EEPROMS
490 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
491 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
492 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
495 #define CONFIG_RTC_PT7C4338
496 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
498 #define CONFIG_CMD_I2C
501 * SPI interface will not be available in case of NAND boot SPI CS0 will be
504 #ifndef CONFIG_NAND_U_BOOT
505 /* eSPI - Enhanced SPI */
506 #define CONFIG_FSL_ESPI
507 #define CONFIG_SPI_FLASH
508 #define CONFIG_SPI_FLASH_SPANSION
509 #define CONFIG_CMD_SF
510 #define CONFIG_SF_DEFAULT_SPEED 10000000
511 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
514 #if defined(CONFIG_TSEC_ENET)
515 #ifndef CONFIG_NET_MULTI
516 #define CONFIG_NET_MULTI
519 #define CONFIG_MII /* MII PHY management */
520 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
521 #define CONFIG_TSEC1 1
522 #define CONFIG_TSEC1_NAME "eTSEC1"
523 #define CONFIG_TSEC2 1
524 #define CONFIG_TSEC2_NAME "eTSEC2"
525 #define CONFIG_TSEC3 1
526 #define CONFIG_TSEC3_NAME "eTSEC3"
528 #define TSEC1_PHY_ADDR 1
529 #define TSEC2_PHY_ADDR 0
530 #define TSEC3_PHY_ADDR 2
532 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
533 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
534 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
536 #define TSEC1_PHYIDX 0
537 #define TSEC2_PHYIDX 0
538 #define TSEC3_PHYIDX 0
540 #define CONFIG_ETHPRIME "eTSEC1"
542 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
544 /* TBI PHY configuration for SGMII mode */
545 #define CONFIG_TSEC_TBICR_SETTINGS ( \
547 | TBICR_ANEG_ENABLE \
548 | TBICR_FULL_DUPLEX \
552 #endif /* CONFIG_TSEC_ENET */
556 #define CONFIG_FSL_SATA
557 #define CONFIG_LIBATA
559 #ifdef CONFIG_FSL_SATA
560 #define CONFIG_SYS_SATA_MAX_DEVICE 2
562 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
563 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
565 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
566 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
568 #define CONFIG_CMD_SATA
570 #endif /* #ifdef CONFIG_FSL_SATA */
572 /* SD interface will only be available in case of SD boot */
575 #define CONFIG_DEF_HWCONFIG esdhc
579 #define CONFIG_CMD_MMC
580 #define CONFIG_DOS_PARTITION
581 #define CONFIG_FSL_ESDHC
582 #define CONFIG_GENERIC_MMC
583 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
586 #define CONFIG_HAS_FSL_DR_USB
588 #if defined(CONFIG_HAS_FSL_DR_USB)
589 #define CONFIG_USB_EHCI
591 #ifdef CONFIG_USB_EHCI
592 #define CONFIG_CMD_USB
593 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
594 #define CONFIG_USB_EHCI_FSL
595 #define CONFIG_USB_STORAGE
602 #if defined(CONFIG_SYS_RAMBOOT)
603 #if defined(CONFIG_RAMBOOT_SDCARD)
604 #define CONFIG_ENV_IS_IN_MMC
605 #define CONFIG_SYS_MMC_ENV_DEV 0
606 #define CONFIG_ENV_SIZE 0x2000
607 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
608 #define CONFIG_ENV_IS_IN_SPI_FLASH
609 #define CONFIG_ENV_SPI_BUS 0
610 #define CONFIG_ENV_SPI_CS 0
611 #define CONFIG_ENV_SPI_MAX_HZ 10000000
612 #define CONFIG_ENV_SPI_MODE 0
613 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
614 #define CONFIG_ENV_SECT_SIZE 0x10000
615 #define CONFIG_ENV_SIZE 0x2000
616 #elif defined(CONFIG_NAND_U_BOOT)
617 #define CONFIG_ENV_IS_IN_NAND
618 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
619 #define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_U_BOOT_SIZE
620 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
622 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
623 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
624 #define CONFIG_ENV_SIZE 0x2000
627 #define CONFIG_ENV_IS_IN_FLASH
628 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
629 #define CONFIG_ENV_ADDR 0xfff80000
631 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
633 #define CONFIG_ENV_SIZE 0x2000
634 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
637 #define CONFIG_LOADS_ECHO /* echo on for serial download */
638 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
641 * Command line configuration.
643 #include <config_cmd_default.h>
645 #define CONFIG_CMD_DATE
646 #define CONFIG_CMD_ERRATA
647 #define CONFIG_CMD_ELF
648 #define CONFIG_CMD_IRQ
649 #define CONFIG_CMD_MII
650 #define CONFIG_CMD_PING
651 #define CONFIG_CMD_SETEXPR
652 #define CONFIG_CMD_REGINFO
654 #undef CONFIG_WATCHDOG /* watchdog disabled */
656 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
657 || defined(CONFIG_FSL_SATA)
658 #define CONFIG_CMD_EXT2
659 #define CONFIG_CMD_FAT
660 #define CONFIG_DOS_PARTITION
664 * Miscellaneous configurable options
666 #define CONFIG_SYS_LONGHELP /* undef to save memory */
667 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
668 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
669 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
670 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
672 #if defined(CONFIG_CMD_KGDB)
673 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
675 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
677 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
678 /* Print Buffer Size */
679 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
680 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
681 #define CONFIG_SYS_HZ 1000 /* dec freq: 1ms ticks */
684 * Internal Definitions
688 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
689 #define BOOTFLAG_WARM 0x02 /* Software reboot */
692 * For booting Linux, the board info and command line data
693 * have to be in the first 64 MB of memory, since this is
694 * the maximum mapped by the Linux kernel during initialization.
696 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
697 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
699 #if defined(CONFIG_CMD_KGDB)
700 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
701 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
705 * Environment Configuration
708 #if defined(CONFIG_TSEC_ENET)
709 #define CONFIG_HAS_ETH0
710 #define CONFIG_HAS_ETH1
711 #define CONFIG_HAS_ETH2
714 #define CONFIG_HOSTNAME P1010RDB
715 #define CONFIG_ROOTPATH /opt/nfsroot
716 #define CONFIG_BOOTFILE uImage
717 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
719 /* default location for tftp and bootm */
720 #define CONFIG_LOADADDR 1000000
722 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
723 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
725 #define CONFIG_BAUDRATE 115200
727 #define CONFIG_EXTRA_ENV_SETTINGS \
728 "hwconfig=" MK_STR(CONFIG_DEF_HWCONFIG) "\0" \
730 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
731 "loadaddr=1000000\0" \
732 "consoledev=ttyS0\0" \
733 "ramdiskaddr=2000000\0" \
734 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
736 "fdtfile=p1010rdb.dtb\0" \
738 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
739 "othbootargs=ramdisk_size=600000\0" \
740 "usbfatboot=setenv bootargs root=/dev/ram rw " \
741 "console=$consoledev,$baudrate $othbootargs; " \
743 "fatload usb 0:2 $loadaddr $bootfile;" \
744 "fatload usb 0:2 $fdtaddr $fdtfile;" \
745 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
746 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
747 "usbext2boot=setenv bootargs root=/dev/ram rw " \
748 "console=$consoledev,$baudrate $othbootargs; " \
750 "ext2load usb 0:4 $loadaddr $bootfile;" \
751 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
752 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
753 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
755 #define CONFIG_RAMBOOTCOMMAND \
756 "setenv bootargs root=/dev/ram rw " \
757 "console=$consoledev,$baudrate $othbootargs; " \
758 "tftp $ramdiskaddr $ramdiskfile;" \
759 "tftp $loadaddr $bootfile;" \
760 "tftp $fdtaddr $fdtfile;" \
761 "bootm $loadaddr $ramdiskaddr $fdtaddr"
763 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
765 #endif /* __CONFIG_H */