3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 #include <galileo/core.h>
35 #include "../board/evb64260/local.h"
38 * High Level Configuration Options
42 #define CONFIG_P3G4 1 /* this is a P3G4 board */
43 #define CFG_GT_6426x GT_64260 /* with a 64260 system controller */
45 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115200 */
47 #undef CONFIG_ECC /* enable ECC support */
48 /* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */
50 /* which initialization functions to call for this board */
51 #define CONFIG_MISC_INIT_R 1
52 #define CONFIG_BOARD_EARLY_INIT_F 1
54 #define CFG_BOARD_NAME "P3G4"
56 #undef CFG_HUSH_PARSER
57 #define CFG_PROMPT_HUSH_PS2 "> "
60 * The following defines let you select what serial you want to use
61 * for your console driver.
63 * to use the MPSC, #define CONFIG_MPSC. If you have wired up another
64 * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
67 #define CONFIG_MPSC_PORT 0
69 #define CONFIG_NET_MULTI /* attempt all available adapters */
71 /* define this if you want to enable GT MAC filtering */
72 #define CONFIG_GT_USE_MAC_HASH_TABLE
74 #undef CONFIG_ETHER_PORT_MII /* use RMII */
77 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
79 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
81 #define CONFIG_ZERO_BOOTDELAY_CHECK
83 #define CONFIG_PREBOOT "echo;" \
84 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
87 #undef CONFIG_BOOTARGS
89 #define CONFIG_EXTRA_ENV_SETTINGS \
92 "nfsargs=setenv bootargs root=/dev/nfs rw " \
93 "nfsroot=${serverip}:${rootpath}\0" \
94 "ramargs=setenv bootargs root=/dev/ram rw\0" \
95 "addip=setenv bootargs ${bootargs} " \
96 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
97 ":${hostname}:${netdev}:off panic=1\0" \
98 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
99 "flash_nfs=run nfsargs addip addtty;" \
100 "bootm ${kernel_addr}\0" \
101 "flash_self=run ramargs addip addtty;" \
102 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
103 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
105 "rootpath=/opt/eldk/ppc_74xx\0" \
106 "bootfile=/tftpboot/p3g4/uImage\0" \
107 "kernel_addr=ff000000\0" \
108 "ramdisk_addr=ff010000\0" \
109 "load=tftp 100000 /tftpboot/p3g4/u-boot.bin\0" \
110 "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \
111 "cp.b 100000 fff00000 ${filesize};" \
112 "setenv filesize;saveenv\0" \
113 "upd=run load;run update\0" \
115 #define CONFIG_BOOTCOMMAND "run flash_self"
117 #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
118 #define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
120 #undef CONFIG_WATCHDOG /* watchdog disabled */
121 #undef CONFIG_ALTIVEC /* undef to disable */
123 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
124 CONFIG_BOOTP_BOOTFILESIZE)
126 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
130 * Command line configuration.
132 #include <config_cmd_default.h>
134 #define CONFIG_CMD_ASKENV
135 #define CONFIG_CMD_DHCP
136 #define CONFIG_CMD_PCI
137 #define CONFIG_CMD_ELF
138 #define CONFIG_CMD_MII
139 #define CONFIG_CMD_PING
140 #define CONFIG_CMD_UNIVERSE
141 #define CONFIG_CMD_BSP
145 * Miscellaneous configurable options
147 #define CFG_LONGHELP /* undef to save memory */
148 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
149 #if defined(CONFIG_CMD_KGDB)
150 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
152 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
154 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
155 #define CFG_MAXARGS 16 /* max number of command args */
156 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
158 #define CFG_MEMTEST_START 0x00400000 /* memtest works on */
159 #define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
161 #define CFG_LOAD_ADDR 0x00300000 /* default load address */
163 #define CFG_HZ 1000 /* decr freq: 1ms ticks */
164 #define CFG_BUS_HZ 133000000 /* 133 MHz */
165 #define CFG_BUS_CLK CFG_BUS_HZ
167 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
171 * Low Level Configuration Settings
172 * (address mappings, register initial values, etc.)
173 * You should know what you are doing if you make changes here.
176 /*-----------------------------------------------------------------------
177 * Definitions for initial stack pointer and data area
179 #define CFG_INIT_RAM_ADDR 0x40000000
180 #define CFG_INIT_RAM_END 0x1000
181 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
182 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
183 #define CFG_INIT_RAM_LOCK
186 /*-----------------------------------------------------------------------
187 * Start addresses for the final memory configuration
188 * (Set up by the startup code)
189 * Please note that CFG_SDRAM_BASE _must_ start at 0
191 #define CFG_SDRAM_BASE 0x00000000
192 #define CFG_FLASH_BASE 0xff000000
193 #define CFG_RESET_ADDRESS 0xfff00100
194 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
195 #define CFG_MONITOR_BASE TEXT_BASE
196 #define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
198 /* areas to map different things with the GT in physical space */
199 #define CFG_DRAM_BANKS 1
200 #define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
202 /* What to put in the bats. */
203 #define CFG_MISC_REGION_BASE 0xf0000000
205 /* Peripheral Device section */
206 #define CFG_GT_REGS 0xf8000000
207 #define CFG_DEV_BASE 0xff000000
209 #define CFG_DEV0_SPACE CFG_DEV_BASE
210 #define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE)
211 #define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE)
212 #define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE)
214 #define CFG_DEV0_SIZE _8M /* Flash bank */
215 #define CFG_DEV1_SIZE 0 /* unused */
216 #define CFG_DEV2_SIZE 0 /* unused */
217 #define CFG_DEV3_SIZE 0 /* unused */
219 #define CFG_16BIT_BOOT_PAR 0xc01b5e7c
220 #define CFG_DEV0_PAR CFG_16BIT_BOOT_PAR
222 #if 0 /* Wrong?? NTL */
223 #define CFG_MPP_CONTROL_0 0x53541717 /* InitAct EOT[4] DBurst TCEn[1] */
224 /* DMAAck[1:0] GNT0[1:0] */
226 #define CFG_MPP_CONTROL_0 0x53547777 /* InitAct EOT[4] DBurst TCEn[1] */
227 /* REQ0[1:0] GNT0[1:0] */
229 #define CFG_MPP_CONTROL_1 0x44009911 /* TCEn[4] TCTcnt[4] GPP[13:12] */
230 /* DMAReq[4] DMAAck[4] WDNMI WDE */
231 #if 0 /* Wrong?? NTL */
232 #define CFG_MPP_CONTROL_2 0x40091818 /* TCTcnt[0] GPP[22:21] BClkIn */
233 /* DMAAck[1:0] GNT1[1:0] */
235 #define CFG_MPP_CONTROL_2 0x40098888 /* TCTcnt[0] */
236 /* GPP[22] (RS232IntB or PCI1Int) */
237 /* GPP[21] (RS323IntA) */
239 /* REQ1[1:0] GNT1[1:0] */
242 #if 0 /* Wrong?? NTL */
243 # define CFG_MPP_CONTROL_3 0x00090066 /* GPP[31:29] BClkOut0 */
244 /* GPP[27:26] Int[1:0] */
246 # define CFG_MPP_CONTROL_3 0x22090066 /* MREQ MGNT */
247 /* GPP[29] (PCI1Int) */
249 /* GPP[27] (PCI0Int) */
250 /* GPP[26] (RtcInt or PCI1Int) */
254 #define CFG_SERIAL_PORT_MUX 0x00001102 /* 11=MPSC1/MPSC0 02=ETH 0 and 2 RMII */
256 #if 0 /* Wrong?? - NTL */
257 # define CFG_GPP_LEVEL_CONTROL 0x000002c6
259 # define CFG_GPP_LEVEL_CONTROL 0x2c600000 /* 0010 1100 0110 0000 */
264 # define CFG_SDRAM_CONFIG 0xd8e18200 /* 0x448 */
265 /* idmas use buffer 1,1
269 normal load (see also ifdef HVL)
270 standard SDRAM (see also ifdef REG)
271 non staggered refresh */
272 /* 31:26 25 23 20 19 18 16 */
273 /* 110110 00 111 0 0 00 1 */
274 /* refresh_count=0x200
275 phisical interleaving disable
276 virtual interleaving enable */
282 #define CFG_DUART_IO CFG_DEV2_SPACE
283 #define CFG_DUART_CHAN 1 /* channel to use for console */
285 #undef CFG_INIT_CHAN1
286 #undef CFG_INIT_CHAN2
288 #define SRAM_BASE CFG_DEV0_SPACE
289 #define SRAM_SIZE 0x00100000 /* 1 MB of sram */
293 /*-----------------------------------------------------------------------
295 *-----------------------------------------------------------------------
298 #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
299 #define PCI_HOST_FORCE 1 /* configure as pci host */
300 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
302 #define CONFIG_PCI /* include pci support */
303 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
304 #define CONFIG_PCI_PNP /* do pci plug-and-play */
306 /* PCI MEMORY MAP section */
307 #define CFG_PCI0_MEM_BASE 0x80000000
308 #define CFG_PCI0_MEM_SIZE _128M
309 #define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE)
311 #define CFG_PCI1_MEM_BASE 0x88000000
312 #define CFG_PCI1_MEM_SIZE _128M
313 #define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE)
315 /* PCI I/O MAP section */
316 #define CFG_PCI0_IO_BASE 0xfa000000
317 #define CFG_PCI0_IO_SIZE _16M
318 #define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE)
319 #define CFG_PCI0_IO_SPACE_PCI 0x00000000
321 #define CFG_PCI1_IO_BASE 0xfb000000
322 #define CFG_PCI1_IO_SIZE _16M
323 #define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE)
324 #define CFG_PCI1_IO_SPACE_PCI 0x00000000
326 /*----------------------------------------------------------------------
327 * Initial BAT mappings
331 * 1) GUARDED and WRITE_THRU not allowed in IBATS
332 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
336 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
337 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
338 #define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
339 #define CFG_DBAT0U CFG_IBAT0U
342 #define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
343 #define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
344 #define CFG_DBAT1L CFG_IBAT1L
345 #define CFG_DBAT1U CFG_IBAT1U
347 /* PCI0, PCI1 in one BAT */
348 #define CFG_IBAT2L BATL_NO_ACCESS
349 #define CFG_IBAT2U CFG_DBAT2U
350 #define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
351 #define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
353 /* GT regs, bootrom, all the devices, PCI I/O */
354 #define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
355 #define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
356 #define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
357 #define CFG_DBAT3U CFG_IBAT3U
359 /* I2C speed and slave address (for compatability) defaults */
360 #define CFG_I2C_SPEED 400000
361 #define CFG_I2C_SLAVE 0x7F
363 /* I2C addresses for the two DIMM SPD chips */
364 #ifndef CONFIG_EVB64260_750CX
365 #define DIMM0_I2C_ADDR 0x56
366 #define DIMM1_I2C_ADDR 0x54
367 #else /* CONFIG_EVB64260_750CX - only has 1 DIMM */
368 #define DIMM0_I2C_ADDR 0x54
369 #define DIMM1_I2C_ADDR 0x54
373 * For booting Linux, the board info and command line data
374 * have to be in the first 8 MB of memory, since this is
375 * the maximum mapped by the Linux kernel during initialization.
377 #define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
379 /*-----------------------------------------------------------------------
382 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
383 #define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
385 #define CFG_EXTRA_FLASH_DEVICE BOOT_DEVICE
386 #define CFG_EXTRA_FLASH_WIDTH 2 /* 16 bit */
387 #define CFG_BOOT_FLASH_WIDTH 2 /* 16 bit */
389 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
390 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
391 #define CFG_FLASH_CFI 1
393 #define CFG_ENV_IS_IN_FLASH 1
394 #define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
395 #define CFG_ENV_SECT_SIZE 0x20000
396 #define CFG_ENV_ADDR 0xFFFE0000
398 /*-----------------------------------------------------------------------
399 * Cache Configuration
401 #define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
402 #if defined(CONFIG_CMD_KGDB)
403 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
406 /*-----------------------------------------------------------------------
407 * L2CR setup -- make sure this is right for your board!
408 * look in include/74xx_7xx.h for the defines used here
413 #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
414 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
416 #define L2_ENABLE (L2_INIT | L2CR_L2E)
419 * Internal Definitions
423 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
424 #define BOOTFLAG_WARM 0x02 /* Software reboot */
426 #define CFG_BOARD_ASM_INIT 1
429 #endif /* __CONFIG_H */