3 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
8 /* ------------------------------------------------------------------------- */
11 * board/config.h - configuration options, board specific
18 * High Level Configuration Options
22 #define CONFIG_MPC824X 1
23 #define CONFIG_MPC8240 1
26 #define CONFIG_SYS_TEXT_BASE 0xFFF00000
28 #define CONFIG_CONS_INDEX 1
34 #define CONFIG_BOOTP_BOOTFILESIZE
35 #define CONFIG_BOOTP_BOOTPATH
36 #define CONFIG_BOOTP_GATEWAY
37 #define CONFIG_BOOTP_HOSTNAME
41 * Command line configuration.
43 #include <config_cmd_default.h>
45 #define CONFIG_CMD_PCI
46 #define CONFIG_CMD_BSP
48 #undef CONFIG_CMD_FLASH
49 #undef CONFIG_CMD_IMLS
50 #undef CONFIG_CMD_LOADS
51 #undef CONFIG_CMD_SAVEENV
52 #undef CONFIG_CMD_SOURCE
55 #define CONFIG_BAUDRATE 19200 /* console baudrate */
57 #define CONFIG_BOOTDELAY 1 /* autoboot after n seconds */
59 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
61 #define CONFIG_SERVERIP 10.0.0.201
62 #define CONFIG_IPADDR 10.0.0.200
63 #define CONFIG_ROOTPATH "/opt/eldk/ppc_82xx"
64 #define CONFIG_NETMASK 255.255.255.0
65 #undef CONFIG_BOOTARGS
67 /* Boot Linux with NFS root filesystem */
68 #define CONFIG_BOOTCOMMAND \
70 "setenv bootargs console=ttyS0,19200 mem=31M quiet " \
71 "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
72 "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \
74 /* "tftpboot 100000 uImage; bootm" */
76 /* Boot Linux with RAMdisk based filesystem (initrd, BusyBox) */
77 #define CONFIG_BOOTCOMMAND \
79 "setenv bootargs console=ttyS0,19200 mem=31M quiet " \
81 "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \
86 * Miscellaneous configurable options
88 #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
89 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
90 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
91 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
92 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
93 #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
94 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
96 #define CONFIG_PRAM 1024 /* reserve 1 MB protected RAM */
98 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */
100 #define CONFIG_HAS_ETH1 1 /* add support for eth1addr */
102 #define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
107 #define CONFIG_PCI /* include pci support */
108 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
109 #define CONFIG_PCI_PNP /* we need Plug 'n Play */
111 #define CONFIG_PCI_SCAN_SHOW /* show PCI auto-scan at boot */
118 #define CONFIG_PCNET /* there are 2 AMD PCnet 79C973 */
119 #define CONFIG_PCNET_79C973
121 #define _IO_BASE 0xfe000000 /* points to PCI I/O space */
125 * Start addresses for the final memory configuration
126 * (Set up by the startup code)
127 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
129 #define CONFIG_SYS_SDRAM_BASE 0x00000000
130 #define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
132 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100
134 #undef CONFIG_SYS_RAMBOOT
135 #define CONFIG_SYS_MONITOR_LEN 0x00030000
136 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
139 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
140 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
141 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
144 #define CONFIG_SYS_NO_FLASH 1 /* There is no FLASH memory */
146 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
147 #define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */
148 #define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
150 #define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
152 #define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
153 #define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 0 ... 32 MB in DRAM */
156 * Serial port configuration
159 #define CONFIG_SYS_NS16550
160 #define CONFIG_SYS_NS16550_SERIAL
162 #define CONFIG_SYS_NS16550_REG_SIZE 1
164 #define CONFIG_SYS_NS16550_CLK 1843200
166 #define CONFIG_SYS_NS16550_COM1 0xff800008
167 #define CONFIG_SYS_NS16550_COM2 0xff800000
170 * Low Level Configuration Settings
171 * (address mappings, register initial values, etc.)
172 * You should know what you are doing if you make changes here.
175 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
176 #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3
178 #define CONFIG_SYS_EUMB_ADDR 0xFCE00000
181 #define CONFIG_SYS_ROMNAL 3 /* rom/flash next access time */
182 #define CONFIG_SYS_ROMFAL 7 /* rom/flash access time */
185 #define CONFIG_SYS_ASRISE 6 /* ASRISE in clocks */
186 #define CONFIG_SYS_ASFALL 12 /* ASFALL in clocks */
187 #define CONFIG_SYS_REFINT 5600 /* REFINT in clocks */
190 #define CONFIG_SYS_BSTOPRE 0x3cf /* Burst To Precharge */
191 #define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */
192 #define CONFIG_SYS_RDLAT 3 /* data latency from read command */
195 #define CONFIG_SYS_PRETOACT 1 /* Precharge to activate interval */
196 #define CONFIG_SYS_ACTTOPRE 3 /* Activate to Precharge interval */
197 #define CONFIG_SYS_ACTORW 2 /* Activate to R/W */
198 #define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latency */
199 #define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE Wrap type */
200 #define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */
201 #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
203 /* Memory bank settings:
205 * only bits 20-29 are actually used from these vales to set the
206 * start/qend address the upper two bits will be 0, and the lower 20
207 * bits will be set to 0x00000 for a start address, or 0xfffff for an
210 #define CONFIG_SYS_BANK0_START 0x00000000
211 #define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
212 #define CONFIG_SYS_BANK0_ENABLE 1
213 #define CONFIG_SYS_BANK1_START 0x00000000
214 #define CONFIG_SYS_BANK1_END 0x00000000
215 #define CONFIG_SYS_BANK1_ENABLE 0
216 #define CONFIG_SYS_BANK2_START 0x00000000
217 #define CONFIG_SYS_BANK2_END 0x00000000
218 #define CONFIG_SYS_BANK2_ENABLE 0
219 #define CONFIG_SYS_BANK3_START 0x00000000
220 #define CONFIG_SYS_BANK3_END 0x00000000
221 #define CONFIG_SYS_BANK3_ENABLE 0
222 #define CONFIG_SYS_BANK4_START 0x00000000
223 #define CONFIG_SYS_BANK4_END 0x00000000
224 #define CONFIG_SYS_BANK4_ENABLE 0
225 #define CONFIG_SYS_BANK5_START 0x00000000
226 #define CONFIG_SYS_BANK5_END 0x00000000
227 #define CONFIG_SYS_BANK5_ENABLE 0
228 #define CONFIG_SYS_BANK6_START 0x00000000
229 #define CONFIG_SYS_BANK6_END 0x00000000
230 #define CONFIG_SYS_BANK6_ENABLE 0
231 #define CONFIG_SYS_BANK7_START 0x00000000
232 #define CONFIG_SYS_BANK7_END 0x00000000
233 #define CONFIG_SYS_BANK7_ENABLE 0
236 * Memory bank enable bitmask, specifying which of the banks defined above
237 * are actually present. MSB is for bank #7, LSB is for bank #0.
239 #define CONFIG_SYS_BANK_ENABLE 0x01
241 #define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */
242 /* see 8240 book for bit definitions */
243 #define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
244 /* currently accessed page in memory */
245 /* see 8240 book for details */
247 /* SDRAM 0 - 256MB */
248 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
249 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
251 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
252 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
254 /* PCI memory space */
255 #define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
256 #define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
258 /* Config addrs, etc */
259 #define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
260 #define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
262 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
263 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
264 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
265 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
266 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
267 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
268 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
269 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
272 * For booting Linux, the board info and command line data
273 * have to be in the first 8 MB of memory, since this is
274 * the maximum mapped by the Linux kernel during initialization.
276 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
279 * Cache Configuration
281 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */
282 #if defined(CONFIG_CMD_KGDB)
283 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
286 #endif /* __CONFIG_H */