3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * board/config.h - configuration options, board specific
16 * High Level Configuration Options
20 #define CONFIG_MPC823 1 /* This is a MPC823 CPU */
21 #define CONFIG_SPD823TS 1 /* ...on a SPD823TS board */
23 #define CONFIG_SYS_TEXT_BASE 0xFF000000
25 #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
27 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
28 #undef CONFIG_8xx_CONS_SMC2
29 #undef CONFIG_8xx_CONS_NONE
30 #define CONFIG_BAUDRATE 115200
32 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
34 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
37 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
39 #define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
41 #define CONFIG_BOOTARGS "root=/dev/nfs rw " \
42 "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
43 "nfsaddrs=10.0.0.99:10.0.0.2"
45 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
46 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
48 #undef CONFIG_WATCHDOG /* watchdog disabled */
52 * Command line configuration.
54 #include <config_cmd_default.h>
56 #define CONFIG_CMD_IDE
58 #undef CONFIG_CMD_SAVEENV
59 #undef CONFIG_CMD_FLASH
62 #define CONFIG_MAC_PARTITION
63 #define CONFIG_DOS_PARTITION
68 #define CONFIG_BOOTP_SUBNETMASK
69 #define CONFIG_BOOTP_GATEWAY
70 #define CONFIG_BOOTP_HOSTNAME
71 #define CONFIG_BOOTP_BOOTPATH
72 #define CONFIG_BOOTP_BOOTFILESIZE
75 /*----------------------------------------------------------------------*/
76 #define CONFIG_ETHADDR 00:D0:93:00:01:CB
77 #define CONFIG_IPADDR 10.0.0.98
78 #define CONFIG_SERVERIP 10.0.0.1
79 #undef CONFIG_BOOTCOMMAND
80 #define CONFIG_BOOTCOMMAND "tftp 200000 uImage;bootm 200000"
81 /*----------------------------------------------------------------------*/
84 * Miscellaneous configurable options
86 #define CONFIG_SYS_LONGHELP /* undef to save memory */
87 #if defined(CONFIG_CMD_KGDB)
88 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
90 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
92 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
93 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
94 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
96 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
97 #define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
99 #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
101 #define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
103 #define CONFIG_SYS_PC_IDE_RESET ((ushort)0x0008) /* PC 12 */
105 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
108 * Low Level Configuration Settings
109 * (address mappings, register initial values, etc.)
110 * You should know what you are doing if you make changes here.
112 /*-----------------------------------------------------------------------
113 * Internal Memory Mapped Register
115 #define CONFIG_SYS_IMMR 0xFFF00000 /* was: 0xFF000000 */
117 /*-----------------------------------------------------------------------
118 * Definitions for initial stack pointer and data area (in DPRAM)
120 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
121 #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
122 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
123 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
125 /*-----------------------------------------------------------------------
126 * Start addresses for the final memory configuration
127 * (Set up by the startup code)
128 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
130 #define CONFIG_SYS_SDRAM_BASE 0x00000000
131 #define CONFIG_SYS_FLASH_BASE 0xFF000000
133 #define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
135 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
137 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
138 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
141 * For booting Linux, the board info and command line data
142 * have to be in the first 8 MB of memory, since this is
143 * the maximum mapped by the Linux kernel during initialization.
145 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
146 /*-----------------------------------------------------------------------
149 #define CONFIG_SYS_MAX_FLASH_BANKS 0 /* max number of memory banks */
150 #define CONFIG_SYS_MAX_FLASH_SECT 0 /* max number of sectors on one chip */
152 #define CONFIG_SYS_FLASH_ERASE_TOUT 0 /* Timeout for Flash Erase (in ms) */
153 #define CONFIG_SYS_FLASH_WRITE_TOUT 0 /* Timeout for Flash Write (in ms) */
155 #define CONFIG_ENV_IS_IN_FLASH 1
156 #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
157 #define CONFIG_ENV_SIZE 0x0800 /* Total Size of Environment Sector */
158 /*-----------------------------------------------------------------------
159 * Cache Configuration
161 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
162 #if defined(CONFIG_CMD_KGDB)
163 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
166 /*-----------------------------------------------------------------------
167 * SYPCR - System Protection Control 11-9
168 * SYPCR can only be written once after reset!
169 *-----------------------------------------------------------------------
170 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
172 #if defined(CONFIG_WATCHDOG)
173 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
174 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
176 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
179 /*-----------------------------------------------------------------------
180 * SIUMCR - SIU Module Configuration 11-6
181 *-----------------------------------------------------------------------
182 * PCMCIA config., multi-function pin tri-state
185 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_GB5E)
187 /*-----------------------------------------------------------------------
188 * TBSCR - Time Base Status and Control 11-26
189 *-----------------------------------------------------------------------
190 * Clear Reference Interrupt Status, Timebase freezing enabled
192 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
194 /*-----------------------------------------------------------------------
195 * PISCR - Periodic Interrupt Status and Control 11-31
196 *-----------------------------------------------------------------------
197 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
199 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
201 /*-----------------------------------------------------------------------
202 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
203 *-----------------------------------------------------------------------
204 * Reset PLL lock status sticky bit, timer expired status bit and timer
205 * interrupt status bit, set PLL multiplication factor !
208 #define CONFIG_SYS_PLPRCR \
209 ( (11 << PLPRCR_MF_SHIFT) | \
210 PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \
211 /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
212 PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
215 /*-----------------------------------------------------------------------
216 * SCCR - System Clock and reset Control Register 15-27
217 *-----------------------------------------------------------------------
218 * Set clock output, timebase and RTC source and divider,
219 * power management and some other internal clocks
221 #define SCCR_MASK SCCR_EBDF11
223 #define CONFIG_SYS_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \
224 SCCR_RTDIV | SCCR_RTSEL | \
225 /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
226 SCCR_EBDF00 | SCCR_DFSYNC00 | \
227 SCCR_DFBRG00 | SCCR_DFNL000 | \
228 SCCR_DFNH000 | SCCR_DFLCD101 | \
231 /*-----------------------------------------------------------------------
232 * RTCSC - Real-Time Clock Status and Control Register
233 *-----------------------------------------------------------------------
236 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
239 /*-----------------------------------------------------------------------
240 * RCCR - RISC Controller Configuration Register
241 *-----------------------------------------------------------------------
244 #define CONFIG_SYS_RCCR 0x0200
246 /*-----------------------------------------------------------------------
247 * RMDS - RISC Microcode Development Support Control Register
248 *-----------------------------------------------------------------------
250 #define CONFIG_SYS_RMDS 0
252 /*-----------------------------------------------------------------------
253 * SDSR - SDMA Status Register
254 *-----------------------------------------------------------------------
256 #define CONFIG_SYS_SDSR ((u_char)0x83)
258 /*-----------------------------------------------------------------------
259 * SDMR - SDMA Mask Register
260 *-----------------------------------------------------------------------
262 #define CONFIG_SYS_SDMR ((u_char)0x00)
264 /*-----------------------------------------------------------------------
267 *-----------------------------------------------------------------------
269 #define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
271 /*-----------------------------------------------------------------------
273 *-----------------------------------------------------------------------
276 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
277 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
278 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
279 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
280 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
281 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
282 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
283 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
285 /*-----------------------------------------------------------------------
287 *-----------------------------------------------------------------------
289 #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
290 #define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */
291 #define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */
292 #define CONFIG_IDE_LED 1 /* LED for ide supported */
293 #define CONFIG_IDE_RESET 1 /* reset for ide supported */
295 #define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
296 #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
298 #define CONFIG_SYS_ATA_BASE_ADDR 0xFE100000
299 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
300 #define CONFIG_SYS_ATA_IDE1_OFFSET 0x0C00
302 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
303 #define CONFIG_SYS_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */
304 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */
306 /*-----------------------------------------------------------------------
308 *-----------------------------------------------------------------------
311 #define CONFIG_SYS_DER 0
314 * Init Memory Controller:
316 * BR0/1 and OR0/1 (FLASH)
319 #define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */
320 #define FLASH_BASE1_PRELIM 0xFF080000 /* FLASH bank #1 */
322 /* used to re-map FLASH both when starting from SRAM or FLASH:
323 * restrict access enough to keep SRAM working (if any)
324 * but not too much to meddle with FLASH accesses
326 /* EPROMs are 512kb */
327 #define CONFIG_SYS_REMAP_OR_AM 0xFFF80000 /* OR addr mask */
328 #define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */
330 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
331 #define CONFIG_SYS_OR_TIMING_FLASH (/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \
332 OR_SCY_5_CLK | OR_EHTR)
334 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
335 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
336 /* 16 bit, bank valid */
337 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
339 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
340 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
341 /* 16 bit, bank valid */
342 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
345 * BR2-5 and OR2-5 (SRAM/SDRAM/PER8/SHARC)
348 #define SRAM_BASE 0xFE200000 /* SRAM bank */
349 #define SRAM_OR_AM 0xFFE00000 /* SRAM is 2 MB */
351 #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
352 #define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
353 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
355 #define PER8_BASE 0xFE000000 /* PER8 bank */
356 #define PER8_OR_AM 0xFFF00000 /* PER8 is 1 MB */
358 #define SHARC_BASE 0xFE400000 /* SHARC bank */
359 #define SHARC_OR_AM 0xFFC00000 /* SHARC is 4 MB */
361 /* SRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
363 #define CONFIG_SYS_OR_TIMING_SRAM 0x00000D42 /* SRAM-Timing */
364 #define CONFIG_SYS_OR2 (SRAM_OR_AM | CONFIG_SYS_OR_TIMING_SRAM )
365 #define CONFIG_SYS_BR2 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V )
367 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
369 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 /* SDRAM-Timing */
370 #define CONFIG_SYS_OR3_PRELIM (SDRAM_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
371 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
373 #define CONFIG_SYS_OR_TIMING_PER8 0x00000F32 /* PER8-Timing */
374 #define CONFIG_SYS_OR4 (PER8_OR_AM | CONFIG_SYS_OR_TIMING_PER8 )
375 #define CONFIG_SYS_BR4 ((PER8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
377 #define CONFIG_SYS_OR_TIMING_SHARC 0x00000700 /* SHARC-Timing */
378 #define CONFIG_SYS_OR5 (SHARC_OR_AM | CONFIG_SYS_OR_TIMING_SHARC )
379 #define CONFIG_SYS_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
381 * Memory Periodic Timer Prescaler
384 /* periodic timer for refresh */
385 #define CONFIG_SYS_MBMR_PTB 204
387 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
388 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
389 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
391 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
392 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
393 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
396 * MBMR settings for SDRAM
400 #define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
401 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \
402 MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
404 #endif /* __CONFIG_H */