2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * T4240 EMU board configuration file
13 #define CONFIG_T4240EMU
14 #define CONFIG_PHYS_64BIT
16 #define CONFIG_SYS_NO_FLASH 1
17 #define CONFIG_SYS_FSL_DDR_EMU 1
18 #define CONFIG_SYS_FSL_NO_QIXIS 1
19 #define CONFIG_SYS_FSL_NO_SERDES 1
23 #define CONFIG_CMD_CACHE
24 #define CONFIG_CMD_CACHE_FLUSH
26 #define CONFIG_ENV_IS_NOWHERE
27 #define CONFIG_ENV_SIZE 0x2000
29 #define CONFIG_SYS_CLK_FREQ 100000000
30 #define CONFIG_DDR_CLK_FREQ 133333333
31 #define CONFIG_FSL_TBCLK_EXTRA_DIV 100
37 #define CONFIG_SYS_SPD_BUS_NUM 1
38 #define SPD_EEPROM_ADDRESS1 0x51
39 #define SPD_EEPROM_ADDRESS2 0x52
40 #define SPD_EEPROM_ADDRESS3 0x53
41 #define SPD_EEPROM_ADDRESS4 0x54
42 #define SPD_EEPROM_ADDRESS5 0x55
43 #define SPD_EEPROM_ADDRESS6 0x56
44 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
45 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
50 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
51 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
52 /* NOR Flash Timing Params */
53 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
58 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(0)
59 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
60 FTIM0_NOR_TEADC(0x1) | \
62 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
63 FTIM1_NOR_TRAD_NOR(0x1))
64 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
65 FTIM2_NOR_TCH(0x0) | \
67 #define CONFIG_SYS_NOR_FTIM3 0x04000000
68 #define CONFIG_SYS_IFC_CCR 0x01000000
70 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
71 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
72 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
73 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
74 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
75 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
76 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
77 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
81 #define CONFIG_SYS_FSL_I2C_SPEED 4000000 /* faster speed for emulator */
82 #define CONFIG_SYS_FSL_I2C2_SPEED 4000000
85 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
86 #define CONFIG_SYS_BMAN_NUM_PORTALS 50
87 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
88 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
89 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
90 #define CONFIG_SYS_QMAN_NUM_PORTALS 50
91 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
92 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
93 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
95 #define CONFIG_SYS_DPAA_FMAN
96 #define CONFIG_SYS_DPAA_PME
97 #define CONFIG_SYS_PMAN
98 #define CONFIG_SYS_DPAA_DCE
99 #define CONFIG_SYS_DPAA_RMAN
100 #define CONFIG_SYS_INTERLAKEN
102 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
103 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
104 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
105 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
109 #define CONFIG_BOOTDELAY 0
112 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
113 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
114 * interleaving. It can be cacheline, page, bank, superbank.
115 * See doc/README.fsl-ddr for details.
117 #ifdef CONFIG_PPC_T4240
118 #define CTRL_INTLV_PREFERED 3way_4KB
120 #define CTRL_INTLV_PREFERED cacheline
123 #define CONFIG_EXTRA_ENV_SETTINGS \
124 "hwconfig=fsl_ddr:" \
125 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
128 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
129 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
130 "consoledev=ttyS0\0" \
131 "ramdiskaddr=2000000\0" \
132 "ramdiskfile=t4240emu/ramdisk.uboot\0" \
134 "fdtfile=t4240emu/t4240emu.dtb\0" \
139 * For emulation this causes u-boot to jump to the start of the proof point
140 * app code automatically
142 #define CONFIG_PROOF_POINTS \
143 "setenv bootargs root=/dev/$bdev rw " \
144 "console=$consoledev,$baudrate $othbootargs;" \
145 "cpu 1 release 0x29000000 - - -;" \
146 "cpu 2 release 0x29000000 - - -;" \
147 "cpu 3 release 0x29000000 - - -;" \
148 "cpu 4 release 0x29000000 - - -;" \
149 "cpu 5 release 0x29000000 - - -;" \
150 "cpu 6 release 0x29000000 - - -;" \
151 "cpu 7 release 0x29000000 - - -;" \
154 #define CONFIG_HVBOOT \
155 "setenv bootargs config-addr=0x60000000; " \
156 "bootm 0x01000000 - 0x00f00000"
158 #define CONFIG_LINUX \
160 "setenv othbootargs ignore_loglevel;" \
161 "setenv bootargs root=/dev/ram rw " \
162 "console=$consoledev,$baudrate $othbootargs;" \
163 "setenv ramdiskaddr 0x02000000;" \
164 "setenv fdtaddr 0x00c00000;" \
165 "setenv loadaddr 0x1000000;" \
166 "bootm $loadaddr $ramdiskaddr $fdtaddr"
168 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
170 #endif /* __CONFIG_H */