2 * Sysam AMCORE board configuration
4 * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it>
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef __AMCORE_CONFIG_H
10 #define __AMCORE_CONFIG_H
13 #define CONFIG_HOSTNAME AMCORE
15 #define CONFIG_MCF530x
19 #define CONFIG_MCFUART
20 #define CONFIG_SYS_UART_PORT 0
21 #define CONFIG_BAUDRATE 115200
22 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
24 #define CONFIG_BOOTDELAY 1
25 #define CONFIG_BOOTCOMMAND "bootm ffc20000"
28 #define CONFIG_CMD_CACHE
29 #define CONFIG_CMD_TIMER
30 #define CONFIG_CMD_DIAG
32 /* undef to save memory */
33 #undef CONFIG_SYS_LONGHELP
35 #if defined(CONFIG_CMD_KGDB)
36 /* Console I/O buff. size */
37 #define CONFIG_SYS_CBSIZE 1024
39 #define CONFIG_SYS_CBSIZE 256
41 /* Print buffer size */
42 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
43 sizeof(CONFIG_SYS_PROMPT)+16)
44 /* max number of command args */
45 #define CONFIG_SYS_MAXARGS 16
46 /* Boot argument buffer size */
47 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
49 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* no console @ startup */
50 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
51 #define CONFIG_LOOPW 1 /* enable loopw command */
52 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
54 #define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */
56 #define CONFIG_SYS_MEMTEST_START 0x0
57 #define CONFIG_SYS_MEMTEST_END 0x1000000
59 #define CONFIG_SYS_HZ 1000
61 #define CONFIG_SYS_CLK 45000000
62 #define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2)
63 /* Register Base Addrs */
64 #define CONFIG_SYS_MBAR 0x10000000
65 /* Definitions for initial stack pointer and data area (in DPRAM) */
66 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
67 /* size of internal SRAM */
68 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
69 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
70 GENERATED_GBL_DATA_SIZE)
71 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
73 #define CONFIG_SYS_SDRAM_BASE 0x00000000
74 #define CONFIG_SYS_SDRAM_SIZE 0x1000000
75 #define CONFIG_SYS_FLASH_BASE 0xffc00000
76 #define CONFIG_SYS_MAX_FLASH_BANKS 1
77 #define CONFIG_SYS_MAX_FLASH_SECT 1024
78 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000
80 #define CONFIG_SYS_FLASH_CFI
81 #define CONFIG_FLASH_CFI_DRIVER
82 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
83 /* amcore design has flash data bytes wired swapped */
84 #define CONFIG_SYS_WRITE_SWAPPED_DATA
86 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
87 #define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024)
88 #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
89 #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
91 #define CONFIG_ENV_IS_IN_FLASH 1
92 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
93 CONFIG_SYS_MONITOR_LEN)
94 #define CONFIG_ENV_SIZE 0x1000
95 #define CONFIG_ENV_SECT_SIZE 0x1000
97 #define LDS_BOARD_TEXT \
98 . = DEFINED(env_offset) ? env_offset : .; \
99 common/env_embedded.o (.text*);
101 /* memory map space for linux boot data */
102 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
105 * Cache Configuration
107 * Special 8K version 3 core cache.
108 * This is a single unified instruction/data cache.
109 * sdram - single region - no masks
111 #define CONFIG_SYS_CACHELINE_SIZE 16
113 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
114 CONFIG_SYS_INIT_RAM_SIZE - 8)
115 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
116 CONFIG_SYS_INIT_RAM_SIZE - 4)
117 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
118 #define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \
120 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \
123 /* CS0 - AMD Flash, address 0xffc00000 */
124 #define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16)
125 /* 4MB, AA=0,V=1 C/I BIT for errata */
126 #define CONFIG_SYS_CS0_MASK 0x003f0001
127 /* WS=10, AA=1, PS=16bit (10) */
128 #define CONFIG_SYS_CS0_CTRL 0x1980
129 /* CS1 - DM9000 Ethernet Controller, address 0x30000000 */
130 #define CONFIG_SYS_CS1_BASE 0x3000
131 #define CONFIG_SYS_CS1_MASK 0x00070001
132 #define CONFIG_SYS_CS1_CTRL 0x0100
134 #endif /* __AMCORE_CONFIG_H */