1 /********************************************************************
3 * Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms
5 * $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/include/configs/barco.h,v $
8 * $Date: 2005/02/21 12:48:58 $
10 * Last ChangeLog Entry
12 * Revision 1.2 2005/02/21 12:48:58 mleeman
13 * update of copyright years (feedback wd)
15 * Revision 1.1 2005/02/14 09:29:25 mleeman
16 * moved barcohydra.h to barco.h
18 * Revision 1.4 2005/02/09 12:56:23 mleeman
19 * add generic header to track changes in sources
22 *******************************************************************/
25 * (C) Copyright 2001, 2002
26 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
28 * See file CREDITS for list of people who contributed to this
31 * This program is free software; you can redistribute it and/or
32 * modify it under the terms of the GNU General Public License as
33 * published by the Free Software Foundation; either version 2 of
34 * the License, or (at your option) any later version.
36 * This program is distributed in the hope that it will be useful,
37 * but WITHOUT ANY WARRANTY; without even the implied warranty of
38 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
39 * GNU General Public License for more details.
41 * You should have received a copy of the GNU General Public License
42 * along with this program; if not, write to the Free Software
43 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
47 /* ------------------------------------------------------------------------- */
50 * board/config.h - configuration options, board specific
57 * High Level Configuration Options
61 #define CONFIG_MPC824X 1
62 #define CONFIG_MPC8245 1
63 #define CONFIG_BARCOBCD_STREAMING 1
67 #define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */
68 #define CONFIG_BAUDRATE 9600
69 #define CONFIG_DRAM_SPEED 100 /* MHz */
71 #define CONFIG_BOOTARGS "mem=32M"
77 #define CONFIG_BOOTP_SUBNETMASK
78 #define CONFIG_BOOTP_GATEWAY
79 #define CONFIG_BOOTP_HOSTNAME
80 #define CONFIG_BOOTP_BOOTPATH
81 #define CONFIG_BOOTP_BOOTFILESIZE
82 #define CONFIG_BOOTP_DNS
86 * Command line configuration.
88 #include <config_cmd_default.h>
90 #define CONFIG_CMD_ELF
91 #define CONFIG_CMD_I2C
92 #define CONFIG_CMD_EEPROM
93 #define CONFIG_CMD_PCI
96 #define CONFIG_HUSH_PARSER 1 /* use "hush" command parser */
97 #define CONFIG_BOOTDELAY 1
98 #define CONFIG_BOOTCOMMAND "boot_default"
101 * Miscellaneous configurable options
103 #define CFG_LONGHELP 1 /* undef to save memory */
104 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
105 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
106 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
107 #define CFG_MAXARGS 16 /* max number of command args */
108 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
109 #define CFG_LOAD_ADDR 0x00100000 /* default load address */
110 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
113 /*-----------------------------------------------------------------------
115 *-----------------------------------------------------------------------
117 #define CONFIG_PCI /* include pci support */
118 #undef CONFIG_PCI_PNP
121 #define PCI_ENET0_IOADDR 0x80000000
122 #define PCI_ENET0_MEMADDR 0x80000000
123 #define PCI_ENET1_IOADDR 0x81000000
124 #define PCI_ENET1_MEMADDR 0x81000000
127 /*-----------------------------------------------------------------------
128 * Start addresses for the final memory configuration
129 * (Set up by the startup code)
130 * Please note that CFG_SDRAM_BASE _must_ start at 0
132 #define CFG_SDRAM_BASE 0x00000000
133 #define CFG_MAX_RAM_SIZE 0x02000000
135 #define CONFIG_LOGBUFFER
136 #ifdef CONFIG_LOGBUFFER
137 #define CFG_STDOUT_ADDR 0x1FFC000
139 #define CFG_STDOUT_ADDR 0x2B9000
142 #define CFG_RESET_ADDRESS 0xFFF00100
144 #if defined (USE_DINK32)
145 #define CFG_MONITOR_LEN 0x00030000
146 #define CFG_MONITOR_BASE 0x00090000
147 #define CFG_RAMBOOT 1
148 #define CFG_INIT_RAM_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
149 #define CFG_INIT_RAM_END 0x10000
150 #define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
151 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
152 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
155 #define CFG_MONITOR_LEN 0x00030000
156 #define CFG_MONITOR_BASE TEXT_BASE
158 #define CFG_GBL_DATA_SIZE 128
160 #define CFG_INIT_RAM_ADDR 0x40000000
161 #define CFG_INIT_RAM_END 0x1000
162 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
166 #define CFG_FLASH_BASE 0xFFF00000
167 #define CFG_FLASH_SIZE (8 * 1024 * 1024) /* Unity has onboard 1MByte flash */
168 #define CFG_ENV_IS_IN_FLASH 1
169 #define CFG_ENV_OFFSET 0x000047A4 /* Offset of Environment Sector */
170 #define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
171 /* #define ENV_CRC 0x8BF6F24B XXX - FIXME: gets defined automatically */
173 #define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
175 #define CFG_MEMTEST_START 0x00000000 /* memtest works on */
176 #define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
178 #define CFG_EUMB_ADDR 0xFDF00000
180 #define CFG_FLASH_RANGE_BASE 0xFFC00000 /* flash memory address range */
181 #define CFG_FLASH_RANGE_SIZE 0x00400000
182 #define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */
183 #define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */
186 * select i2c support configuration
188 * Supported configurations are {none, software, hardware} drivers.
189 * If the software driver is chosen, there are some additional
190 * configuration items that the driver uses to drive the port pins.
192 #define CONFIG_HARD_I2C 1 /* To enable I2C support */
193 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
194 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
195 #define CFG_I2C_SLAVE 0x7F
197 #ifdef CONFIG_SOFT_I2C
198 #error "Soft I2C is not configured properly. Please review!"
199 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
200 #define I2C_ACTIVE (iop->pdir |= 0x00010000)
201 #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
202 #define I2C_READ ((iop->pdat & 0x00010000) != 0)
203 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
204 else iop->pdat &= ~0x00010000
205 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
206 else iop->pdat &= ~0x00020000
207 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
208 #endif /* CONFIG_SOFT_I2C */
210 #define CFG_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
211 #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
212 #define CFG_EEPROM_PAGE_WRITE_BITS 3
213 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
215 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
216 #define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
217 #define CFG_DBUS_SIZE2 1
219 /*-----------------------------------------------------------------------
220 * Definitions for initial stack pointer and data area (in DPRAM)
225 * NS16550 Configuration (internal DUART)
228 * Low Level Configuration Settings
229 * (address mappings, register initial values, etc.)
230 * You should know what you are doing if you make changes here.
233 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
235 #define CFG_ROMNAL 0x0F /*rom/flash next access time */
236 #define CFG_ROMFAL 0x1E /*rom/flash access time */
238 #define CFG_REFINT 0x8F /* no of clock cycles between CBR refresh cycles */
240 /* the following are for SDRAM only*/
241 #define CFG_BSTOPRE 0x25C /* Burst To Precharge, sets open page interval */
242 #define CFG_REFREC 8 /* Refresh to activate interval */
243 #define CFG_RDLAT 4 /* data latency from read command */
244 #define CFG_PRETOACT 3 /* Precharge to activate interval */
245 #define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
246 #define CFG_ACTORW 2 /* Activate to R/W */
247 #define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
248 #define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
250 #define CFG_REGISTERD_TYPE_BUFFER 1
252 #define CFG_REGDIMM 0
255 /* memory bank settings*/
257 * only bits 20-29 are actually used from these vales to set the
258 * start/end address the upper two bits will be 0, and the lower 20
259 * bits will be set to 0x00000 for a start address, or 0xfffff for an
262 #define CFG_BANK0_START 0x00000000
263 #define CFG_BANK0_END 0x01FFFFFF
264 #define CFG_BANK0_ENABLE 1
265 #define CFG_BANK1_START 0x02000000
266 #define CFG_BANK1_END 0x02ffffff
267 #define CFG_BANK1_ENABLE 0
268 #define CFG_BANK2_START 0x03f00000
269 #define CFG_BANK2_END 0x03ffffff
270 #define CFG_BANK2_ENABLE 0
271 #define CFG_BANK3_START 0x04000000
272 #define CFG_BANK3_END 0x04ffffff
273 #define CFG_BANK3_ENABLE 0
274 #define CFG_BANK4_START 0x05000000
275 #define CFG_BANK4_END 0x05FFFFFF
276 #define CFG_BANK4_ENABLE 0
277 #define CFG_BANK5_START 0x06000000
278 #define CFG_BANK5_END 0x06FFFFFF
279 #define CFG_BANK5_ENABLE 0
280 #define CFG_BANK6_START 0x07000000
281 #define CFG_BANK6_END 0x07FFFFFF
282 #define CFG_BANK6_ENABLE 0
283 #define CFG_BANK7_START 0x08000000
284 #define CFG_BANK7_END 0x08FFFFFF
285 #define CFG_BANK7_ENABLE 0
287 * Memory bank enable bitmask, specifying which of the banks defined above
288 are actually present. MSB is for bank #7, LSB is for bank #0.
290 #define CFG_BANK_ENABLE 0x01
292 #define CFG_ODCR 0xff /* configures line driver impedances, */
293 /* see 8240 book for bit definitions */
294 #define CFG_PGMAX 0x32 /* how long the 8240 retains the */
295 /* currently accessed page in memory */
296 /* see 8240 book for details */
298 /* SDRAM 0 - 256MB */
299 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
300 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
302 /* stack in DCACHE @ 1GB (no backing mem) */
303 #if defined(USE_DINK32)
304 #define CFG_IBAT1L (0x40000000 | BATL_PP_00 )
305 #define CFG_IBAT1U (0x40000000 | BATU_BL_128K )
307 #define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
308 #define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
312 #define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
313 #define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
315 /* Flash, config addrs, etc */
316 #define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
317 #define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
319 #define CFG_DBAT0L CFG_IBAT0L
320 #define CFG_DBAT0U CFG_IBAT0U
321 #define CFG_DBAT1L CFG_IBAT1L
322 #define CFG_DBAT1U CFG_IBAT1U
323 #define CFG_DBAT2L CFG_IBAT2L
324 #define CFG_DBAT2U CFG_IBAT2U
325 #define CFG_DBAT3L CFG_IBAT3L
326 #define CFG_DBAT3U CFG_IBAT3U
329 * For booting Linux, the board info and command line data
330 * have to be in the first 8 MB of memory, since this is
331 * the maximum mapped by the Linux kernel during initialization.
333 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
334 /*-----------------------------------------------------------------------
337 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
338 #define CFG_MAX_FLASH_SECT 20 /* max number of sectors on one chip */
340 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
341 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
343 #define CFG_FLASH_CHECKSUM
345 /*-----------------------------------------------------------------------
346 * Cache Configuration
348 #define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */
349 #if defined(CONFIG_CMD_KGDB)
350 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
355 * Internal Definitions
359 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
360 #define BOOTFLAG_WARM 0x02 /* Software reboot */
362 /* values according to the manual */
364 #define CONFIG_DRAM_50MHZ 1
365 #define CONFIG_SDRAM_50MHZ
367 #define CONFIG_DISK_SPINUP_TIME 1000000
370 #endif /* __CONFIG_H */