2 * Config file for Compulab CM-FX6 board
4 * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
6 * Author: Nikita Kiryanov <nikita@compulab.co.il>
8 * SPDX-License-Identifier: GPL-2.0+
11 #ifndef __CONFIG_CM_FX6_H
12 #define __CONFIG_CM_FX6_H
14 #include <asm/arch/imx-regs.h>
15 #include <config_distro_defaults.h>
16 #include "mx6_common.h"
19 #define CONFIG_SYS_LITTLE_ENDIAN
20 #define CONFIG_MACH_TYPE 4273
22 #ifndef CONFIG_SPL_BUILD
26 #define CONFIG_DM_GPIO
27 #define CONFIG_CMD_GPIO
29 #define CONFIG_DM_SERIAL
30 #define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
33 /* Display information on boot */
34 #define CONFIG_DISPLAY_CPUINFO
35 #define CONFIG_DISPLAY_BOARDINFO
36 #define CONFIG_TIMESTAMP
39 #include <config_cmd_default.h>
40 #define CONFIG_CMD_GREPENV
41 #undef CONFIG_CMD_FLASH
42 #undef CONFIG_CMD_LOADB
43 #undef CONFIG_CMD_LOADS
44 #undef CONFIG_CMD_XIMG
45 #undef CONFIG_CMD_FPGA
46 #undef CONFIG_CMD_IMLS
50 #define CONFIG_CMD_MMC
51 #define CONFIG_GENERIC_MMC
52 #define CONFIG_FSL_ESDHC
53 #define CONFIG_FSL_USDHC
54 #define CONFIG_SYS_FSL_USDHC_NUM 3
55 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
58 #define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR
59 #define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR
60 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
61 #define CONFIG_NR_DRAM_BANKS 2
62 #define CONFIG_SYS_MEMTEST_START 0x10000000
63 #define CONFIG_SYS_MEMTEST_END 0x10010000
64 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
65 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
66 #define CONFIG_SYS_INIT_SP_OFFSET \
67 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
68 #define CONFIG_SYS_INIT_SP_ADDR \
69 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
72 #define CONFIG_MXC_UART
73 #define CONFIG_MXC_UART_BASE UART4_BASE
74 #define CONFIG_BAUDRATE 115200
75 #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
78 #define CONFIG_SYS_PROMPT "CM-FX6 # "
79 #define CONFIG_SYS_CBSIZE 1024
80 #define CONFIG_SYS_MAXARGS 16
81 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
82 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
83 sizeof(CONFIG_SYS_PROMPT) + 16)
86 #define CONFIG_SYS_NO_FLASH
88 #define CONFIG_SF_DEFAULT_BUS 0
89 #define CONFIG_SF_DEFAULT_CS 0
90 #define CONFIG_SF_DEFAULT_SPEED 25000000
91 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
94 #define CONFIG_ENV_OVERWRITE
95 #define CONFIG_ENV_IS_IN_SPI_FLASH
96 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
97 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
98 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
99 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
100 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
101 #define CONFIG_ENV_SIZE (8 * 1024)
102 #define CONFIG_ENV_OFFSET (768 * 1024)
104 #define CONFIG_EXTRA_ENV_SETTINGS \
105 "kernel=uImage-cm-fx6\0" \
107 "loadaddr=0x10800000\0" \
108 "fdtaddr=0x11000000\0" \
109 "console=ttymxc3,115200\0" \
111 "bootscr=boot.scr\0" \
112 "bootm_low=18000000\0" \
113 "video_hdmi=mxcfb0:dev=hdmi,1920x1080M-32@50,if=RGB32\0" \
114 "video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \
115 "fdtfile=cm-fx6.dtb\0" \
116 "doboot=bootm ${loadaddr}\0" \
118 "setboottypez=setenv kernel zImage-cm-fx6;" \
119 "setenv doboot bootz ${loadaddr} - ${fdtaddr};" \
120 "setenv loadfdt true;\0" \
121 "setboottypem=setenv kernel uImage-cm-fx6;" \
122 "setenv doboot bootm ${loadaddr};" \
123 "setenv loadfdt false;\0"\
124 "run_eboot=echo Starting EBOOT ...; "\
125 "mmc dev ${mmcdev} && " \
126 "mmc rescan && mmc read 10042000 a 400 && go 10042000\0" \
128 "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
129 "loadmmcbootscript=load mmc ${mmcdev} ${loadaddr} ${bootscr}\0" \
130 "mmcbootscript=echo Running bootscript from mmc ...; "\
131 "source ${loadaddr}\0" \
132 "mmcargs=setenv bootargs console=${console} " \
135 "mmcloadkernel=load mmc ${mmcdev} ${loadaddr} ${kernel}\0" \
136 "mmcloadfdt=load mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \
137 "mmcboot=echo Booting from mmc ...; " \
141 "sataroot=/dev/sda2 rw rootwait\0" \
142 "sataargs=setenv bootargs console=${console} " \
143 "root=${sataroot} " \
145 "loadsatabootscript=load sata ${satadev} ${loadaddr} ${bootscr}\0" \
146 "satabootscript=echo Running bootscript from sata ...; " \
147 "source ${loadaddr}\0" \
148 "sataloadkernel=load sata ${satadev} ${loadaddr} ${kernel}\0" \
149 "sataloadfdt=load sata ${satadev} ${fdtaddr} ${fdtfile}\0" \
150 "sataboot=echo Booting from sata ...; "\
153 "nandroot=/dev/mtdblock4 rw\0" \
154 "nandrootfstype=ubifs\0" \
155 "nandargs=setenv bootargs console=${console} " \
156 "root=${nandroot} " \
157 "rootfstype=${nandrootfstype} " \
159 "nandloadfdt=nand read ${fdtaddr} 780000 80000;\0" \
160 "nandboot=echo Booting from nand ...; " \
162 "nand read ${loadaddr} 0 780000; " \
163 "if ${loadfdt}; then " \
167 "boot=mmc dev ${mmcdev}; " \
168 "if mmc rescan; then " \
169 "if run loadmmcbootscript; then " \
170 "run mmcbootscript;" \
172 "if run mmcloadkernel; then " \
173 "if ${loadfdt}; then " \
180 "if sata init; then " \
181 "if run loadsatabootscript; then " \
182 "run satabootscript;" \
184 "if run sataloadkernel; then " \
185 "if ${loadfdt}; then " \
186 "run sataloadfdt; " \
194 #define CONFIG_BOOTCOMMAND \
195 "run setboottypem; run boot"
199 #define CONFIG_MXC_SPI
200 #define CONFIG_SPI_FLASH
201 #define CONFIG_SPI_FLASH_ATMEL
202 #define CONFIG_SPI_FLASH_EON
203 #define CONFIG_SPI_FLASH_GIGADEVICE
204 #define CONFIG_SPI_FLASH_MACRONIX
205 #define CONFIG_SPI_FLASH_SPANSION
206 #define CONFIG_SPI_FLASH_STMICRO
207 #define CONFIG_SPI_FLASH_SST
208 #define CONFIG_SPI_FLASH_WINBOND
211 #ifndef CONFIG_SPL_BUILD
212 #define CONFIG_CMD_NAND
213 #define CONFIG_SYS_NAND_BASE 0x40000000
214 #define CONFIG_SYS_NAND_MAX_CHIPS 1
215 #define CONFIG_SYS_MAX_NAND_DEVICE 1
216 #define CONFIG_NAND_MXS
217 #define CONFIG_SYS_NAND_ONFI_DETECTION
218 /* APBH DMA is required for NAND support */
219 #define CONFIG_APBH_DMA
220 #define CONFIG_APBH_DMA_BURST
221 #define CONFIG_APBH_DMA_BURST8
225 #define CONFIG_FEC_MXC
226 #define CONFIG_FEC_MXC_PHYADDR 0
227 #define CONFIG_FEC_XCV_TYPE RGMII
228 #define IMX_FEC_BASE ENET_BASE_ADDR
229 #define CONFIG_PHYLIB
230 #define CONFIG_PHY_ATHEROS
232 #define CONFIG_ETHPRIME "FEC0"
233 #define CONFIG_ARP_TIMEOUT 200UL
234 #define CONFIG_NET_RETRY_COUNT 5
237 #define CONFIG_CMD_USB
238 #define CONFIG_USB_EHCI
239 #define CONFIG_USB_EHCI_MX6
240 #define CONFIG_USB_STORAGE
241 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
242 #define CONFIG_MXC_USB_FLAGS 0
243 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
244 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
247 #define CONFIG_CMD_I2C
248 #define CONFIG_SYS_I2C
249 #define CONFIG_SYS_I2C_MXC
250 #define CONFIG_SYS_I2C_SPEED 100000
251 #define CONFIG_SYS_MXC_I2C3_SPEED 400000
253 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
254 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
255 #define CONFIG_SYS_I2C_EEPROM_BUS 2
258 #define CONFIG_CMD_SATA
259 #define CONFIG_SYS_SATA_MAX_DEVICE 1
260 #define CONFIG_LIBATA
262 #define CONFIG_DWC_AHSATA
263 #define CONFIG_DWC_AHSATA_PORT_ID 0
264 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
267 #define CONFIG_MXC_GPIO
270 #define CONFIG_ZERO_BOOTDELAY_CHECK
271 #define CONFIG_LOADADDR 0x10800000
272 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
273 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
274 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
275 #define CONFIG_SETUP_MEMORY_TAGS
276 #define CONFIG_INITRD_TAG
277 #define CONFIG_REVISION_TAG
278 #define CONFIG_SERIAL_TAG
281 #define CONFIG_SYS_GENERIC_BOARD
282 #define CONFIG_STACKSIZE (128 * 1024)
283 #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
284 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */
285 #define CONFIG_OF_BOARD_SETUP
288 #include "imx6_spl.h"
289 #define CONFIG_SPL_BOARD_INIT
290 #define CONFIG_SPL_MMC_SUPPORT
291 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x80 /* offset 64 kb */
292 #define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS / 2 * 1024)
293 #define CONFIG_SPL_SPI_SUPPORT
294 #define CONFIG_SPL_SPI_FLASH_SUPPORT
295 #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
296 #define CONFIG_SPL_SPI_LOAD
298 #endif /* __CONFIG_CM_FX6_H */