include/configs/colibri_pxa270.h

   1 /*
   2  * Toradex Colibri PXA270 configuration file
   3  *
   4  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Board Configuration Options
  14  */
  15 #define CONFIG_CPU_PXA27X               1       /* Marvell PXA270 CPU */
  16 #define CONFIG_SYS_TEXT_BASE            0x0
  17
  18 /*
  19  * Environment settings
  20  */
  21 #define CONFIG_ENV_OVERWRITE
  22 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)
  23 #define CONFIG_ARCH_CPU_INIT
  24 #define CONFIG_BOOTCOMMAND                                              \
  25         "if mmc init && fatload mmc 0 0xa0000000 uImage; then "         \
  26                 "bootm 0xa0000000; "                                    \
  27         "fi; "                                                          \
  28         "if usb reset && fatload usb 0 0xa0000000 uImage; then "        \
  29                 "bootm 0xa0000000; "                                    \
  30         "fi; "                                                          \
  31         "bootm 0x80000;"
  32 #define CONFIG_BOOTARGS                 "console=tty0 console=ttyS0,115200"
  33 #define CONFIG_TIMESTAMP
  34 #define CONFIG_BOOTDELAY                2       /* Autoboot delay */
  35 #define CONFIG_CMDLINE_TAG
  36 #define CONFIG_SETUP_MEMORY_TAGS
  37 #define CONFIG_LZMA                     /* LZMA compression support */
  38 #define CONFIG_OF_LIBFDT
  39
  40 /*
  41  * Serial Console Configuration
  42  */
  43 #define CONFIG_PXA_SERIAL
  44 #define CONFIG_FFUART                   1
  45 #define CONFIG_CONS_INDEX               3
  46 #define CONFIG_BAUDRATE                 115200
  47
  48 /*
  49  * Bootloader Components Configuration
  50  */
  51 #include <config_cmd_default.h>
  52
  53 #define CONFIG_CMD_NET
  54 #define CONFIG_CMD_ENV
  55 #undef  CONFIG_CMD_IMLS
  56 #define CONFIG_CMD_MMC
  57 #define CONFIG_CMD_USB
  58 #define CONFIG_CMD_FLASH
  59
  60 /*
  61  * Networking Configuration
  62  *  chip on the Voipac PXA270 board
  63  */
  64 #ifdef  CONFIG_CMD_NET
  65 #define CONFIG_CMD_PING
  66 #define CONFIG_CMD_DHCP
  67
  68 #define CONFIG_DRIVER_DM9000            1
  69 #define CONFIG_DM9000_BASE              0x08000000
  70 #define DM9000_IO                       (CONFIG_DM9000_BASE)
  71 #define DM9000_DATA                     (CONFIG_DM9000_BASE + 4)
  72 #define CONFIG_NET_RETRY_COUNT          10
  73
  74 #define CONFIG_BOOTP_BOOTFILESIZE
  75 #define CONFIG_BOOTP_BOOTPATH
  76 #define CONFIG_BOOTP_GATEWAY
  77 #define CONFIG_BOOTP_HOSTNAME
  78 #endif
  79
  80 /*
  81  * HUSH Shell Configuration
  82  */
  83 #define CONFIG_SYS_HUSH_PARSER          1
  84
  85 #define CONFIG_SYS_LONGHELP
  86 #ifdef  CONFIG_SYS_HUSH_PARSER
  87 #define CONFIG_SYS_PROMPT               "$ "
  88 #else
  89 #endif
  90 #define CONFIG_SYS_CBSIZE               256
  91 #define CONFIG_SYS_PBSIZE               \
  92         (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
  93 #define CONFIG_SYS_MAXARGS              16
  94 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
  95 #define CONFIG_SYS_DEVICE_NULLDEV       1
  96 #define CONFIG_CMDLINE_EDITING          1
  97 #define CONFIG_AUTO_COMPLETE            1
  98
  99
 100 /*
 101  * Clock Configuration
 102  */
 103 #define CONFIG_SYS_CPUSPEED             0x290           /* 520MHz */
 104
 105 /*
 106  * DRAM Map
 107  */
 108 #define CONFIG_NR_DRAM_BANKS            1               /* We have 1 bank of DRAM */
 109 #define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
 110 #define PHYS_SDRAM_1_SIZE               0x04000000      /* 64 MB */
 111
 112 #define CONFIG_SYS_DRAM_BASE            0xa0000000      /* CS0 */
 113 #define CONFIG_SYS_DRAM_SIZE            0x04000000      /* 64 MB DRAM */
 114
 115 #define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on */
 116 #define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM */
 117
 118 #define CONFIG_SYS_LOAD_ADDR            PHYS_SDRAM_1
 119 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 120 #define CONFIG_SYS_INIT_SP_ADDR         0x5c010000
 121
 122 /*
 123  * NOR FLASH
 124  */
 125 #ifdef  CONFIG_CMD_FLASH
 126 #define PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
 127 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 128
 129 #define CONFIG_SYS_FLASH_CFI
 130 #define CONFIG_FLASH_CFI_DRIVER         1
 131
 132 #define CONFIG_SYS_MAX_FLASH_SECT       (4 + 255)
 133 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 134
 135 #define CONFIG_SYS_FLASH_ERASE_TOUT     (25 * CONFIG_SYS_HZ)
 136 #define CONFIG_SYS_FLASH_WRITE_TOUT     (25 * CONFIG_SYS_HZ)
 137
 138 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 139 #define CONFIG_SYS_FLASH_PROTECTION             1
 140
 141 #define CONFIG_ENV_IS_IN_FLASH          1
 142
 143 #else   /* No flash */
 144 #define CONFIG_SYS_NO_FLASH
 145 #define CONFIG_SYS_ENV_IS_NOWHERE
 146 #endif
 147
 148 #define CONFIG_SYS_MONITOR_BASE         0x0
 149 #define CONFIG_SYS_MONITOR_LEN          0x80000
 150
 151 #define CONFIG_ENV_ADDR                 \
 152                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 153 #define CONFIG_ENV_SIZE                 0x40000
 154 #define CONFIG_ENV_SECT_SIZE            0x40000
 155 #define CONFIG_ENV_ADDR_REDUND          (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 156 #define CONFIG_ENV_SIZE_REDUND          (CONFIG_ENV_SIZE)
 157
 158 /*
 159  * GPIO settings
 160  */
 161 #define CONFIG_SYS_GPSR0_VAL    0x00000000
 162 #define CONFIG_SYS_GPSR1_VAL    0x00020000
 163 #define CONFIG_SYS_GPSR2_VAL    0x0002C000
 164 #define CONFIG_SYS_GPSR3_VAL    0x00000000
 165
 166 #define CONFIG_SYS_GPCR0_VAL    0x00000000
 167 #define CONFIG_SYS_GPCR1_VAL    0x00000000
 168 #define CONFIG_SYS_GPCR2_VAL    0x00000000
 169 #define CONFIG_SYS_GPCR3_VAL    0x00000000
 170
 171 #define CONFIG_SYS_GPDR0_VAL    0x08000000
 172 #define CONFIG_SYS_GPDR1_VAL    0x0002A981
 173 #define CONFIG_SYS_GPDR2_VAL    0x0202FC00
 174 #define CONFIG_SYS_GPDR3_VAL    0x00000000
 175
 176 #define CONFIG_SYS_GAFR0_L_VAL  0x00100000
 177 #define CONFIG_SYS_GAFR0_U_VAL  0x00C00010
 178 #define CONFIG_SYS_GAFR1_L_VAL  0x999A901A
 179 #define CONFIG_SYS_GAFR1_U_VAL  0xAAA00008
 180 #define CONFIG_SYS_GAFR2_L_VAL  0xAAAAAAAA
 181 #define CONFIG_SYS_GAFR2_U_VAL  0x0109A000
 182 #define CONFIG_SYS_GAFR3_L_VAL  0x54000300
 183 #define CONFIG_SYS_GAFR3_U_VAL  0x00024001
 184
 185 #define CONFIG_SYS_PSSR_VAL     0x30
 186
 187 /*
 188  * Clock settings
 189  */
 190 #define CONFIG_SYS_CKEN         0x00500240
 191 #define CONFIG_SYS_CCCR         0x02000290
 192
 193 /*
 194  * Memory settings
 195  */
 196 #define CONFIG_SYS_MSC0_VAL     0x000095f2
 197 #define CONFIG_SYS_MSC1_VAL     0x00007ff4
 198 #define CONFIG_SYS_MSC2_VAL     0x00000000
 199 #define CONFIG_SYS_MDCNFG_VAL   0x08000ac9
 200 #define CONFIG_SYS_MDREFR_VAL   0x2013e01e
 201 #define CONFIG_SYS_MDMRS_VAL    0x00320032
 202 #define CONFIG_SYS_FLYCNFG_VAL  0x00000000
 203 #define CONFIG_SYS_SXCNFG_VAL   0x40044004
 204
 205 /*
 206  * PCMCIA and CF Interfaces
 207  */
 208 #define CONFIG_SYS_MECR_VAL     0x00000001
 209 #define CONFIG_SYS_MCMEM0_VAL   0x00014307
 210 #define CONFIG_SYS_MCMEM1_VAL   0x00014307
 211 #define CONFIG_SYS_MCATT0_VAL   0x0001c787
 212 #define CONFIG_SYS_MCATT1_VAL   0x0001c787
 213 #define CONFIG_SYS_MCIO0_VAL    0x0001430f
 214 #define CONFIG_SYS_MCIO1_VAL    0x0001430f
 215
 216 #include "pxa-common.h"
 217
 218 #endif  /* __CONFIG_H */