2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * Corenet DS style board configuration file
29 #include "../board/freescale/common/ics307_clk.h"
31 #ifdef CONFIG_RAMBOOT_PBL
32 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
33 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
36 #ifdef CONFIG_SRIOBOOT_SLAVE
37 /* Set 1M boot space */
38 #define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
39 #define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS \
40 (0x300000000ull | CONFIG_SYS_SRIOBOOT_SLAVE_ADDR)
41 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
42 #define CONFIG_SYS_NO_FLASH
45 /* High Level Configuration Options */
47 #define CONFIG_E500 /* BOOKE e500 family */
48 #define CONFIG_E500MC /* BOOKE e500mc family */
49 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
50 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
51 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
52 #define CONFIG_MP /* support multiple processors */
54 #ifndef CONFIG_SYS_TEXT_BASE
55 #define CONFIG_SYS_TEXT_BASE 0xeff80000
58 #ifndef CONFIG_RESET_VECTOR_ADDRESS
59 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
62 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
63 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
64 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
65 #define CONFIG_PCI /* Enable PCI/PCIE */
66 #define CONFIG_PCIE1 /* PCIE controler 1 */
67 #define CONFIG_PCIE2 /* PCIE controler 2 */
68 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
69 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
71 #define CONFIG_SYS_SRIO
72 #define CONFIG_SRIO1 /* SRIO port 1 */
73 #define CONFIG_SRIO2 /* SRIO port 2 */
75 #define CONFIG_FSL_LAW /* Use common FSL init code */
77 #define CONFIG_ENV_OVERWRITE
79 #ifdef CONFIG_SYS_NO_FLASH
80 #define CONFIG_ENV_IS_NOWHERE
82 #define CONFIG_FLASH_CFI_DRIVER
83 #define CONFIG_SYS_FLASH_CFI
84 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
87 #if defined(CONFIG_SPIFLASH)
88 #define CONFIG_SYS_EXTRA_ENV_RELOC
89 #define CONFIG_ENV_IS_IN_SPI_FLASH
90 #define CONFIG_ENV_SPI_BUS 0
91 #define CONFIG_ENV_SPI_CS 0
92 #define CONFIG_ENV_SPI_MAX_HZ 10000000
93 #define CONFIG_ENV_SPI_MODE 0
94 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
95 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
96 #define CONFIG_ENV_SECT_SIZE 0x10000
97 #elif defined(CONFIG_SDCARD)
98 #define CONFIG_SYS_EXTRA_ENV_RELOC
99 #define CONFIG_ENV_IS_IN_MMC
100 #define CONFIG_FSL_FIXED_MMC_LOCATION
101 #define CONFIG_SYS_MMC_ENV_DEV 0
102 #define CONFIG_ENV_SIZE 0x2000
103 #define CONFIG_ENV_OFFSET (512 * 1097)
104 #elif defined(CONFIG_NAND)
105 #define CONFIG_SYS_EXTRA_ENV_RELOC
106 #define CONFIG_ENV_IS_IN_NAND
107 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
108 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
109 #elif defined(CONFIG_ENV_IS_NOWHERE)
110 #define CONFIG_ENV_SIZE 0x2000
112 #define CONFIG_ENV_IS_IN_FLASH
113 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
114 #define CONFIG_ENV_SIZE 0x2000
115 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
118 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
121 * These can be toggled for performance analysis, otherwise use default.
123 #define CONFIG_SYS_CACHE_STASHING
124 #define CONFIG_BACKSIDE_L2_CACHE
125 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
126 #define CONFIG_BTB /* toggle branch predition */
127 #define CONFIG_DDR_ECC
128 #ifdef CONFIG_DDR_ECC
129 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
130 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
133 #define CONFIG_ENABLE_36BIT_PHYS
135 #ifdef CONFIG_PHYS_64BIT
136 #define CONFIG_ADDR_MAP
137 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
140 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
141 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
142 #define CONFIG_SYS_MEMTEST_END 0x00400000
143 #define CONFIG_SYS_ALT_MEMTEST
144 #define CONFIG_PANIC_HANG /* do not reset board on panic */
147 * Config the L3 Cache as L3 SRAM
149 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
150 #ifdef CONFIG_PHYS_64BIT
151 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
153 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
155 #define CONFIG_SYS_L3_SIZE (1024 << 10)
156 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
158 #ifdef CONFIG_PHYS_64BIT
159 #define CONFIG_SYS_DCSRBAR 0xf0000000
160 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
164 #define CONFIG_ID_EEPROM
165 #define CONFIG_SYS_I2C_EEPROM_NXID
166 #define CONFIG_SYS_EEPROM_BUS_NUM 0
167 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
168 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
173 #define CONFIG_VERY_BIG_RAM
174 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
175 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
177 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
178 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
180 #define CONFIG_DDR_SPD
181 #define CONFIG_FSL_DDR3
183 #ifdef CONFIG_P3060QDS
184 #define CONFIG_SYS_SPD_BUS_NUM 0
186 #define CONFIG_SYS_SPD_BUS_NUM 1
188 #define SPD_EEPROM_ADDRESS1 0x51
189 #define SPD_EEPROM_ADDRESS2 0x52
190 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
191 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
194 * Local Bus Definitions
197 /* Set the local bus clock 1/8 of platform clock */
198 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
200 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */
201 #ifdef CONFIG_PHYS_64BIT
202 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
204 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
207 #define CONFIG_SYS_FLASH_BR_PRELIM \
208 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
210 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
211 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
213 #define CONFIG_SYS_BR1_PRELIM \
214 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
215 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
217 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
218 #ifdef CONFIG_PHYS_64BIT
219 #define PIXIS_BASE_PHYS 0xfffdf0000ull
221 #define PIXIS_BASE_PHYS PIXIS_BASE
224 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
225 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
227 #define PIXIS_LBMAP_SWITCH 7
228 #define PIXIS_LBMAP_MASK 0xf0
229 #define PIXIS_LBMAP_SHIFT 4
230 #define PIXIS_LBMAP_ALTBANK 0x40
232 #define CONFIG_SYS_FLASH_QUIET_TEST
233 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
235 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
236 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
237 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
238 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
240 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
242 #if defined(CONFIG_RAMBOOT_PBL)
243 #define CONFIG_SYS_RAMBOOT
247 #ifdef CONFIG_NAND_FSL_ELBC
248 #define CONFIG_SYS_NAND_BASE 0xffa00000
249 #ifdef CONFIG_PHYS_64BIT
250 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
252 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
255 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
256 #define CONFIG_SYS_MAX_NAND_DEVICE 1
257 #define CONFIG_MTD_NAND_VERIFY_WRITE
258 #define CONFIG_CMD_NAND
259 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
261 /* NAND flash config */
262 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
263 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
264 | BR_PS_8 /* Port Size = 8 bit */ \
265 | BR_MS_FCM /* MSEL = FCM */ \
267 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
268 | OR_FCM_PGS /* Large Page*/ \
277 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
278 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
279 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
280 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
282 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
283 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
284 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
285 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
288 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
289 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
290 #endif /* CONFIG_NAND_FSL_ELBC */
292 #define CONFIG_SYS_FLASH_EMPTY_INFO
293 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
294 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
296 #define CONFIG_BOARD_EARLY_INIT_F
297 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
298 #define CONFIG_MISC_INIT_R
300 #define CONFIG_HWCONFIG
302 /* define to use L1 as initial stack */
303 #define CONFIG_L1_INIT_RAM
304 #define CONFIG_SYS_INIT_RAM_LOCK
305 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
306 #ifdef CONFIG_PHYS_64BIT
307 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
308 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
309 /* The assembler doesn't like typecast */
310 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
311 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
312 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
314 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
315 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
316 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
318 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
320 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
321 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
323 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
324 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
326 /* Serial Port - controlled on board with jumper J8
330 #define CONFIG_CONS_INDEX 1
331 #define CONFIG_SYS_NS16550
332 #define CONFIG_SYS_NS16550_SERIAL
333 #define CONFIG_SYS_NS16550_REG_SIZE 1
334 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
336 #define CONFIG_SYS_BAUDRATE_TABLE \
337 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
339 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
340 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
341 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
342 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
344 /* Use the HUSH parser */
345 #define CONFIG_SYS_HUSH_PARSER
346 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
348 /* pass open firmware flat tree */
349 #define CONFIG_OF_LIBFDT
350 #define CONFIG_OF_BOARD_SETUP
351 #define CONFIG_OF_STDOUT_VIA_ALIAS
353 /* new uImage format support */
355 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
358 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
359 #define CONFIG_HARD_I2C /* I2C with hardware support */
360 #define CONFIG_I2C_MULTI_BUS
361 #define CONFIG_I2C_CMD_TREE
362 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
363 #define CONFIG_SYS_I2C_SLAVE 0x7F
364 #define CONFIG_SYS_I2C_OFFSET 0x118000
365 #define CONFIG_SYS_I2C2_OFFSET 0x118100
370 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
371 #ifdef CONFIG_PHYS_64BIT
372 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
374 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
376 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
378 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
379 #ifdef CONFIG_PHYS_64BIT
380 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
382 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
384 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
389 #ifdef CONFIG_SRIOBOOT_MASTER
390 /* master port for srioboot*/
391 #define CONFIG_SRIOBOOT_MASTER_PORT 0
392 /* #define CONFIG_SRIOBOOT_MASTER_PORT 1 */
394 * for slave u-boot IMAGE instored in master memory space,
395 * PHYS must be aligned based on the SIZE
397 #define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 0xfef080000ull
398 #define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 0xfff80000ull
399 #define CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE 0x80000 /* 512K */
400 #define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 0xfef080000ull
401 #define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 0x3fff80000ull
403 * for slave UCODE instored in master memory space,
404 * PHYS must be aligned based on the SIZE
406 #define CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS 0xfef020000ull
407 #define CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS 0x3ffe00000ull
408 #define CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE 0x10000 /* 64K */
414 #ifdef CONFIG_SRIOBOOT_SLAVE
415 /* slave port for srioboot */
416 #define CONFIG_SRIOBOOT_SLAVE_PORT0
417 /* #define CONFIG_SRIOBOOT_SLAVE_PORT1 */
418 #define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR 0xFFE00000
419 #define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS \
420 (0x300000000ull | CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR)
424 * eSPI - Enhanced SPI
426 #define CONFIG_FSL_ESPI
427 #define CONFIG_SPI_FLASH
428 #define CONFIG_SPI_FLASH_SPANSION
429 #define CONFIG_CMD_SF
430 #define CONFIG_SF_DEFAULT_SPEED 10000000
431 #define CONFIG_SF_DEFAULT_MODE 0
435 * Memory space is mapped 1-1, but I/O space must start from 0.
438 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
439 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
440 #ifdef CONFIG_PHYS_64BIT
441 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
442 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
444 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
445 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
447 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
448 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
449 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
450 #ifdef CONFIG_PHYS_64BIT
451 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
453 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
455 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
457 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
458 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
459 #ifdef CONFIG_PHYS_64BIT
460 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
461 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
463 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
464 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
466 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
467 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
468 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
469 #ifdef CONFIG_PHYS_64BIT
470 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
472 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
474 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
476 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
477 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
478 #ifdef CONFIG_PHYS_64BIT
479 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
480 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
482 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
483 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
485 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
486 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
487 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
488 #ifdef CONFIG_PHYS_64BIT
489 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
491 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
493 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
495 /* controller 4, Base address 203000 */
496 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
497 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
498 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
499 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
500 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
501 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
504 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
505 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
506 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
507 #ifdef CONFIG_PHYS_64BIT
508 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
510 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
512 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
513 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
514 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
515 #ifdef CONFIG_PHYS_64BIT
516 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
518 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
520 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
522 #define CONFIG_SYS_DPAA_FMAN
523 #define CONFIG_SYS_DPAA_PME
524 /* Default address of microcode for the Linux Fman driver */
525 #if defined(CONFIG_SPIFLASH)
527 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
528 * env, so we got 0x110000.
530 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
531 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
532 #elif defined(CONFIG_SDCARD)
534 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
535 * about 545KB (1089 blocks), Env is stored after the image, and the env size is
536 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
538 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
539 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
540 #elif defined(CONFIG_NAND)
541 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
542 #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
543 #elif defined(CONFIG_SRIOBOOT_SLAVE)
545 * Slave has no ucode locally, it can fetch this from remote. When implementing
546 * in two corenet boards, slave's ucode could be stored in master's memory
547 * space, the address can be mapped from slave TLB->slave LAW->
548 * slave SRIO outbound window->master inbound window->master LAW->
549 * the ucode address in master's NOR flash.
551 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
552 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
554 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
555 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000
557 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
558 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
560 #ifdef CONFIG_SYS_DPAA_FMAN
561 #define CONFIG_FMAN_ENET
562 #define CONFIG_PHYLIB_10G
563 #define CONFIG_PHY_VITESSE
564 #define CONFIG_PHY_TERANETICS
568 #define CONFIG_PCI_PNP /* do pci plug-and-play */
571 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
572 #define CONFIG_DOS_PARTITION
573 #endif /* CONFIG_PCI */
576 #ifdef CONFIG_FSL_SATA_V2
577 #define CONFIG_LIBATA
578 #define CONFIG_FSL_SATA
580 #define CONFIG_SYS_SATA_MAX_DEVICE 2
582 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
583 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
585 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
586 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
589 #define CONFIG_CMD_SATA
590 #define CONFIG_DOS_PARTITION
591 #define CONFIG_CMD_EXT2
594 #ifdef CONFIG_FMAN_ENET
595 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
596 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
597 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
598 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
599 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
601 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
602 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
603 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
604 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
605 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
607 #define CONFIG_SYS_TBIPA_VALUE 8
608 #define CONFIG_MII /* MII PHY management */
609 #define CONFIG_ETHPRIME "FM1@DTSEC1"
610 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
616 #define CONFIG_LOADS_ECHO /* echo on for serial download */
617 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
620 * Command line configuration.
622 #include <config_cmd_default.h>
624 #define CONFIG_CMD_DHCP
625 #define CONFIG_CMD_ELF
626 #define CONFIG_CMD_ERRATA
627 #define CONFIG_CMD_GREPENV
628 #define CONFIG_CMD_IRQ
629 #define CONFIG_CMD_I2C
630 #define CONFIG_CMD_MII
631 #define CONFIG_CMD_PING
632 #define CONFIG_CMD_SETEXPR
633 #define CONFIG_CMD_REGINFO
636 #define CONFIG_CMD_PCI
637 #define CONFIG_CMD_NET
643 #define CONFIG_CMD_USB
644 #define CONFIG_USB_STORAGE
645 #define CONFIG_USB_EHCI
646 #define CONFIG_USB_EHCI_FSL
647 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
648 #define CONFIG_CMD_EXT2
649 #define CONFIG_HAS_FSL_DR_USB
652 #define CONFIG_FSL_ESDHC
653 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
654 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
655 #define CONFIG_CMD_MMC
656 #define CONFIG_GENERIC_MMC
657 #define CONFIG_CMD_EXT2
658 #define CONFIG_CMD_FAT
659 #define CONFIG_DOS_PARTITION
663 * Miscellaneous configurable options
665 #define CONFIG_SYS_LONGHELP /* undef to save memory */
666 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
667 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
668 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
669 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
670 #ifdef CONFIG_CMD_KGDB
671 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
673 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
675 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
676 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
677 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
678 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
681 * For booting Linux, the board info and command line data
682 * have to be in the first 64 MB of memory, since this is
683 * the maximum mapped by the Linux kernel during initialization.
685 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
686 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
688 #ifdef CONFIG_CMD_KGDB
689 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
690 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
694 * Environment Configuration
696 #define CONFIG_ROOTPATH "/opt/nfsroot"
697 #define CONFIG_BOOTFILE "uImage"
698 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
700 /* default location for tftp and bootm */
701 #define CONFIG_LOADADDR 1000000
703 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
705 #define CONFIG_BAUDRATE 115200
707 #if defined(CONFIG_P4080DS) || defined(CONFIG_P3060QDS)
708 #define __USB_PHY_TYPE ulpi
710 #define __USB_PHY_TYPE utmi
713 #define CONFIG_EXTRA_ENV_SETTINGS \
714 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
715 "bank_intlv=cs0_cs1;" \
716 "usb1:dr_mode=host,phy_type=" MK_STR(__USB_PHY_TYPE) "\0"\
718 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
719 "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \
720 "tftpflash=tftpboot $loadaddr $uboot && " \
721 "protect off $ubootaddr +$filesize && " \
722 "erase $ubootaddr +$filesize && " \
723 "cp.b $loadaddr $ubootaddr $filesize && " \
724 "protect on $ubootaddr +$filesize && " \
725 "cmp.b $loadaddr $ubootaddr $filesize\0" \
726 "consoledev=ttyS0\0" \
727 "ramdiskaddr=2000000\0" \
728 "ramdiskfile=p4080ds/ramdisk.uboot\0" \
730 "fdtfile=p4080ds/p4080ds.dtb\0" \
734 #define CONFIG_HDBOOT \
735 "setenv bootargs root=/dev/$bdev rw " \
736 "console=$consoledev,$baudrate $othbootargs;" \
737 "tftp $loadaddr $bootfile;" \
738 "tftp $fdtaddr $fdtfile;" \
739 "bootm $loadaddr - $fdtaddr"
741 #define CONFIG_NFSBOOTCOMMAND \
742 "setenv bootargs root=/dev/nfs rw " \
743 "nfsroot=$serverip:$rootpath " \
744 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
745 "console=$consoledev,$baudrate $othbootargs;" \
746 "tftp $loadaddr $bootfile;" \
747 "tftp $fdtaddr $fdtfile;" \
748 "bootm $loadaddr - $fdtaddr"
750 #define CONFIG_RAMBOOTCOMMAND \
751 "setenv bootargs root=/dev/ram rw " \
752 "console=$consoledev,$baudrate $othbootargs;" \
753 "tftp $ramdiskaddr $ramdiskfile;" \
754 "tftp $loadaddr $bootfile;" \
755 "tftp $fdtaddr $fdtfile;" \
756 "bootm $loadaddr $ramdiskaddr $fdtaddr"
758 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
760 #ifdef CONFIG_SECURE_BOOT
761 #include <asm/fsl_secure_boot.h>
764 #endif /* __CONFIG_H */